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| REJ09B0465-0100 16 H8S/20103, H8S/20203, H8S/20223 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/Tiny Series H8S/20103 H8S/20203 H8S/20223 R4F20103 R4F20203 R4F20223 All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.1.00 Revision Date: Oct. 03, 2008 Rev. 1.00 Oct. 03, 2008 Page ii of xxvi Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 1.00 Oct. 03, 2008 Page iii of xxvi General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev. 1.00 Oct. 03, 2008 Page iv of xxvi How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes. When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes. The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the H8S/20103 Group, H8S/20203 Group, H8S/20223 Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. Document Type Data Sheet Hardware Manual Contents Document Title Document No. This manual Overview of hardware and electrical characteristics Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation Detailed descriptions of the CPU and instruction set Examples of applications and sample programs Preliminary report on the specifications of a product, document, etc. H8S/20103 Group H8S/20203 Group H8S/20223 Group Hardware Manual H8S/2600 Series H8S/2000 Series Software Manual Software Manual REJ09B0143 Application Note Renesas Technical Update The latest versions are available from our web site. Rev. 1.00 Oct. 03, 2008 Page v of xxvi 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF (4) (2) 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. Rev. 0.50, 10/04, page 416 of 914 (3) Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. Rev. 1.00 Oct. 03, 2008 Page vi of xxvi 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Bit Chart] Bit: 15 Initial value: R/W: 0 R/W 14 0 R/W 13 12 11 10 0 R 9 1 R 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 Q 0 R/W 3 2 1 0 IFE 0 R/W ASID2 ASID1 ASID0 0 R/W 0 R/W 0 R/W ACMP2 ACMP1 ACMP0 0 R/W 0 R/W 0 R/W [Table of Bits] (1) Bit 15 14 13 to 11 10 9 (2) Bit Name - - ASID2 to ASID0 - - - (3) (4) Description (5) Reserved These bits are always read as 0. Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1. Initial Value R/W 0 0 All 0 0 1 0 R R R/W R R Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "-". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 -: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. R: The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. W: The bit or field is writable. (5) Description Describes the function of the bit or field and specifies the values for writing. Rev. 1.00 Oct. 03, 2008 Page vii of xxvi 4. Description of Abbreviations The abbreviations used in this manual are listed below. * Abbreviations specific to this product Description Bus controller Clock pulse generator Interrupt controller Serial communications interface 16-bit timer pulse unit Watchdog timer Abbreviation BSC CPG INT SCI TPU WDT * Abbreviations other than those listed above Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Description Asynchronous communications interface adapter Bits per second Cyclic redundancy check Direct memory access Direct memory access controller Global System for Mobile Communications High impedance Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) Input/output Infrared Data Association Least significant bit Most significant bit No connection Phase-locked loop Pulse width modulation Special function register Subscriber Identity Module Universal asynchronous receiver/transmitter Voltage-controlled oscillator All trademarks and registered trademarks are the property of their respective owners. Rev. 1.00 Oct. 03, 2008 Page viii of xxvi Contents Section 1 Overview................................................................................................1 1.1 Features................................................................................................................................. 1 1.1.1 Applications .......................................................................................................... 1 1.1.2 Overview of Functions.......................................................................................... 1 List of Products..................................................................................................................... 6 Block Diagram...................................................................................................................... 8 Pin Assignments ................................................................................................................. 11 1.4.1 Pin Functions ...................................................................................................... 14 1.2 1.3 1.4 Section 2 CPU......................................................................................................21 2.1 Features............................................................................................................................... 21 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ................................. 22 2.1.2 Differences from H8/300 CPU ........................................................................... 23 2.1.3 Differences from H8/300H CPU......................................................................... 23 CPU Operating Modes........................................................................................................ 24 2.2.1 Advanced Mode.................................................................................................. 24 Address Space..................................................................................................................... 27 Register Configuration........................................................................................................ 31 2.4.1 General Registers................................................................................................ 32 2.4.2 Program Counter (PC) ........................................................................................ 33 2.4.3 Extended Control Register (EXR) ...................................................................... 33 2.4.4 Condition-Code Register (CCR)......................................................................... 34 2.4.5 Initial Register Values......................................................................................... 36 Data Formats....................................................................................................................... 37 2.5.1 General Register Data Formats ........................................................................... 37 2.5.2 Memory Data Formats ........................................................................................ 39 Instruction Set ..................................................................................................................... 40 2.6.1 Table of Instructions Classified by Function ...................................................... 41 2.6.2 Basic Instruction Formats ................................................................................... 51 Addressing Modes and Effective Address Calculation....................................................... 53 2.7.1 Register Direct--Rn ........................................................................................... 53 2.7.2 Register Indirect--@ERn ................................................................................... 53 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn)............. 54 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn................................................................................................................ 54 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32................................... 54 2.2 2.3 2.4 2.5 2.6 2.7 Rev. 1.00 Oct. 03, 2008 Page ix of xxvi 2.8 2.9 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32................................................................ 55 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) .................................. 55 2.7.8 Memory Indirect--@@aa:8 ............................................................................... 56 2.7.9 Effective Address Calculation ............................................................................ 57 Processing States ................................................................................................................ 59 Usage Notes ........................................................................................................................ 61 2.9.1 TAS Instruction .................................................................................................. 61 2.9.2 STM and LDM Instructions................................................................................ 61 2.9.3 Note on Bit Manipulation Instructions................................................................ 61 2.9.4 EEPMOVE Instruction ....................................................................................... 62 Section 3 Exception Handling ............................................................................. 63 3.1 3.2 3.3 Exception Handling Types and Priority.............................................................................. 63 Exception Handling Sources and Vector Table .................................................................. 63 Reset ................................................................................................................................... 64 3.3.1 Reset Sources...................................................................................................... 64 3.3.2 Reset Exception Handling .................................................................................. 67 3.3.3 Interrupts immediately after Reset...................................................................... 68 3.3.4 On-Chip Peripheral Functions after Reset Release............................................. 68 Trace Exception Handling .................................................................................................. 69 Interrupt Exception Handling ............................................................................................. 70 Trap Instruction Exception Handling.................................................................................. 70 Stack Status after Exception Handling ............................................................................... 71 Usage Note ......................................................................................................................... 72 3.4 3.5 3.6 3.7 3.8 Section 4 Interrupt Controller.............................................................................. 73 4.1 4.2 Features............................................................................................................................... 73 Register Descriptions.......................................................................................................... 75 4.2.1 Interrupt Control Register (INTCR) ................................................................... 76 4.2.2 Interrupt Priority Registers A to I (IPRA to IPRI).............................................. 77 4.2.3 IRQ Enable Register (IER) ................................................................................. 79 4.2.4 IRQ Sense Control Register H and L (ISCRH and ISCRL) ............................... 80 4.2.5 IRQ Status Register (ISR)................................................................................... 83 4.2.6 IRQ Noise Canceler Control Register (INCCR)................................................. 84 4.2.7 Interrupt Vector Offset Register (VOFR) ........................................................... 85 4.2.8 Event Link Interrupt Control Status Register (ELCSR) ..................................... 86 Interrupt Sources................................................................................................................. 87 4.3.1 External Interrupt sources ................................................................................... 87 4.3.2 Internal Interrupts ............................................................................................... 88 Interrupt Exception Handling Vector Table........................................................................ 89 4.3 4.4 Rev. 1.00 Oct. 03, 2008 Page x of xxvi 4.5 4.6 Interrupt Control Modes and Interrupt Operation ............................................................... 96 4.5.1 Interrupt Control Mode 0 .................................................................................... 96 4.5.2 Interrupt Control Mode 2 .................................................................................... 98 4.5.3 Interrupt Exception Handling Sequence ........................................................... 100 4.5.4 Interrupt Response Time................................................................................... 102 4.5.5 DTC Activation by Interrupt............................................................................. 102 Usage Notes ...................................................................................................................... 103 4.6.1 Conflict between Interrupt Generation and Disabling ...................................... 103 4.6.2 Instructions that Disable Interrupts ................................................................... 104 4.6.3 Time when Interrupts are Disabled................................................................... 104 4.6.4 Interrupts during Execution of EEPMOV Instruction....................................... 104 4.6.5 Changing PMR, ISCRH, ISCRL and INCCR................................................... 105 4.6.6 IRQ Status Register (ISR)................................................................................. 105 4.6.7 NMI Pin ............................................................................................................ 106 Section 5 Clock Pulse Generator .......................................................................107 5.1 5.2 Overview........................................................................................................................... 108 Register Descriptions........................................................................................................ 110 5.2.1 Backup Control Register (BACKR) ................................................................. 111 5.2.2 System Clock Control Register (SYSCCR)...................................................... 113 5.2.3 Power-Down Control Register 1 (LPCR1) ....................................................... 115 5.2.4 Power-Down Control Register 2 (LPCR2) ....................................................... 117 5.2.5 Power-Down Control Register 3 (LPCR3) ....................................................... 118 5.2.6 OSC Oscillation Settling Control Status Register (OSCCSR).......................... 120 5.2.7 High-Speed OCO Control Register (HOCR).................................................... 121 5.2.8 High-Speed OCO Trimming Data Protect Register (HOTRMDPR) ................ 122 5.2.9 High-Speed OCO Trimming Data Register 1 (HOTRMDR1).......................... 123 5.2.10 High-Speed OCO Trimming Data Register 2 (HOTRMDR2).......................... 124 5.2.11 High-Speed OCO Trimming Data Register 3 (HOTRMDR3).......................... 124 5.2.12 High-Speed OCO Trimming Data Register 4 (HOTRMDR4).......................... 125 Operation of Selection of System Base Clock .................................................................. 126 5.3.1 Switching System Base Clock to hoco ........................................................... 129 5.3.2 Switching System Base Clock to osc.............................................................. 131 5.3.3 Clock Change Timing ....................................................................................... 132 5.3.4 Backup Operation ............................................................................................. 135 High-Speed On-Chip Oscillator........................................................................................ 139 5.4.1 Procedures for Switching to 32MHz................................................................. 139 5.4.2 Trimming of High-Speed OCO......................................................................... 140 Main Clock Oscillator....................................................................................................... 142 5.5.1 Connecting Crystal Resonator .......................................................................... 142 Rev. 1.00 Oct. 03, 2008 Page xi of xxvi 5.3 5.4 5.5 5.6 5.7 5.8 5.5.2 Connecting Ceramic Resonator ........................................................................ 143 5.5.3 External Clock Input Method............................................................................ 143 Subclock Generator .......................................................................................................... 144 5.6.1 Connecting 32.768-kHz Crystal Resonator ...................................................... 144 5.6.2 Pin Connection when not Using Subclock........................................................ 144 Prescaler............................................................................................................................ 145 Usage Notes ...................................................................................................................... 146 5.8.1 Note on Resonators........................................................................................... 146 5.8.2 Notes on Board Design ..................................................................................... 146 Section 6 Power-Down Modes.......................................................................... 147 6.1 Register Descriptions........................................................................................................ 148 6.1.1 Power-Down Control Registers 1, 2, and 3 (LPCR1, LPCR2, LPCR3) ........... 148 6.1.2 Module Standby Control Register 1 (MSTCR1) .............................................. 148 6.1.3 Module Standby Control Register 2 (MSTCR2) .............................................. 150 6.1.4 Module Standby Control Register 3 (MSTCR3) .............................................. 151 Mode Transitions and States of LSI.................................................................................. 153 6.2.1 Active Mode ..................................................................................................... 155 6.2.2 Sleep Mode ....................................................................................................... 155 6.2.3 Standby Mode................................................................................................... 156 Bus Master Clock Division Function................................................................................ 156 6.3.1 Reset States....................................................................................................... 156 Module Standby Function................................................................................................. 157 PSC Divider Stop Function............................................................................................... 157 6.2 6.3 6.4 6.5 Section 7 ROM .................................................................................................. 159 7.1 7.2 7.3 Overview .......................................................................................................................... 159 Block Configuration ......................................................................................................... 160 CPU Reprogramming Mode ............................................................................................. 163 7.3.1 EW0 Mode........................................................................................................ 165 7.3.2 EW1 Mode........................................................................................................ 165 Register Descriptions........................................................................................................ 166 7.4.1 Flash Memory Control Register 1 (FLMCR1).................................................. 166 7.4.2 Flash Memory Control Register 2 (FLMCR2).................................................. 168 7.4.3 Flash Memory Data Flash Protect Register (DFPR)......................................... 170 7.4.4 Flash Memory Status Register (FLMSTR)....................................................... 171 On-Board Programming ................................................................................................... 174 7.5.1 Boot Mode ........................................................................................................ 174 7.5.2 Specifications of Standard Serial Communication Interface in Boot Mode ..... 180 7.5.3 Programming/Erasing in User Mode ................................................................ 207 7.4 7.5 Rev. 1.00 Oct. 03, 2008 Page xii of xxvi 7.6 7.7 7.8 7.9 Programming/Erasing ....................................................................................................... 208 7.6.1 Software Commands......................................................................................... 208 Protection.......................................................................................................................... 225 7.7.1 Software Protection........................................................................................... 225 7.7.2 Lock-Bit Protection........................................................................................... 225 7.7.3 PROM Programmer Protection/Boot Mode Protection .................................... 226 Programmer Mode ............................................................................................................ 227 Usage Notes ...................................................................................................................... 228 Section 8 RAM ..................................................................................................231 Section 9 Peripheral I/O Mapping Controller....................................................233 9.1 Register Descriptions........................................................................................................ 235 9.1.1 Peripheral Function Mapping Register Write-Protect Register (PMCWPR).... 236 9.1.2 Port Group 1 Peripheral Function Mapping Registers 1 to 4 (PMCRn1 to PMCRn4 (n = 1, 2, 3, 5, and 6)) .................................................. 237 9.1.3 Port Group 2 Peripheral Function Mapping Registers 1 to 4 (PMCRn1 to PMCRn4 (n = 8, 9, and A) .......................................................... 258 Usage Notes ...................................................................................................................... 266 9.2.1 Procedures for Setting Multiplexed Port Functions .......................................... 266 9.2.2 Notes on Setting PMC Registers....................................................................... 266 9.2 Section 10 I/O Ports ...........................................................................................267 10.1 Port 1................................................................................................................................. 267 10.1.1 Port Mode Register 1 (PMR1) .......................................................................... 268 10.1.2 Port Control Register 1 (PCR1) ........................................................................ 269 10.1.3 Port Data Register 1 (PDR1)............................................................................. 270 10.1.4 Port Pull-Up Control Register 1 (PUCR1)........................................................ 271 10.1.5 Port Drive Control Register 1 (PDVR1) ........................................................... 272 Port 2................................................................................................................................. 273 10.2.1 Port Mode Register 2 (PMR2) .......................................................................... 274 10.2.2 Port Control Register 2 (PCR2) ........................................................................ 275 10.2.3 Port Data Register 2 (PDR2)............................................................................. 276 10.2.4 Port Pull-Up Control Register 2 (PUCR2)........................................................ 277 10.2.5 Port Drive Control Register 2 (PDVR2) ........................................................... 278 Port 3................................................................................................................................. 279 10.3.1 Port Mode Register 3 (PMR3) .......................................................................... 280 10.3.2 Port Control Register 3 (PCR3) ........................................................................ 281 10.3.3 Port Data Register 3 (PDR3)............................................................................. 282 10.3.4 Port Pull-Up Control Register 3 (PUCR3)........................................................ 283 Rev. 1.00 Oct. 03, 2008 Page xiii of xxvi 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.3.5 Port Drive Control Register 3 (PDVR3) ........................................................... 284 Port 5................................................................................................................................. 285 10.4.1 Port Mode Register 5 (PMR5) .......................................................................... 286 10.4.2 Port Control Register 5 (PCR5) ........................................................................ 287 10.4.3 Port Data Register 5 (PDR5) ............................................................................ 288 10.4.4 Port Pull-Up Control Register 5 (PUCR5)........................................................ 289 10.4.5 Port Drive Control Register 5 (PDVR5) ........................................................... 290 Port 6................................................................................................................................. 291 10.5.1 Port Mode Register 6 (PMR6) .......................................................................... 292 10.5.2 Port Control Register 6 (PCR6) ........................................................................ 293 10.5.3 Port Data Register 6 (PDR6) ............................................................................ 294 10.5.4 Port Pull-Up Control Register 6 (PUCR6)........................................................ 295 10.5.5 Port Drive Control Register 6 (PDVR6) ........................................................... 296 Port 8................................................................................................................................. 297 10.6.1 Port Mode Register 8 (PMR8) .......................................................................... 298 10.6.2 Port Control Register 8 (PCR8) ........................................................................ 299 10.6.3 Port Data Register 8 (PDR8) ............................................................................ 300 10.6.4 Port Pull-Up Control Register 8 (PUCR8)........................................................ 301 10.6.5 Port Drive Control Register 8 (PDVR8) ........................................................... 302 10.6.6 Notes on Using Port 8....................................................................................... 302 Port 9................................................................................................................................. 303 10.7.1 Port Mode Register 9 (PMR9) .......................................................................... 304 10.7.2 Port Control Register 9 (PCR9) ........................................................................ 305 10.7.3 Port Data Register 9 (PDR9) ............................................................................ 306 10.7.4 Port Pull-Up Control Register 9 (PUCR9)........................................................ 307 10.7.5 Port Drive Control Register 9 (PDVR9) ........................................................... 308 Port A................................................................................................................................ 309 10.8.1 Port Mode Register A (PMRA) ........................................................................ 310 10.8.2 Port Control Register A (PCRA) ...................................................................... 311 10.8.3 Port Data Register A (PDRA)........................................................................... 312 10.8.4 Port Pull-Up Control Register A (PUCRA)...................................................... 313 10.8.5 Port Mode Register A (PMRA) ........................................................................ 314 10.8.6 Port Control Register A (PCRA) ...................................................................... 315 10.8.7 Port Data Register A (PDRA)........................................................................... 316 10.8.8 Port Pull-Up Control Register A (PUCRA)...................................................... 317 10.8.9 Port Mode Register A (PMRA) ........................................................................ 318 10.8.10 Port Control Register A (PCRA) ...................................................................... 319 10.8.11 Port Data Register A (PDRA)........................................................................... 320 10.8.12 Port Pull-Up Control Register A (PUCRA)...................................................... 321 10.8.13 Notes on Using Port A ...................................................................................... 321 Rev. 1.00 Oct. 03, 2008 Page xiv of xxvi Port B ................................................................................................................................ 322 10.9.1 Port Control Register B (PCRB)....................................................................... 323 10.9.2 Port Data Register B (PDRB) ........................................................................... 324 10.9.3 Port Pull-Up Control Register B (PUCRB) ...................................................... 325 10.9.4 Notes on Using Port B ...................................................................................... 325 10.10 Port J ................................................................................................................................. 326 10.10.1 Port Mode Register J (PMRJ) ........................................................................... 327 10.10.2 Port Control Register J (PCRJ) ......................................................................... 328 10.10.3 Port Data Register J (PDRJ) ............................................................................. 329 10.10.4 Port Pull-Up Control Register J (PUCRJ)......................................................... 330 10.9 Section 11 Data Transfer Controller (DTC) ......................................................331 11.1 11.2 Features............................................................................................................................. 331 Register Descriptions........................................................................................................ 333 11.2.1 DTC Mode Register A (MRA) ......................................................................... 334 11.2.2 DTC Mode Register B (MRB).......................................................................... 336 11.2.3 DTC Source Address Register (SAR)............................................................... 337 11.2.4 DTC Destination Address Register (DAR)....................................................... 337 11.2.5 DTC Transfer Count Register A (CRA) ........................................................... 338 11.2.6 DTC Transfer Count Register B (CRB)............................................................ 338 11.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) .................................. 339 11.2.8 DTC Vector Register (DTVECR)..................................................................... 341 Activation Sources............................................................................................................ 342 Location of Register Information and DTC Vector Table ................................................ 344 Operation .......................................................................................................................... 349 11.5.1 Normal Mode.................................................................................................... 351 11.5.2 Repeat Mode ..................................................................................................... 352 11.5.3 Block Transfer Mode ........................................................................................ 353 11.5.4 Chain Transfer .................................................................................................. 354 11.5.5 Interrupt Sources............................................................................................... 355 11.5.6 Operation Timing.............................................................................................. 356 11.5.7 Number of DTC Execution States .................................................................... 357 Procedures for Using DTC................................................................................................ 359 11.6.1 Activation by Interrupt...................................................................................... 359 11.6.2 Activation by Software ..................................................................................... 359 Examples of Use of the DTC ............................................................................................ 360 11.7.1 Normal Mode.................................................................................................... 360 11.7.2 Chain Transfer when Transfer Counter = 0 ...................................................... 361 11.7.3 Software Activation .......................................................................................... 363 Usage Notes ...................................................................................................................... 364 Rev. 1.00 Oct. 03, 2008 Page xv of xxvi 11.3 11.4 11.5 11.6 11.7 11.8 11.8.1 11.8.2 11.8.3 Module Standby Mode Setting ......................................................................... 364 DTCE Bit Setting.............................................................................................. 364 DTC Activation by SCI3, IIC2/SSU and A/D Converter Interrupt Sources..... 364 Section 12 Event Link Controller...................................................................... 365 12.1 12.2 Overview .......................................................................................................................... 365 Register Descriptions........................................................................................................ 367 12.2.1 Event Link Control Register (ELCR) ............................................................... 367 12.2.2 Event Link Setting Registers 0 to 32 (ELSR0 to ELSR32) .............................. 368 12.2.3 Event Link Option Setting Register A (ELOPA).............................................. 372 12.2.4 Event Link Option Setting Register B (ELOPB) .............................................. 373 12.2.5 Event Link Option Setting Register C (ELOPC) .............................................. 373 12.2.6 Port-Group Setting Registers 1 and 2 (PGR1 and PGR2)................................. 374 12.2.7 Port-Group Control Registers 1 and 2 (PGC1 and PGC2)................................ 375 12.2.8 Port Buffer Registers 1 and 2 (PDBF1 and PDBF2)......................................... 376 12.2.9 Event Link Port Setting Registers 0 to 3 (PEL0 to PEL3) ................................ 377 12.2.10 Event-Generation Timer Control Register (ELTMCR) .................................... 378 12.2.11 Event-Generation Timer Interval Setting Register A (ELTMSA) .................... 379 12.2.12 Event-Generation Timer Interval Setting Register B (ELTMSB)..................... 381 12.2.13 Event-Generation Timer Delay Selection Register (ELTMDR)....................... 383 12.2.14 ELC Timer Counter (ELTMCNT).................................................................... 384 Operation .......................................................................................................................... 385 12.3.1 Relation between Interrupt Processing and Event Linking............................... 385 12.3.2 Event Linkage................................................................................................... 385 12.3.3 Operation of Peripheral Timer Modules When Event is Input ......................... 387 12.3.4 Operation of A/D and D/A Converters When Event is Input ........................... 387 12.3.5 Port Operation upon Event Input and Event Generation................................... 388 12.3.6 Event-Generation Timer ................................................................................... 394 12.3.7 Procedure for Linking Events ........................................................................... 396 12.3 Section 13 Timer RA......................................................................................... 397 13.1 13.2 Overview .......................................................................................................................... 397 Register Descriptions........................................................................................................ 398 13.2.1 Timer RA Control Register (TRACR).............................................................. 399 13.2.2 Timer RA I/O Control Register (TRAIOC)...................................................... 401 13.2.3 Timer RA Mode Register (TRAMR)................................................................ 403 13.2.4 Timer RA Interrupt Enable Status Register (TRAIR)....................................... 404 13.2.5 Timer RA Prescaler Register (TRAPRE) ......................................................... 405 13.2.6 Timer RA Timer Register (TRATR) ................................................................ 406 Operation .......................................................................................................................... 407 13.3 Rev. 1.00 Oct. 03, 2008 Page xvi of xxvi 13.4 13.3.1 Operations Common to Various Modes............................................................ 407 13.3.2 Timer Mode ...................................................................................................... 408 13.3.3 Pulse Output Mode ........................................................................................... 408 13.3.4 Event Counter Mode ......................................................................................... 409 13.3.5 Pulse Width Measurement Mode...................................................................... 409 13.3.6 Pulse Cycle Measurement Mode....................................................................... 411 13.3.7 Operation through an Event Link...................................................................... 412 Usage Notes ...................................................................................................................... 414 Section 14 Timer RB .........................................................................................415 14.1 14.2 Overview........................................................................................................................... 415 Register Descriptions........................................................................................................ 416 14.2.1 Timer RB Control Register (TRBCR) .............................................................. 417 14.2.2 Timer RB One-Shot Control Register (TRBOCR) ........................................... 418 14.2.3 Timer RB I/O Control Register (TRBIOC) ...................................................... 419 14.2.4 Timer RB Mode Register (TRBMR) ................................................................ 421 14.2.5 Timer RB Interrupt Enable Status Register (TRBIR) ....................................... 422 14.2.6 Timer RB Prescaler Register (TRBPRE).......................................................... 423 14.2.7 Timer RB Secondary Register (TRBSC) .......................................................... 423 14.2.8 Timer RB Primary Register (TRBPR) .............................................................. 424 Operation .......................................................................................................................... 425 14.3.1 Timer Mode ...................................................................................................... 425 14.3.2 Programmable Waveform Generation Mode .................................................... 426 14.3.3 Programmable One-Shot Generation Mode...................................................... 428 14.3.4 Programmable Wait One-Shot Generation Mode ............................................. 430 14.3.5 Timing at Which Values Take Effect in Prescaler or Counter Depending on TWRC Bit......................................................................................................... 432 14.3.6 TOCNT Settings and Pin State Update Conditions .......................................... 434 14.3.7 Operation through an Event Link...................................................................... 435 Interrupt Request............................................................................................................... 435 Usage Notes ...................................................................................................................... 436 14.3 14.4 14.5 Section 15 Timer RC .........................................................................................437 15.1 15.2 Features............................................................................................................................. 437 Register Descriptions........................................................................................................ 440 15.2.1 Timer RC Mode Register (TRCMR) ................................................................ 441 15.2.2 Timer RC Control Register 1 (TRCCR1) ......................................................... 442 15.2.3 Timer RC Control Register 2 (TRCCR2) ......................................................... 444 15.2.4 Timer RC Interrupt Enable Register (TRCIER) ............................................... 445 15.2.5 Timer RC Status Register (TRCSR) ................................................................. 446 Rev. 1.00 Oct. 03, 2008 Page xvii of xxvi 15.3 15.4 15.5 15.2.6 Timer RC I/O Control Register 0 (TRCIOR0) ................................................. 449 15.2.7 Timer RC I/O Control Register 1 (TRCIOR1) ................................................. 451 15.2.8 Timer RC Output Enable Register (TRCOER)................................................. 453 15.2.9 Timer RC Digital Filtering Function Select Register (TRCDF) ....................... 454 15.2.10 Timer RC A/D Conversion Start Trigger Control Register (TRCADCR) ........ 455 15.2.11 Timer RC Counter (TRCCNT) ......................................................................... 456 15.2.12 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD).................... 457 Operation .......................................................................................................................... 459 15.3.1 Timer Mode Operation ..................................................................................... 461 15.3.2 PWM Mode Operation...................................................................................... 466 15.3.3 PWM2 Mode Operation.................................................................................... 471 15.3.4 Digital Filtering Function for Input Capture Inputs.......................................... 477 15.3.5 A/D Conversion Start Trigger Setting Function ............................................... 478 15.3.6 Function of Changing Output Pins for GR ....................................................... 480 15.3.7 Operation through an Event Link ..................................................................... 482 Operation Timing.............................................................................................................. 483 15.4.1 TRCCNT Counting Timing .............................................................................. 483 15.4.2 Output Compare Output Timing....................................................................... 484 15.4.3 Input Capture Timing........................................................................................ 485 15.4.4 Timing of Counter Clearing by Compare Match .............................................. 485 15.4.5 Buffer Operation Timing .................................................................................. 486 15.4.6 Timing of IMFA to IMFD Flag Setting at Compare Match ............................. 487 15.4.7 Timing of IMFA to IMFD Setting at Input Capture ......................................... 488 15.4.8 Timing of Status Flag Clearing......................................................................... 489 15.4.9 Timing of A/D Conversion Start Trigger Generation on Compare Match ....... 490 Usage Notes ...................................................................................................................... 491 Section 16 Timer RD......................................................................................... 495 16.1 16.2 Features............................................................................................................................. 495 Register Descriptions........................................................................................................ 503 16.2.1 Timer RD Start Register (TRDSTR) ................................................................ 505 16.2.2 Timer RD Mode Register (TRDMDR)............................................................. 507 16.2.3 Timer RD PWM Mode Register (TRDPMR) ................................................... 508 16.2.4 Timer RD Function Control Register (TRDFCR) ............................................ 509 16.2.5 Timer RD Output Master Enable Register 1 (TRDOER1) ............................... 511 16.2.6 Timer RD Output Master Enable Register 2 (TRDOER2) ............................... 513 16.2.7 Timer RD Output Control Register (TRDOCR)............................................... 513 16.2.8 Timer RD A/D Conversion Start Trigger Control Register (TRDADCR)........ 515 16.2.9 Timer RD Counter (TRDCNT)......................................................................... 516 16.2.10 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD).................... 517 Rev. 1.00 Oct. 03, 2008 Page xviii of xxvi 16.3 16.4 16.5 16.2.11 Timer RD Control Register (TRDCR).............................................................. 519 16.2.12 Timer RD I/O Control Registers (TRDIORA and TRDIORC) ........................ 521 16.2.13 Timer RD Status Register (TRDSR)................................................................. 525 16.2.14 Timer RD Interrupt Enable Register (TRDIER) ............................................... 528 16.2.15 PWM Mode Output Level Control Register (POCR) ....................................... 529 16.2.16 Timer RD Digital Filtering Function Select Register (TRDDF)....................... 530 16.2.17 Interface with CPU ........................................................................................... 531 Operation .......................................................................................................................... 532 16.3.1 Counter Operation............................................................................................. 541 16.3.2 Waveform Output by Compare Match.............................................................. 544 16.3.3 Input Capture Function ..................................................................................... 547 16.3.4 Synchronous Operation..................................................................................... 550 16.3.5 PWM Mode ...................................................................................................... 551 16.3.6 Reset Synchronous PWM Mode ....................................................................... 557 16.3.7 Complementary PWM Mode............................................................................ 561 16.3.8 PWM3 Mode Operation.................................................................................... 567 16.3.9 Buffer Operation ............................................................................................... 573 16.3.10 Timer RD Output Timing ................................................................................. 581 16.3.11 Digital Filtering Function for Input Capture Inputs .......................................... 584 16.3.12 Function of Changing Output Pins for GR ....................................................... 585 16.3.13 A/D Conversion Start Trigger Setting Function ............................................... 587 16.3.14 Operation by Event Clear.................................................................................. 589 Interrupt Sources............................................................................................................... 590 16.4.1 Status Flag Set Timing...................................................................................... 590 16.4.2 Status Flag Clearing Timing ............................................................................. 592 Usage Notes ...................................................................................................................... 592 Section 17 Timer RE..........................................................................................603 17.1 17.2 Features............................................................................................................................. 603 Register Descriptions........................................................................................................ 605 17.2.1 Timer RE Second Data Register/Counter Data Register (TRESEC) ................ 606 17.2.2 Timer RE Minute Data Register/Compare Data Register (TREMIN) .............. 607 17.2.3 Timer RE Hour Data Register (TREHR) .......................................................... 608 17.2.4 Timer RE Day-of-Week Data Register (TREWK) ........................................... 609 17.2.5 Timer RE Control Register 1 (TRECR1).......................................................... 610 17.2.6 Timer RE Control Register 2 (TRECR2).......................................................... 613 17.2.7 Timer RE Interrupt Flag Register (TREIFR) .................................................... 614 17.2.8 Timer RE Clock Source Select Register (TRECSR) ........................................ 616 Operation of Realtime Clock Mode .................................................................................. 618 17.3.1 Initial Settings of Registers after Power-On ..................................................... 618 Rev. 1.00 Oct. 03, 2008 Page xix of xxvi 17.3 17.4 17.5 17.6 17.3.2 Initial Setting Procedure ................................................................................... 618 17.3.3 Data Reading Procedure in Realtime Clock Mode ........................................... 620 17.3.4 Operation in Realtime Clock Mode .................................................................. 621 Operation of Output Compare Mode ................................................................................ 622 Interrupt Sources............................................................................................................... 625 Usage Notes ...................................................................................................................... 626 Section 18 Timer RG......................................................................................... 627 18.1 18.2 Features............................................................................................................................. 627 Register Descriptions........................................................................................................ 630 18.2.1 Timer RG Mode Register (TRGMDR)............................................................. 631 18.2.2 Timer RG Counter Control Register (TRGCNTCR) ........................................ 632 18.2.3 Timer RG Control Register (TRGCR).............................................................. 633 18.2.4 Timer RG I/O Control Register (TRGIOR)...................................................... 634 18.2.5 Timer RG Status Register (TRGSR)................................................................. 636 18.2.6 Timer RG Interrupt Enable Register (TRGIER)............................................... 637 18.2.7 Timer RG Counter (TRGCNT)......................................................................... 638 18.2.8 General Registers A and B (GRA, GRB), GRA and GRB Buffer Registers (BRA, BRB) ..................................................................................................... 639 Operation .......................................................................................................................... 641 18.3.1 Timer Mode ...................................................................................................... 642 18.3.2 PWM Mode ...................................................................................................... 648 18.3.3 Phase Counting Mode....................................................................................... 653 18.3.4 Buffer Operation............................................................................................... 658 18.3.5 Operation through an Event Link ..................................................................... 661 18.3.6 Digital Filtering Function for Input Capture Inputs.......................................... 662 Usage Note ....................................................................................................................... 663 18.4.1 Restrictions on Access to Registers when Internal 40 Clock is Selected as Counter Clock................................................................................................... 663 18.3 18.4 Section 19 Watchdog Timer (WDT) ................................................................. 665 19.1 19.2 Features............................................................................................................................. 666 Register Descriptions........................................................................................................ 667 19.2.1 Timer Control/Status Register WD (TCSRWD) .............................................. 667 19.2.2 Timer Counter WD (TCWD)............................................................................ 668 19.2.3 Timer Mode Register WD (TMWD) ................................................................ 669 19.2.4 Timer Interrupt Control Register WD (TICRWD) ........................................... 670 19.2.5 Timer Interrupt Flag Register WD (TIFRWD)................................................. 671 Operation .......................................................................................................................... 672 19.3.1 Watchdog Timer Overflow Reset ..................................................................... 672 19.3 Rev. 1.00 Oct. 03, 2008 Page xx of xxvi 19.4 19.3.2 Watchdog Timer Setting Flow.......................................................................... 673 19.3.3 Watchdog Timer Periodic Interrupt .................................................................. 674 Usage Notes ...................................................................................................................... 675 19.4.1 Notes on System Design ................................................................................... 675 19.4.2 Notes on Stopping the Watchdog Timer or Switching the Count Clock .......... 675 Section 20 Serial Communication Interface 3 (SCI3, IrDA).............................677 20.1 20.2 Features............................................................................................................................. 677 Register Descriptions........................................................................................................ 682 20.2.1 Receive Shift Register (RSR) ........................................................................... 683 20.2.2 Receive Data Register (RDR) ........................................................................... 683 20.2.3 Transmit Shift Register (TSR) .......................................................................... 683 20.2.4 Transmit Data Register (TDR).......................................................................... 684 20.2.5 Serial Mode Register (SMR) ............................................................................ 684 20.2.6 Serial Control Register 3 (SCR3)...................................................................... 686 20.2.7 Serial Status Register (SSR) ............................................................................. 688 20.2.8 Bit Rate Register (BRR) ................................................................................... 690 20.2.9 Sampling Mode Register (SPMR) .................................................................... 695 20.2.10 IrDA Control Register (IrCR) ........................................................................... 695 Operation in Asynchronous Mode .................................................................................... 697 20.3.1 Clock................................................................................................................. 697 20.3.2 SCI3 Initialization............................................................................................. 698 20.3.3 Data Transmission ............................................................................................ 700 20.3.4 Data Reception.................................................................................................. 702 Operation in Clocked Synchronous Mode ........................................................................ 706 20.4.1 Clock................................................................................................................. 706 20.4.2 SCI3 Initialization............................................................................................. 706 20.4.3 Data Transmission ............................................................................................ 707 20.4.4 Data Reception (Clocked Synchronous Mode)................................................. 709 20.4.5 Simultaneous Data Transmission and Reception .............................................. 711 Multiprocessor Communication Function......................................................................... 713 20.5.1 Multiprocessor Data Transmission ................................................................... 714 20.5.2 Multiprocessor Data Reception......................................................................... 716 IrDA Operation ................................................................................................................. 720 20.6.1 Transmission..................................................................................................... 721 20.6.2 Reception .......................................................................................................... 721 20.6.3 High-Level Pulse Width Selection.................................................................... 722 Noise Canceler.................................................................................................................. 723 Interrupt Requests ............................................................................................................. 724 Usage Notes ...................................................................................................................... 725 Rev. 1.00 Oct. 03, 2008 Page xxi of xxvi 20.3 20.4 20.5 20.6 20.7 20.8 20.9 20.9.1 20.9.2 20.9.3 20.9.4 20.9.5 20.9.6 Break Detection and Processing ....................................................................... 725 Mark State and Break Sending ......................................................................... 725 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ................................................................. 725 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ......................................................................................... 726 Relation between Writes to TDR and TDRE Flag............................................ 727 Restrictions on Using DTC............................................................................... 727 Section 21 I2C Bus Interface 2 (IIC2)................................................................ 729 21.1 21.2 Features............................................................................................................................. 729 Register Descriptions........................................................................................................ 732 21.2.1 IIC2/SSU Select Register (ICSUSR) ................................................................ 733 21.2.2 I2C Bus Control Register 1 (ICCR1)................................................................. 733 21.2.3 I2C Bus Control Register 2 (ICCR2)................................................................. 736 21.2.4 I2C Bus Mode Register (ICMR)........................................................................ 738 21.2.5 I2C Bus Interrupt Enable Register (ICIER)....................................................... 739 21.2.6 I2C Bus Status Register (ICSR)......................................................................... 741 21.2.7 Slave Address Register (SAR).......................................................................... 745 21.2.8 I2C Bus Transmit Data Register (ICDRT) ........................................................ 745 21.2.9 I2C Bus Receive Data Register (ICDRR).......................................................... 746 21.2.10 I2C Bus Shift Register (ICDRS)........................................................................ 746 Operation .......................................................................................................................... 747 21.3.1 I2C Bus Format.................................................................................................. 747 21.3.2 Master Transmit Operation............................................................................... 748 21.3.3 Master Receive Operation ................................................................................ 750 21.3.4 Slave Transmit Operation ................................................................................. 752 21.3.5 Slave Receive Operation................................................................................... 755 21.3.6 Clock Synchronous Serial Format .................................................................... 756 21.3.7 Noise Filter Circuit ........................................................................................... 759 21.3.8 Example of Use................................................................................................. 760 Interrupt Request .............................................................................................................. 764 Bit Synchronous Circuit.................................................................................................... 765 Usage Notes ...................................................................................................................... 766 21.6.1 SCL and SDA pins selected by PMC ............................................................... 766 21.6.2 Restriction on Use of Bit Manipulation Instructions to Set MST and TRS in Multi-Master Usage.............................................................................. 766 21.3 21.4 21.5 21.6 Section 22 Synchronous Serial Communication Unit (SSU) ............................ 767 22.1 Features............................................................................................................................. 767 Rev. 1.00 Oct. 03, 2008 Page xxii of xxvi 22.2 22.3 22.4 22.5 Register Descriptions........................................................................................................ 769 22.2.1 IIC2/SSU Select Register (ICSUSR) ................................................................ 769 22.2.2 SS Control Register H (SSCRH) ...................................................................... 770 22.2.3 SS Control Register L (SSCRL) ....................................................................... 771 22.2.4 SS Mode Register (SSMR) ............................................................................... 773 22.2.5 SS Mode Register 2 (SSMR2) .......................................................................... 774 22.2.6 SS Enable Register (SSER) .............................................................................. 776 22.2.7 SS Status Register (SSSR) ................................................................................ 777 22.2.8 SS Receive Data Register (SSRDR) ................................................................. 779 22.2.9 SS Transmit Data Register (SSTDR)................................................................ 779 22.2.10 SS Shift Register (SSTRSR)............................................................................. 780 Operation .......................................................................................................................... 780 22.3.1 Transfer Clock .................................................................................................. 780 22.3.2 Relationship between Clock Polarity and Phase, and Data............................... 780 22.3.3 Relationship between Data Input/Output Pin and Shift Register ...................... 782 22.3.4 Communication Modes and Pin Functions ....................................................... 783 22.3.5 Operation in Clocked Synchronous Communication Mode.............................. 784 22.3.6 Operation in Four-Line Bus Communication Mode ......................................... 791 22.3.7 SCS Pin Control and Arbitration ...................................................................... 797 Interrupt Requests ............................................................................................................. 798 Usage Notes ...................................................................................................................... 799 Section 23 Hardware LIN ..................................................................................801 23.1 23.2 Overview........................................................................................................................... 801 Register Configuration...................................................................................................... 802 23.2.1 LIN Control Register (LINCR)......................................................................... 802 23.2.2 LIN Status Register (LINST)............................................................................ 804 Operation .......................................................................................................................... 805 23.3.1 Master Mode ..................................................................................................... 805 23.3.2 Slave Mode ....................................................................................................... 808 23.3.3 Bus Conflict Detection Function....................................................................... 813 23.3.4 Terminating Hardware LIN .............................................................................. 814 Interrupt Requests ............................................................................................................. 815 Usage Note........................................................................................................................ 815 23.3 23.4 23.5 Section 24 A/D Converter..................................................................................817 24.1 24.2 Features............................................................................................................................. 817 Register Description ......................................................................................................... 821 24.2.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7) .............................................. 822 24.2.2 A/D Control/Status Register (ADCSR) ............................................................ 823 Rev. 1.00 Oct. 03, 2008 Page xxiii of xxvi 24.3 24.4 24.5 24.6 24.7 24.8 24.2.3 A/D Control Register (ADCR) ......................................................................... 825 24.2.4 A/D Mode Register (ADMR) ........................................................................... 827 24.2.5 Compare Data Register (CMPR) ...................................................................... 828 24.2.6 Compare Control Status Register (CMPCSR) .................................................. 830 24.2.7 Compare Analog Level Registers H and L (CMPVALH and CMPVALL) ..... 832 Operation .......................................................................................................................... 834 A/D Conversion Mode Operation..................................................................................... 835 24.4.1 Single Mode in A/D Conversion Mode ............................................................ 835 24.4.2 Scan Mode in A/D Conversion Mode............................................................... 837 Compare Mode Operation ................................................................................................ 839 24.5.1 Single Mode in Compare Mode........................................................................ 839 24.5.2 Scan Mode in Comparison Mode ..................................................................... 840 24.5.3 Input Sampling and A/D Conversion Time ...................................................... 841 24.5.4 External Trigger Input Timing.......................................................................... 843 Interrupt Source ................................................................................................................ 844 A/D Conversion Accuracy Definitions ............................................................................. 845 Usage Notes ...................................................................................................................... 847 24.8.1 Module Standby Mode Setting ......................................................................... 847 24.8.2 Permissible Signal Source Impedance .............................................................. 847 24.8.3 Influences on Absolute Precision...................................................................... 848 24.8.4 Setting Range of Analog Power Supply and Other Pins................................... 848 24.8.5 Notes on Board Design ..................................................................................... 848 24.8.6 Notes on Noise Countermeasures ..................................................................... 849 24.8.7 Notes on Analog Input Pins .............................................................................. 850 Section 25 D/A Converter ................................................................................. 851 25.1 25.2 Features............................................................................................................................. 851 Register Descriptions........................................................................................................ 852 25.2.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)......................................... 852 25.2.2 D/A Control Register (DACR) ......................................................................... 853 Operation .......................................................................................................................... 854 Usage Notes ...................................................................................................................... 856 25.4.1 Setting for Module Stop Mode ......................................................................... 856 25.4.2 Operation in Standby Mode .............................................................................. 856 25.3 25.4 Section 26 Low-Voltage Detection Circuits...................................................... 857 26.1 26.2 Features............................................................................................................................. 858 Register Descriptions........................................................................................................ 860 26.2.1 Low-Voltage Detection Circuit Control Protect Register (VDCPR) ................ 861 26.2.2 Low-Voltage Detection Circuit 2 Control Register H (LD2CRH) ................... 862 Rev. 1.00 Oct. 03, 2008 Page xxiv of xxvi 26.3 26.2.3 Low-Voltage Detection Circuit 2 Control Register L (LD2CRL) .................... 864 26.2.4 Low-Voltage Detection Circuit 1 Control Register H (LD1CRH) ................... 865 26.2.5 Low-Voltage Detection Circuit 1 Control Register L (LD1CRL) .................... 867 26.2.6 Low-Voltage Detection Circuit 0 Control Register H (LD0CRH) ................... 868 26.2.7 Low-Voltage Detection Circuit 0 Control Register L (LD0CRL) .................... 869 Operation .......................................................................................................................... 870 26.3.1 Power-On Reset Function ................................................................................. 870 26.3.2 Low-Voltage Detection Circuit......................................................................... 871 Section 27 List of Registers ...............................................................................883 27.1 27.2 Register Addresses (Address Order)................................................................................. 884 Register Bits...................................................................................................................... 900 Section 28 Electrical Characteristics .................................................................915 28.1 28.2 Absolute Maximum Ratings ............................................................................................. 915 Electrical Characteristics .................................................................................................. 916 28.2.1 Power Supply Voltage and Operating Ranges .................................................. 916 28.3 DC Characteristics ............................................................................................................ 918 28.4 AC Characteristics ............................................................................................................ 928 28.5 A/D Converter Characteristics .......................................................................................... 934 28.6 D/A Converter Characteristics .......................................................................................... 936 28.7 Flash Memory Characteristics .......................................................................................... 937 28.8 Electrical Characteristics for Low-Voltage Detection Circuits......................................... 939 28.9 Electrical Characteristics for Power-On Reset Function................................................... 942 28.10 Timing Charts ................................................................................................................... 943 28.11 Output Load Circuit .......................................................................................................... 951 Appendix..............................................................................................................953 A. B. Package Dimensions ......................................................................................................... 953 Handling of Unused Pins .................................................................................................. 957 Index ....................................................................................................................959 Rev. 1.00 Oct. 03, 2008 Page xxv of xxvi Rev. 1.00 Oct. 03, 2008 Page xxvi of xxvi Section 1 Overview Section 1 Overview 1.1 Features The H8S/Tiny series is a 16-bit CISC (complex instruction set computer) microcontroller, each member of the H8S/Tiny series has the powerful H8S/2000 CPU with an internal 32-bit architecture as its core. The H8S/2000 CPU provides upwards-compatibility with the other members of the Renesas Technology H8 Family: H8/300, H8/300H Tiny and H8/300H. The on-chip peripheral function modules include a data transfer controller, event link controller, serial communication interface, I2C bus interface 2, synchronous serial communication unit, hardware LIN communication interface, A/D and D/A converters, low-voltage detection circuit, and versatile timers. These modules realize low-cost systems. The power consumption of these modules can be controlled dynamically using power-down modes. 1.1.1 Applications Examples of the applications include home appliances, office automation equipment, consumer equipment, and industrial equipment. 1.1.2 Overview of Functions Table 1.1 lists the specifications of the products of this series. Table 1.1 Overview of Functions Module/ Function ROM Description * Flash memory version Program memory: 128 kbytes or 96 kbytes Number of program/erase times: 1000 times Data flash: 4 kbytes x two blocks Number of program/erase times: 10000 times RAM * Capacity: 8 kbytes Classification Memory Rev. 1.00 Oct. 03, 2008 Page 1 of 962 REJ09B0465-0100 Section 1 Overview Classification CPU Module/ Function CPU Description * 16-bit high-speed H8S/2000 CPU (CISC type) Upwardly compatible with H8/300 and H8/300H CPUs at object level * * * General-register architecture (sixteen 16-bit general registers) Eight addressing modes 16-Mbyte address space Program: 16 Mbytes available Data: 16 Mbytes available * 65 basic instructions including bit operation instructions, multiply and divide instructions, bit manipulation instructions, and others Minimum instruction execution time: 50 ns (for an ADD instruction) while system clock = 20 MHz and VCC = 2.7 to 5.5 V * Operating mode Interrupt (source) Interrupt controller (INTC) Advanced single-chip mode * * Nine external interrupt pins (NMI, and IRQ7 to IRQ0) Internal interrupt sources 55 (H8S/20103 group) 61 (H8S/20203 group) 63 (H8S/20223 group) * * * Two interrupt control modes (specified by the interrupt control register) Four interrupt priority orders specifiable (by setting the interrupt priority register) Independent vector addresses Two clock generation circuits: main and sub-clock oscillators Two on-chip oscillators High speed: 40 MHz Low speed: 125 kHz * Three power-down modes: sleep mode, software standby mode, and module standby mode Clock Clock pulse generator (CPG) * * Rev. 1.00 Oct. 03, 2008 Page 2 of 962 REJ09B0465-0100 Section 1 Overview Classification Voltage detection DMA Module/ Function Description Voltage Voltage drop detected detection circuit (LVD) Data transfer * controller * (DTC) A/D converter (ADC) * * * * * Transfer via any number of channels possible Three transfer modes 10-bit resolution x eight to sixteen input channels Sample and hold function included Conversion time: 2 s per channel Two operating modes: single mode and scan mode Three ways to start A/D conversion: software, timer trigger, and external pin trigger. 8-bit resolution x two input channels A/D converter D/A converter D/A converter (DAC) Timer RA Timer RB Timer RC Timer RD Timer RE Timer RG * Timers 8 bits x one channel (with 8-bit prescaler) 8 bits x one channel (with 8-bit prescaler) 16 bits x one channel (only available with H8S/20103 group) 16 bits x two channels (x two units in H8S/20203 and H8S/20223 groups) 8 bits x one channel with real-time clock function 16 bits x one channel with phase-counting mode Watchdog 8 bit x one channel timer (WDT) Serial interfaces Serial communication interface (SCI3) Synchronous serial communication unit (SSU) * Three channels (either for asynchronous or clock-synchronous communication) * Full-duplex communication capability * Any desired bit rate selectable IrDA (only available with channel 2) * * One channel (IIC2 and selection format) Clock-synchronous communication with chip-select function Rev. 1.00 Oct. 03, 2008 Page 3 of 962 REJ09B0465-0100 Section 1 Overview Classification Module/ Function 2 Description * * * One channel (SSU and selection format) Continuous transmission and reception possible Two transmission/reception formats I C bus format: generates start and stop conditions in master mode automatically, acknowledge bit, master or slave operation 2 Serial interfaces I C bus interface 2 (IIC2) Clock-synchronous serial format: no acknowledge bit, master operation only Hardware One channel (timer RA and SCI3 used) LIN interface Event link controller (ELC) Events (interrupts) generated by peripheral modules can be interconnected between modules, enabling cooperation between the modules without CPU intervention. * I/O pins 55 (H8S/20103 group) 69 (H8S/20203 and H8S/20223 groups) * * Pull-up resistors settable for all ports LED driving capability I/O ports Rev. 1.00 Oct. 03, 2008 Page 4 of 962 REJ09B0465-0100 Section 1 Overview Classification Packages Module/ Function Description * 64-pin QFP package (PLQP0064KB-A) Former code: 64P6Q-A Body size: 10 x 10 mm Pin pitch: 0.50 mm * 64-pin QFP package (PLQP0064GA-A) Former code: 64P6U-A Body size: 14 x 14 mm Pin pitch: 0.80 mm * 80-pin QFP package (PLQP0080JA-A) Former code: FP-80W Body size: 14 x 14 mm Pin pitch: 0.65 mm * 80-pin QFP package (PLQP0080KB-A) Former code: 80P6Q-A Body size: 12 x 12 mm Pin pitch: 0.50 mm Operating frequency/ Power supply voltage Operating ambient temperature (C) * * * * Operating frequency: 4 to 20 MHz Power supply voltage: Vcc = 2.7 to 5.5 V, Avcc = 2.7 to 5.5 V -20 to +85C (version N) -40 to +85C (version D) Rev. 1.00 Oct. 03, 2008 Page 5 of 962 REJ09B0465-0100 Section 1 Overview 1.2 List of Products Table 1.2 lists products of this series, and figure 1.1 shows how to read the part number. Table 1.2 Group H8S/20103 List of Products Part No. ROM Capacity RAM Capacity Package 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes PLQP0064KB-A (LQFP1010-64) PLQP0064GA-A (LQFP1414-64) PLQP0064KB-A (LQFP1010-64) PLQP0064GA-A (LQFP1414-64) PLQP0080KB-A (LQFP1212-80) PLQP0080JA-A (LQFP1414-80) PLQP0080KB-A (LQFP1212-80) PLQP0080JA-A (LQFP1414-80) PLQP0080KB-A (LQFP1212-80) PLQP0080JA-A (LQFP1414-80) PLQP0080KB-A (LQFP1212-80) PLQP0080JA-A (LQFP1414-80) Version D Version N Version D Version N Version D Remarks Version N R4F20103NFA 128 kbytes R4F20102NFA 96 kbytes R4F20103NFB 128 kbytes R4F20102NFB 96 kbytes R4F20103DFA 128 kbytes R4F20102DFA 96 kbytes R4F20103DFB 128 kbytes R4F20102DFB 96 kbytes H8S/20203 R4F20203NFC 128 kbytes R4F20202NFC 96 kbytes R4F20203NFD 128 kbytes R4F20202NFD 96 kbytes R4F20203DFC 128 kbytes R4F20202DFC 96 kbytes R4F20203DFD 128 kbytes R4F20202DFD 96 kbytes H8S/20223 R4F20223NFC 128 kbytes R4F20222NFC 96 kbytes R4F20223NFD 128 kbytes R4F20222NFD 96 kbytes R4F20223DFC 128 kbytes R4F20222DFC 96 kbytes R4F20223DFD 128 kbytes R4F20222DFD 96 kbytes Rev. 1.00 Oct. 03, 2008 Page 6 of 962 REJ09B0465-0100 Section 1 Overview Part number R 4 F 20103 N FA Package type FA: PLQP0064KB-A (64-pin version) or FC: PLQP0080KB-A (80-pin version) FB: PLQP0064GA-A (64-pin version) or FD: PLQP0080JA-A (80-pin version) Operating temperature N: -20C to +85C D: -40C to +85C Product-specific code H8S/20103 Memory type F: On-chip flash memory Product classification 4: Microcomputer Indicates Renesas semiconductor product Figure 1.1 How to Read the Part Number Rev. 1.00 Oct. 03, 2008 Page 7 of 962 REJ09B0465-0100 Section 1 Overview 1.3 VCC VSS Block Diagram Peripheral address bus Peripheral data bus Port 1 RES TEST P11/IRQ1 P12/IRQ2 P13/IRQ3 P15/IRQ5 P16/IRQ6 P17/IRQ7 Internal data bus Bus controller ROM H8S/2000 CPU Internal address bus RAM DTC P20/SCK3 P21/RXD P22/TXD P23/TRCOI P24/TRDOI_0 P25/SCK3_2 P26/RXD_2 P27/TXD_2 P30/FTIOA P31/FTIOB P32/FTIOC P33/FTIOD P34/FTCI P35/SCK3_3 P36/RXD_3 P37/TXD_3 PJ0/OSC1 PJ1/OSC2 X1 X2 Main clock oscillator Sub-clock oscillator Low-voltage detection circuit Port 3 ELC High-speed OCO Low-speed OCO PMC Interrupt controller NMI SCI3 x 3 channels LIN x 1 channel P50/TCLKA P51/TCLKB P52/TGIOA P53/TGIOB P54/SSO P55/SSCK P56/SDA/SCS P57/SCL/SSI IIC2 SSU 8-bit timer x 4 channels * Timer RA * Timer RB * Timer RE * WDT Port 5 10-bit A/D PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6/DA0 PB7/AN7/DA1 Port 2 16-bit timer x 4 channels * Timer RC * Timer RD * Timer RG 8-bit D/A Port A P60/FTIOA0 P61/FTIOB0 P62/FTIOC0 P63/FTIOD0 P64/FTIOA1 P65/FTIOB1 P66/FTIOC1 P67/FTIOD1 Port B PA4 PA5 PA6 PA7 AVCC AVss Port 8 Figure 1.2 Block Diagram of H8S/20103 Group Rev. 1.00 Oct. 03, 2008 Page 8 of 962 REJ09B0465-0100 Port 6 P85/TRAIO P86/TRBO P87/TREO Section 1 Overview VCC VSS RES TEST ROM Internal data bus Port 1 VSS Internal address bus Peripheral data bus H8S/2000 CPU Peripheral address bus Bus controller P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/IRQ5 P16/IRQ6 P17/IRQ7 RAM DTC P20/SCK3 P21/RXD P22/TXD P23 P24/TRDOI_0 P25/SCK3_2 P26/RXD_2 P27/TXD_2 P30 P31 P32 P33 P34 P35/SCK3_3 P36/RXD_3 P37/TXD_3 PJ0/OSC1 PJ1/OSC2 X1 X2 Main clock oscillator Sub-clock oscillator Low-voltage detection circuit Port 3 ELC High-speed OCO Low-speed OCO PMC Interrupt controller NMI SCI3 x 3 channels LIN x 1 channel P50/TCLKA P51/TCLKB P52/TGIOA P53/TGIOB P54/SSO P55/SSCK P56/SDA/SCS P57/SCL/SSI IIC2 SSU 8-bit timer x 4 channels * Timer RA * Timer RB * Timer RE * WDT Port 5 10-bit A/D PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6/DA0 PB7/AN7/DA1 PA0/AN8 PA1/AN9 PA2/AN10 PA3/AN11 PA4 PA5 PA6 PA7 AVCC AVSS Port 2 16-bit timer x 5 channels * Timer RD_0 * Timer RD_1 * Timer RG 8-bit D/A Port A P60/FTIOA0 P61/FTIOB0 P62/FTIOC0 P63/FTIOD0 P64/FTIOA1 P65/FTIOB1 P66/FTIOC1 P67/FTIOD1 Port B Port 9 Port 8 Figure 1.3 Block Diagram of H8S/20203 Group Rev. 1.00 Oct. 03, 2008 Page 9 of 962 REJ09B0465-0100 Port 6 P90/FTIOA2 P91/FTIOB2 P92/FTIOC2 P93/FTIOD2 P94/FTIOA3 P95/FTIOB3 P96/FTIOC3 P97/FTIOD3 P85/TRAIO P86/TRBO P87/TREO Section 1 Overview VCC VSS VSS RES TEST Peripheral data bus Port 1 Internal data bus Bus controller Peripheral address bus ROM H8S/2000 CPU Internal address bus P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/IRQ5 P16/IRQ6 P17/IRQ7 RAM DTC P20/SCK3 P21/RXD P22/TXD P23 P24/TRDOI_0 P25/SCK3_2 P26/RXD_2 P27/TXD_2 P30 P31 P32 P33 P34 P35/SCK3_3 P36/RXD_3 P37/TXD_3 PJ0/OSC1 PJ1/OSC2 X1 X2 Main clock oscillator Sub-clock oscillator Low-voltage detection circuit Port 3 ELC High-speed OCO Low-speed OCO PMC Interrupt controller NMI SCI3 x 3 channels LIN x 1 channel P50/TCLKA P51/TCLKB P52/TGIOA P53/TGIOB P54/SSO P55/SSCK P56/SDA/SCS P57/SCL/SSI IIC2 SSU 8-bit timer x 4 channels * Timer RA * Timer RB * Timer RE * WDT Port 5 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6/DA0 PB7/AN7/DA1 PA0/AN8 PA1/AN9 PA2/AN10 PA3/AN11 PA4/AN0_2 PA5/AN1_2 PA6/AN2_2 PA7/AN3_2 AVCC AVSS 10-bit A/D (unit 1) Port 2 16-bit timer x 5 channels * Timer RD_0 * Timer RD_1 * Timer RG 8-bit D/A Port A Port 9 Port 8 Figure 1.4 Block Diagram of H8S/20223 Group Rev. 1.00 Oct. 03, 2008 Page 10 of 962 REJ09B0465-0100 Port 6 10-bit A/D (unit 2) P60/FTIOA0 P61/FTIOB0 P62/FTIOC0 P63/FTIOD0 P64/FTIOA1 P65/FTIOB1 P66/FTIOC1 P67/FTIOD1 Port B P90/FTIOA2 P91/FTIOB2 P92/FTIOC2 P93/FTIOD2 P94/FTIOA3 P95/FTIOB3 P96/FTIOC3 P97/FTIOD3 P85/TRAIO P86/TRBO P87/TREO Section 1 Overview 1.4 Pin Assignments P25/SCK3_2 P23/TRCOI P22/TXD P21/RXD P20/SCK3 P87/TREO P86/TRBO P85/TRAIO P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P60/FTIOA0 NMI P61/FTIOB0 P62/FTIOC0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 P26/RXD_2 P27/TXD_2 P24/TRDOI_0 P11/IRQ1 P12/IRQ2 P13/IRQ3 PA4 PA5 PA6 PA7 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 PB4/AN4 PB5/AN5 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 33 32 31 30 29 28 H8S/20103 Group PLQP0064KB-A 64P6Q-A/FP-64K PLQP0064GA-A 64P6U-A (top view) 27 26 25 24 23 22 21 20 19 18 17 P63/FTIOD0 P50/TCLKA P51/TCLKB P52/TGIOA P53/TGIOB P57/SCL/SSI P56/SDA/SCS P55/SSCK P54/SSO P17/IRQ7 P16/IRQ6 P15/IRQ5 P30/FTIOA P31/FTIOB P32/FTIOC P33/FTIOD 9 10 11 12 13 14 15 PB6/AN6/DA0 PB7/AN7/DA1 AVCC X2 X1 AVSS RES TEST Vss PJ1/OSC2 PJ0/OSC1 VCC P37/TXD_3 P36/RXD_3 P35/SCK3_3 P34/FTCI Figure 1.5 Pin Assignment of H8S/20103 Group Rev. 1.00 Oct. 03, 2008 Page 11 of 962 REJ09B0465-0100 16 1 2 3 4 5 6 7 8 Section 1 Overview 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 9 10 11 12 13 14 15 16 17 18 Note: Do not connect any pin to NC. Rev. 1.00 Oct. 03, 2008 Page 12 of 962 REJ09B0465-0100 PB6/AN6/DA0 PB7/AN7/DA1 AVCC X2 X1 NC RES TEST Vss PJ1/OSC2 PJ0/OSC1 VCC NMI P87/TREO P86/TRBO P85/TRAIO P37/TXD_3 P36/RXD_3 P35/SCK3_3 P34 Figure 1.6 Pin Assignment of H8S/20203 Group 19 1 2 3 4 5 6 7 8 20 P97/FTIOD3 P90/FTIOA2 P91/FTIOB2 P92/FTIOC2 P93/FTIOD2 PA4 PA5 PA6 PA7 PA0/AN8 PA1/AN9 PA2/AN10 PA3/AN11 AVss PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 41 P96/FTIOC3 P95/FTIOB3 P94/FTIOA3 P13/IRQ3 P12/IRQ2 P23 P22/TXD P21/RXD P20/SCK3 P24/TRDOI_0 VSS P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 P25/SCK3_2 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 H8S/20203 Group PLQP0080JA-A FP-80W PLQP0080KB-A 80P6Q-A (top view) P26/RXD_2 P27/TXD_2 P11/IRQ1 P10/IRQ0 P50/TCLKA P51/TCLKB P52/TGIOA P53/TGIOB P54/SSO P55/SSCK P56/SDA/SCS P57/SCL/SSI P17/IRQ7 P16/IRQ6 P15/IRQ5 P14/IRQ4 P30 P31 P32 P33 Section 1 Overview 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 9 10 11 12 13 14 15 16 17 18 Note: Do not connect any pin to NC. PB6/AN6/DA0 PB7/AN7/DA1 AVCC X2 X1 NC RES TEST Vss PJ1/OSC2 PJ0/OSC1 VCC NMI P87/TREO P86/TRBO P85/TRAIO P37/TXD_3 P36/RXD_3 P35/SCK3_3 P34 Figure 1.7 Pin Assignment of H8S/20223 Group Rev. 1.00 Oct. 03, 2008 Page 13 of 962 REJ09B0465-0100 19 1 2 3 4 5 6 7 8 20 P97/FTIOD3 P90/FTIOA2 P91/FTIOB2 P92/FTIOC2 P93/FTIOD2 PA4/AN0_2 PA5/AN1_2 PA6/AN2_2 PA7/AN3_2 PA0/AN8 PA1/AN9 PA2/AN10 PA3/AN11 AVss PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 41 P96/FTIOC3 P95/FTIOB3 P94/FTIOA3 P13/IRQ3 P12/IRQ2 P23 P22/TXD P21/RXD P20/SCK3 P24/TRDOI_0 VSS P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 P25/SCK3_2 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 H8S/20223 Group PLQP0080JA-A FP-80W PLQP0080KB-A 80P6Q-A (top view) P26/RXD_2 P27/TXD_2 P11/IRQ1 P10/IRQ0 P50/TCLKA P51/TCLKB P52/TGIOA P53/TGIOB P54/SSO P55/SSCK P56/SDA/SCS P57/SCL/SSI P17/IRQ7 P16/IRQ6 P15/IRQ5 P14/IRQ4 P30 P31 P32 P33 Section 1 Overview 1.4.1 Table 1.3 Pin Functions Pin Functions Pin No. H8S/20203 and H8S/20103 H8S/20223 Group Groups I/O 12 12 Input Classification Symbol Power supply VCC Description Power supply pin. Connect this pin to the system power supply. Ground pin. Connect this pin to the system power supply (0 V). Analog power supply pin for A/D and D/A converters. When A/D and D/A converters are not used, connect this pin to the system power supply. Analog ground pin for A/D and D/A converters. Connect this pin to the system power supply (0 V). VSS 9 9, 50 Input AVCC 3 3 Input AVSS 6 74 Input Clock OSC1 11 11 10 Input OSC2/CLKOUT 10 Pins to be connected to a crystal or ceramic Output resonator for the system clock. An external clock can also be input to OSC1. When the on-chip oscillator is not used, the system clock signal can be output from OSC2. For connection examples, see section 5, Clock Pulse Generator. Rev. 1.00 Oct. 03, 2008 Page 14 of 962 REJ09B0465-0100 Section 1 Overview Pin No. H8S/20203 and H8S/20103 H8S/20223 Group Groups I/O 5 4 5 4 Input Classification Clock Symbol X1 X2 Description Pins to be connected to a Output crystal resonator for the 32.768-kHz sub-clock. For connection examples, see section 5, Clock Pulse Generator. Input Reset pin. Applying a low level signal to this pin resets this LSI. Test pin. Connect this pin to VSS. Non-maskable interrupt request input pin. Be sure to pull up this pin with a resistor. External interrupt request input pins. Either rising, falling, or rising/falling edge of these pins can be detected. Pin for pulse output, count source input, and input of pulses to be measured. System control RES 7 7 TEST External interrupt NMI 8 35 8 13 Input Input IRQ0 to IRQ7 52 to 54*1 21 to 23 37, 38 56, 57 25 to 28 Input Timer RA TRAIO 41 16 I/O TRAO Timer RB TRGB TRBO Timer RC*3 FTCI FTIOA to FTIOD *2 *2 42 16 20 to 17 *2 *2 15 Output Pin for inverted pulse output. Input Pin for trigger input. Output Pin for pulse output and PWM output. Input I/O Pin for external event input. Pins for output-compare output, input-capture input, and PWM output. Rev. 1.00 Oct. 03, 2008 Page 15 of 962 REJ09B0465-0100 Section 1 Overview Pin No. H8S/20203 and H8S/20103 H8S/20223 Group Groups I/O 20 47 Input Input Classification Symbol Timer RC* 3 Description Pin for external trigger input. Pin for inputting the timeroutput enable or disable signal. Pin for output-compare output, input-capture input, and external clock input. Pin for output-compare output, input-capture input, and PWM output. Pin for output-compare output, input-capture input, and PWM synchronous output (at reset or in complementary PWM mode). Pin for output-compare output, input-capture input, and PWM output. Pin for output-compare output, input-capture input, and PWM output (at reset or in complementary PWM mode). Pins for output-compare output, input-capture input, and PWM output. Pin for inputting the timeroutput enable or disable signal. TRGC TRCOI Timer RD_0 FTIOA0 36 42 I/O FTIOB0 34 43 I/O FTIOC0 33 44 I/O FTIOD0 32 45 I/O FTIOA1 37 46 I/O FTIOB1 to FTIOD1 TRDOI_0 38 to 40 47 to 49 I/O 51 51 Input Rev. 1.00 Oct. 03, 2008 Page 16 of 962 REJ09B0465-0100 Section 1 Overview Pin No. H8S/20203 and H8S/20103 H8S/20223 Group Groups I/O 62 I/O Classification Symbol Timer RD_1* 5 Description Pin for output-compare output, input-capture input, and external clock input. Pin for output-compare output, input-capture input, and PWM output. Pin for output-compare output, input-capture input, and PWM synchronous output (at reset or in complementary PWM mode). Pin for output-compare output, input-capture input, and PWM output. Pin for output-compare output, input-capture input, and PWM output (at reset or in complementary PWM mode). Pins for output-compare output, input-capture input, and PWM output. Pin for inputting the timeroutput enable or disable signal. FTIOA2 FTIOB2 63 I/O FTIOC2 64 I/O FTIOD2 65 I/O FTIOA3 58 I/O FTIOB3 to FTIOD3 TRDOI_1 59 to 61 I/O *4 Input Timer RE Timer RG TREO TCLKA TCLKB TGIOA TGIOB 43 31 30 29 28 14 36 35 34 33 Output Pin for clock signal output. Input I/O Pins for external clock input. Pins for output-compare output, input-capture input, and PWM output. Rev. 1.00 Oct. 03, 2008 Page 17 of 962 REJ09B0465-0100 Section 1 Overview Pin No. H8S/20203 and H8S/20103 H8S/20223 Group Groups I/O 46 50 13 45 49 14 44 48 15 26 54 39 17 53 40 18 52 41 19 30 I/O Input/output pin for I2C data. Bus can be directly driven by the NMOS open-drain output. When this pin is used, an external pull-up resistor is required. Input/output pin for I2C clock signal. Bus can be directly driven by the NMOS open-drain output. When this pin is used, an external pull-up resistor is required. Input/output pin for the chip select signal. Input/output pin for the clock signal. Input/output pin for data transmission/reception. Input/output pin for data transmission/reception. I/O Input/output pins for clock signals. Input Input pins for data reception. Classification Symbol Description Serial TXD communication TXD_2 interface 3 TXD_3 (SCI3) RXD RXD_2 RXD_3 SCK3 SCK3_2 SCK3_3 I2C bus interface 2 (IIC2) SDA Output Output pins for data transmission. SCL 27 29 I/O Synchronous SCS serial communication SSCK unit (SSU) SSI SSO 26 25 27 24 30 31 29 32 I/O I/O I/O I/O Rev. 1.00 Oct. 03, 2008 Page 18 of 962 REJ09B0465-0100 Section 1 Overview Pin No. H8S/20203 and H8S/20103 H8S/20223 Group Groups I/O 6 Classification Symbol AD converter_1 AN11 to AN0* Description Analog input pins. 2, 1, 64, 63, 59 to 62 *7 73 to 70, 2, 1 80 to 75 *7 Input ADTRG1 Input Input pin for the conversion-start trigger signal. Analog input pins. Input pin for the conversion-start trigger signal. AD 8 converter_2* AN3_2 to AN0_2 ADTRG2 69 to 66 *7 Input Input DA converter I/O ports DA1 DA0 P17 to P10* P27 to P20 P37 to P30 P57 to P50 P67 to P60 9 2 1 23 to 21, 54 to 52 2 1 Output Analog output pins. 8-bit input/output port pins. 8-bit input/output port pins. 8-bit input/output port pins. 8-bit input/output port pins. 8-bit input/output port pins. 28 to 25, 57, 56, I/O 38, 37 I/O I/O I/O I/O 50, 49, 51, 39 to 41, 51, 55 48 to 44 to 52 20 to 13 31 to 28 24 to 27 36, 34 to 32, 37 to 40 41 to 43 10 17 to 24 29 to 36 49 to 42 P87 to P85 P97 to P90* 14 to 16 61 to 58 65 to 62 69 to 66 73 to 70 I/O I/O I/O 3-bit input/output port pins. 8-bit input/output port pins. 8-bit input/output port pins. 58 to 55 PA7 to PA0*11 Rev. 1.00 Oct. 03, 2008 Page 19 of 962 REJ09B0465-0100 Section 1 Overview Pin No. H8S/20203 and H8S/20103 H8S/20223 Group Groups I/O 62 to 59, 2, 1, 80 to 75 63, 64, 1, 2 10, 11 10, 11 I/O I/O Classification Symbol I/O ports PB7 to PB0 PJ1 and PJ0 Description 8-bit input/output port pins. 2-bit input/output port pins. Notes: 1. In the H8S/20103 group, the IRQ0 and IRQ4 pins are not available with the initial setting of the PMC. 2. The TRAO and TRGB pins are not available with the initial setting of the PMC. 3. The H8S/20203 and H8S/20223 groups do not incorporate timer RC. 4. The TRDOI_1 pin is not available with the initial setting of the PMC. 5. The H8S/20103 group does not incorporate timer RD_1. 6. In the H8S/20103 group, AN8 to AN11 are not available. 7. The ADTRG1 and ADTRG2 functions are not available due to the initial setting of the PMC. 8. The H8S/20103 and H8S/20203 group do not incorporate A/D converter_2. 9. The H8S/20103 group does not provide P14 or P10. 10. The H8S/20103 group does not provide P97 to P90. 11. The H8S/20103 group does not provide PA3 to PA0. Rev. 1.00 Oct. 03, 2008 Page 20 of 962 REJ09B0465-0100 Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. 2.1 Features * Upward-compatibility with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H CPU object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes Rev. 1.00 Oct. 03, 2008 Page 21 of 962 REJ09B0465-0100 Section 2 CPU * High-speed operation All frequently-used instructions are executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B) 16 / 8-bit register-register divide: 12 states (DIVXU.B) 16 x 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) 32 / 16-bit register-register divide: 20 states (DIVXU.W) * Two CPU operating modes Normal mode Advanced mode * Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * The number of execution states of the MULXU and MULXS instructions Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. Rev. 1.00 Oct. 03, 2008 Page 22 of 962 REJ09B0465-0100 Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift and two-bit rotate instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions are executed twice as fast. Rev. 1.00 Oct. 03, 2008 Page 23 of 962 REJ09B0465-0100 Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Note that this LSI supports only advanced mode. Advanced mode supports a maximum 16-Mbyte address space. 2.2.1 Advanced Mode * Address space Linear access to a maximum address space of 16 Mbytes is possible. * Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers. * Instruction set All instructions and addressing modes can be used. * Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.1). For details of the exception vector table, see section 3, Exception Handling. Rev. 1.00 Oct. 03, 2008 Page 24 of 962 REJ09B0465-0100 Section 2 CPU H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved for system use) H'00000007 H'00000008 Exception vector table (Reserved for system use) H'00000014 Reserved Exception vector 1 Figure 2.1 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the top area of this range is also used for the exception vector table. Rev. 1.00 Oct. 03, 2008 Page 25 of 962 REJ09B0465-0100 Section 2 CPU * Stack structure In advanced mode, the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling. They are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 3, Exception Handling. SP PC (16 bits) SP (SP *2 ) EXR*1 Reserved*1*3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch Notes: 1. When EXR is not used, it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning. (b) Exception Handling Figure 2.2 Stack Structure in Advanced Mode Rev. 1.00 Oct. 03, 2008 Page 26 of 962 REJ09B0465-0100 Section 2 CPU 2.3 Address Space Figure 2.3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. Rev. 1.00 Oct. 03, 2008 Page 27 of 962 REJ09B0465-0100 Section 2 CPU H8S/20103 H'000000 Interrupt vectors H'000000 H8S/20102 Interrupt vectors On-chip flash ROM (128 kbytes) H'017FFF H'018000 H'01FFFF H'020000 On-chip flash ROM (96 kbytes) Reserved area Reserved area H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 kbytes) H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 kbytes) Reserved area H'FF0000 On-chip I/O registers H'FF0FFF H'FF1000 Reserved area H'FF0FFF H'FF1000 H'FF0000 Reserved area On-chip I/O registers Reserved area H'FFDF7F H'FFDF80 On-chip RAM (8 kbytes) H'FFFF7F H'FFFF80 On-chip I/O registers H'FFFFFF H'FFDF7F H'FFDF80 On-chip RAM (8 kbytes) H'FFFF7F H'FFFF80 On-chip I/O registers H'FFFFFF Figure 2.3 Memory Map (1) (H8S/20103 Group) Rev. 1.00 Oct. 03, 2008 Page 28 of 962 REJ09B0465-0100 Section 2 CPU H8S/20203 H'000000 Interrupt vectors H'000000 H8S/20202 Interrupt vectors On-chip flash ROM (128 kbytes) H'017FFF H'018000 H'01FFFF H'020000 On-chip flash ROM (96 kbytes) Reserved area Reserved area H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 kbytes) H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 kbytes) Reserved area H'FF0000 On-chip I/O registers H'FF0FFF H'FF1000 Reserved area H'FF0FFF H'FF1000 H'FF0000 Reserved area On-chip I/O registers Reserved area H'FFDF7F H'FFDF80 On-chip RAM (8 kbytes) H'FFFF7F H'FFFF80 On-chip I/O registers H'FFFFFF H'FFDF7F H'FFDF80 On-chip RAM (8 kbytes) H'FFFF7F H'FFFF80 On-chip I/O registers H'FFFFFF Figure 2.3 Memory Map (2) (H8S/20203 Group) Rev. 1.00 Oct. 03, 2008 Page 29 of 962 REJ09B0465-0100 Section 2 CPU H8S/20223 H'000000 Interrupt vectors H'000000 H8S/20222 Interrupt vectors On-chip flash ROM (128 kbytes) H'017FFF H'018000 H'01FFFF H'020000 On-chip flash ROM (96 kbytes) Reserved area Reserved area H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 kbytes) H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 kbytes) Reserved area H'FF0000 On-chip I/O registers H'FF0FFF H'FF1000 Reserved area H'FF0FFF H'FF1000 H'FF0000 Reserved area On-chip I/O registers Reserved area H'FFDF7F H'FFDF80 On-chip RAM (8 kbytes) H'FFFF7F H'FFFF80 On-chip I/O registers H'FFFFFF H'FFDF7F H'FFDF80 On-chip RAM (8 kbytes) H'FFFF7F H'FFFF80 On-chip I/O registers H'FFFFFF Figure 2.3 Memory Map (3) (H8S/20223 Group) Rev. 1.00 Oct. 03, 2008 Page 30 of 962 REJ09B0465-0100 Section 2 CPU 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.4. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers 23 PC 0 EXR T 76543210 - - - - I2 I1 I0 76543210 CCR I UI H U N Z V C Legend: SP PC EXR T I2 to I0 CCR I UI : Stack pointer : Program counter : Extended control register : Trace bit : Interrupt mask bits : Condition-code register : Interrupt mask bit : User bit or interrupt mask bit* H U N Z V C : Half-carry flag : User bit : Negative flag : Zero flag : Overflow flag : Carry flag Note: * For this LSI, the interrupt mask bit is not available. Figure 2.4 CPU Internal Registers Rev. 1.00 Oct. 03, 2008 Page 31 of 962 REJ09B0465-0100 Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.5 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The usage of each register can be selected independently. General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.6 shows the stack. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.5 Usage of General Registers Rev. 1.00 Oct. 03, 2008 Page 32 of 962 REJ09B0465-0100 Section 2 CPU Free area SP (ER7) Stack area Figure 2.6 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC instructions. When an instruction other than STC is executed, all interrupts including NMI are masked in three states after the instruction is completed. Bit 7 Symbol T Bit Name Trace bit Description 0: Consecutively executes instructions. 1: Starts trace exception processing each time an instruction is executed. 6 to 3 2 to 0 I2* I1 I0 Note: * Reserved Interrupt request mask level 2 to 0 These bits are always read as 1. These bits specify interrupt request mask levels (0 to 3). For details, see section 4, Interrupt Controller. R/W R/W R/W The I2-bit is reserved in this product. The I2 bit is set to 1 if an interrupt is accepted, but this does not affect the mask level for interrupt requests. Rev. 1.00 Oct. 03, 2008 Page 33 of 962 REJ09B0465-0100 Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Bit 7 6 Symbol I UI Bit Name Interrupt mask bit User bit or interrupt mask bit Half-carry flag Description 0: Does not mask interrupts. 1: Masks interrupts. This bit does not affect this LSI operation. R/W R/W R/W 5 H [Setting conditions] * If there is a carry or borrow bit 3 when the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or NEG.B instruction is executed. If there is a carry or borrow at bit 11 when the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed. If there is a carry or borrow at bit 27 when the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed. R/W * * [Clearing condition] When none of the above setting conditions are satisfied. 4 3 U N User bit Negative flag This bit does not affect the LSI operation. [Setting condition] When the execution result is negative. [Clearing condition] When the execution result is not negative. R/W R/W Rev. 1.00 Oct. 03, 2008 Page 34 of 962 REJ09B0465-0100 Section 2 CPU Bit 2 Symbol Z Bit Name Zero flag Description [Setting condition] When data is zero. [Clearing condition] When data is not zero. R/W R/W 1 V Overflow flag [Setting condition] When an overflow occurs after an arithmetic instruction has been executed. [Clearing condition] When no overflow occurs after an arithmetic instruction has been executed. R/W 0 C Carry flag [Setting condition] When a carry occurs after an instruction has been executed. [Clearing condition] When no carry occurs after an instruction has been executed. R/W * I (interrupt mask bit) This bit masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, see section 4, Interrupt Controller. * UI (user bit/interrupt mask bit) This bit can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. For this LSI, interrupt mask bit is not available. * H (half carry flag) When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Rev. 1.00 Oct. 03, 2008 Page 35 of 962 REJ09B0465-0100 Section 2 CPU * U (user bit) This bit can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. * N (negative bit) This bit stores the value of the most significant bit of data as a sign bit. * C (carry flag) This flag is set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 1.00 Oct. 03, 2008 Page 36 of 962 REJ09B0465-0100 Section 2 CPU 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.7 shows the data formats of general registers. Data Type 1-bit data Register Number RnH Data Format 7 0 Don't care 76 54 32 10 7 1-bit data RnL Don't care 0 76 54 32 10 7 4-bit BCD data RnH Upper 43 Lower 0 Don't care 7 4-bit BCD data RnL Don't care Upper 43 Lower 0 7 Byte data RnH MSB 0 Don't care LSB 7 0 LSB Byte data RnL Don't care MSB Figure 2.7 General Register Data Formats (1) Rev. 1.00 Oct. 03, 2008 Page 37 of 962 REJ09B0465-0100 Section 2 CPU Data Type Word data Register Number Rn Data Format 15 0 MSB LSB Word data 15 En 0 MSB LSB Longword data 31 ERn 16 15 0 MSB En Rn LSB Legend: ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.7 General Register Data Formats (2) Rev. 1.00 Oct. 03, 2008 Page 38 of 962 REJ09B0465-0100 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.8 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 Data Format 0 0 Byte data Address L MSB LSB Word data Address 2M Address 2M+1 MSB LSB Longword data Address 2N Address 2N+1 Address 2N+2 Address 2N+3 MSB LSB Figure 2.8 Memory Data Formats Rev. 1.00 Oct. 03, 2008 Page 39 of 962 REJ09B0465-0100 Section 2 CPU 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV POP*1, PUSH*1 LDM*5, STM*5 MOVFPE*3, MOVTPE*3 Size B/W/L W/L L B B/W/L B B/W/L L B/W W/L B B/W/L B/W/L B 4 8 14 5 9 1 Total: 65 19 Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*4 Logic operations Shift Bit manipulation Branch System control Block data transfer AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR BCC*2, JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV Notes: B: Byte size; W: Word size; L: Longword size. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. BCC is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 5. The ER7 register is used as a stack pointer in an STM and LDM instructions. Accordingly, ER7 cannot be stored by STM or loaded by LDM. Rev. 1.00 Oct. 03, 2008 Page 40 of 962 REJ09B0465-0100 Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Symbol Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: * Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 1.00 Oct. 03, 2008 Page 41 of 962 REJ09B0465-0100 Section 2 CPU Table 2.3 Instruction MOV Data Transfer Instructions 1 Size* Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. B/W/L MOVFPE MOVTPE POP B B W/L Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn PUSH W/L Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. LDM* 2 L L @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. STM* 2 Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. The ER7 register is used as a stack pointer in the STM and LDM instructions. Accordingly, ER7 cannot be stored by STM or loaded by LDM. Rev. 1.00 Oct. 03, 2008 Page 42 of 962 REJ09B0465-0100 Section 2 CPU Table 2.4 Instruction ADD SUB Arithmetic Operations Instructions (1) Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.) B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register. B/W/L Rd 1 Rd, Rd 2 Rd Adds or subtracts the value 1 or 2 to or from data in a general register. (Only the value 1 can be added to or subtracted from byte operands.) L Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. B Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data. B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Oct. 03, 2008 Page 43 of 962 REJ09B0465-0100 Section 2 CPU Table 2.4 Instruction DIVXS Arithmetic Operations Instructions (2) 1 Size* Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16bit quotient and 16-bit remainder. B/W CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. 2 TAS* B @ERd - 0, 1 ( Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 1.00 Oct. 03, 2008 Page 44 of 962 REJ09B0465-0100 Section 2 CPU Table 2.5 Instruction AND Logic Operations Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L Rd Rd Takes the one's complement (logical complement) of data in a general register. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Oct. 03, 2008 Page 45 of 962 REJ09B0465-0100 Section 2 CPU Table 2.6 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Shift Instructions Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L Rd (shift) Rd Performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. B/W/L B/W/L Rd (rotate) Rd Rotates data in a general register. 1-bit or 2 bit rotation is possible. Rd (rotate) Rd Rotates data including the carry flag in a general register. 1-bit or 2 bit rotation is possible. Size refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Oct. 03, 2008 Page 46 of 962 REJ09B0465-0100 Section 2 CPU Table 2.7 Instruction BSET Bit Manipulation Instructions (1) Size* B Function 1 ( BCLR B 0 ( BNOT B ( BTST B ( BAND B C ( BIAND B C ( BOR B C ( BIOR B C ( Note: * Size refers to the operand size. B: Byte Rev. 1.00 Oct. 03, 2008 Page 47 of 962 REJ09B0465-0100 Section 2 CPU Table 2.7 Instruction BXOR Bit Manipulation Instructions (2) Size* B Function C ( BIXOR B C ( BLD B ( BILD B ( BST B C ( BIST B C ( Note: * Size refers to the operand size. B: Byte Rev. 1.00 Oct. 03, 2008 Page 48 of 962 REJ09B0465-0100 Section 2 CPU Table 2.8 Instruction Bcc Branch Instructions Size Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 JMP BSR JSR RTS Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine Rev. 1.00 Oct. 03, 2008 Page 49 of 962 REJ09B0465-0100 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory operand. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC ORC XORC B B B CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP Note: * PC + 2 PC Only increments the program counter. Size refers to the operand size. B: Byte W: Word Rev. 1.00 Oct. 03, 2008 Page 50 of 962 REJ09B0465-0100 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction EEPMOV.B Size Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next: if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next: Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W 2.6.2 Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.9 shows examples of instruction formats. * Operation field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields, and some have no register field. * Effective address extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition field Specifies the branching condition of Bcc instructions. Rev. 1.00 Oct. 03, 2008 Page 51 of 962 REJ09B0465-0100 Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) rn rm MOV.B @(d:16, Rn), Rm, etc. (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.9 Instruction Formats (Examples) Rev. 1.00 Oct. 03, 2008 Page 52 of 962 REJ09B0465-0100 Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 2.7.1 Register Direct--Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). Rev. 1.00 Oct. 03, 2008 Page 53 of 962 REJ09B0465-0100 Section 2 CPU 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.4 (1) Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn Register Indirect with Post-Increment--@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. (2) Register Indirect with Pre-Decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, and 4 for longword access. For word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address, the upper 16 bits are a sign extension. For a 32-bit absolute address, the entire address space is accessed. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Rev. 1.00 Oct. 03, 2008 Page 54 of 962 REJ09B0465-0100 Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32 The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction code can be used directly as an operand. The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit address indicated by the PC value to generate a 24-bit branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. Rev. 1.00 Oct. 03, 2008 Page 55 of 962 REJ09B0465-0100 Section 2 CPU 2.7.8 Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'000000 to H'0000FF in advanced mode). In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the top area of the address range in which the branch address is stored is also used for the exception vector area. For further details, see section 3, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or the instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Specified by @aa:8 Reserved Branch address Advanced Mode Figure 2.10 Branch Address Specification in Memory Indirect Addressing Mode Rev. 1.00 Oct. 03, 2008 Page 56 of 962 REJ09B0465-0100 Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. Table 2.13 Effective Address Calculation No 1 Addressing Mode and Instruction Format Register direct (Rn) Effective Address Calculation Effective Address (EA) Operand is general register contents. op 2 rm rn 31 General register contents Register indirect (@ERn) 0 31 24 23 0 Don't care op 3 r Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 31 General register contents 0 31 24 23 0 op r disp 31 Sign extension Don't care 0 disp 4 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 31 General register contents 0 31 24 23 0 Don't care op r 31 1, 2, or 4 * Register indirect with pre-decrement @-ERn 0 General register contents 31 24 23 0 Don't care op r Operand Size Byte Word Longword 1, 2, or 4 Offset 1 2 4 Rev. 1.00 Oct. 03, 2008 Page 57 of 962 REJ09B0465-0100 Section 2 CPU No 5 Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA) @aa:8 op abs 31 24 23 H'FFFF 87 0 Don't care @aa:16 op abs 31 24 23 16 15 0 Don't care Sign extension @aa:24 op abs 31 24 23 0 Don't care @aa:32 op abs 31 24 23 0 Don't care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 * Normal mode* 31 op abs H'000000 15 87 abs 0 0 Memory contents 31 24 23 16 15 H'00 0 Don't care * Advanced mode 31 op abs 31 Memory contents 87 H'000000 abs 0 31 24 23 Don't care 0 0 Note: * For this LSI, normal mode is not available. Rev. 1.00 Oct. 03, 2008 Page 58 of 962 REJ09B0465-0100 Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.11 indicates the state transitions. * Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, see section 3, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, see section 3, Exception Handling. * Program execution state In this state the CPU executes program instructions in sequence. * Bus-released state The bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed. For details, see section 6, Power-Down Modes. Rev. 1.00 Oct. 03, 2008 Page 59 of 962 REJ09B0465-0100 Section 2 CPU Reset state* re le a se es qu t re se Re Re se t re q ue st Re s t re qu e et st t Exception handling state Re se Bus-released state Request for exception handling End of exception handling d En of bu Re ex que ce st pti fo on r ha n SLEEP instruction dli n g Program stop state Program execution state Note: * A transition to the reset state occurs in any of the following cases. 1. When RES goes low in any state 2. When the watchdog timer overflows 3. When an LVD reset is caused by a low-voltage detection Figure 2.11 State Transitions Rev. 1.00 Oct. 03, 2008 Page 60 of 962 REJ09B0465-0100 Bus request e sr End of bus request Bu s qu re es t t es qu e Res t req t ues Section 2 CPU 2.9 2.9.1 Usage Notes TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The H8S and H8/300 Series C/C++ Compiler of Renesas Technology Corp. does not generate a TAS instruction. Accordingly, when a TAS instruction is used as a user-defined embedded function, register ER0, ER1, ER4, or ER5 should be used. 2.9.2 STM and LDM Instructions The ER7 register is used as a stack pointer in an STM and LDM instructions. Accordingly, ER7 cannot be stored by STM or loaded by LDM. Two, three, or four registers can be stored or loaded by a single STM or LDM instruction. The combination of registers that can be stored or loaded are as follows. * Two registers: ER0 and ER1, ER2 and ER3, or ER4 and ER5 * Three registers: ER0 to ER2 or ER4 to ER6 * Four registers: ER0 to ER3 The H8S and H8/300 Series C/C++ Compiler of Renesas Technology Corp. does not generate an STM or LDM instruction that uses ER7. 2.9.3 Note on Bit Manipulation Instructions Bit manipulation instructions such as BSET, BCLR, BNOT, BST, and BIST read data in byte units, perform bit manipulation, and write data in byte units. Thus, care must be taken when these bit manipulation instructions are executed for a register or port including write-only bits. In addition, the BCLR instruction can be used to clear the flag of an internal I/O register. In this case, if the flag to be cleared has been set by an interrupt processing routine, the flag need not be read before executing the BCLR instruction. Rev. 1.00 Oct. 03, 2008 Page 61 of 962 REJ09B0465-0100 Section 2 CPU 2.9.4 EEPMOVE Instruction 1. The EEPMOVE instruction performs a block transfer. As shown in the following figure, EEPMOV transfers data whose start address is indicated by R5 for the number of bytes indicated by R4L to the address indicated by R6. R5 R6 R5 + R4L R6 + R4L 2. R4L and R6 should be set so that the end address (R6 + R4L) of the transfer destination does not exceed H'FFFF (R6 should not change from H'FFFF to H'0000 during EEPMOV instruction execution). R5 R6 R5 + R4L Cannot be set H'FFFF R6 + R4L Rev. 1.00 Oct. 03, 2008 Page 62 of 962 REJ09B0465-0100 Section 3 Exception Handling Section 3 Exception Handling 3.1 Exception Handling Types and Priority As table 3.1 indicates, exception handling is caused by a reset, trace, NMI interrupt, trap instruction, or interrupt. Exception handling is prioritized as shown in table 3.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, see section 4, Interrupt Controller. Table 3.1 Priority High Exception Handling Types and Priority Exception Type Reset Start Timing of Exception Handling Started immediately after a low-to-high transition at the RES pin, or by other reset sources. The CPU enters the reset state when the RES pin is low. Started when execution of the current instruction or exception handling ends, if the trace (T) bit in EXR is set to 1. Generated when an edge of the NMI pin is input. An NMI interrupt request has the highest priority among interrupt requests. It is always accepted regardless of the value of the I bit in CCR. Started by execution of a trap instruction (TRAPA). Started when execution of the current instruction or exception handling ends, if an interrupt request has been issued.*2 Trace*1 NMI Trap instruction*3 Low Interrupt Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state. 3.2 Exception Handling Sources and Vector Table Different vector addresses are assigned to different exception sources. For details on the exception sources and their vector addresses, see section 4, Interrupt Controller. Rev. 1.00 Oct. 03, 2008 Page 63 of 962 REJ09B0465-0100 Section 3 Exception Handling 3.3 Reset A reset has the highest exception handling priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for the specified time at power-on and during operation, hold the RES pin low for the specified time. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules, and selects low-speed on-chip oscillator as a system clock. The chip can also be reset by detection of the low-voltage, overflow of the watchdog timer, or software. The interrupt control mode is 0 immediately after reset. 3.3.1 Reset Sources This LSI enters the reset state by reset sources listed in table 3.2. If multiple reset sources occur simultaneously, a reset source having the highest priority will be accepted. A reset source can be identified by reading the reset source flag register (RSTFR). For details on a low-voltage detection reset, see section 26, Low-Voltage Detection Circuits. For details on a watchdog timer overflow reset, see section 19, Watchdog Timer (WDT). Table 3.2 List of Reset Sources Description Priority This LSI enters the reset state if the RES pin is held low for High at least a specified period. This LSI enters the reset state if the power voltage becomes the specified voltage or lower. This LSI enters the reset state if the counter in the watchdog timer overflows. This LSI enters the reset state if the SRST bit in RSTCR is set to 1. Low Reset Source Reset by RES pin Low-voltage detection reset Watchdog timer overflow reset Software reset Rev. 1.00 Oct. 03, 2008 Page 64 of 962 REJ09B0465-0100 Section 3 Exception Handling (1) Reset Source Flag Register (RSTFR) Address: H'FF0620 Bit: b7 b6 0 b5 SWRST (0) b4 PRST (0) b3 LVD2RST (0) b2 LVD1RST (0) b1 PORRST (0) b0 WRST (0) Value after reset: 0 Bit 7 6 5 Symbol SWRST Bit Name Reserved Description This bit is read as 0. The write value should be 0. R/W Software reset detection flag RES pin reset detection flag LVD2 reset detection flag LVD1 reset detection flag LVD0 reset detection flag 1: Indicates that a reset by a software reset occurs. R/W 0: Indicates that a reset by a software reset does not occur. 1: Indicates that a reset by a RES pin reset occurs. R/W 0: Indicates that a reset by a RES pin reset does not occur. 1: Indicates that a reset by a LVD2 reset occurs. 0: Indicates that a reset by a LVD2 reset does not occur. 1: Indicates that a reset by a LVD1 reset occurs. 0: Indicates that a reset by a LVD1 reset does not occur. 1: Indicates that a reset by a LVD0 reset occurs. 0: Indicates that a reset by a LVD0 reset does not occur. R/W R/W R/W R/W 4 PRST 3 LVD2RST 2 LVD1RST 1 PORRST 0 WRST Watchdog timer 1: Indicates that a reset by a watchdog timer reset detection overflows. flag 0: Indicates that a reset by a watchdog timer does not occur. Note: Each flag in this register can be cleared by writing 0 to it. The write value to the reserved bits should always be 0. Rev. 1.00 Oct. 03, 2008 Page 65 of 962 REJ09B0465-0100 Section 3 Exception Handling (2) Reset Control Register (RSTCR) Address: Bit: H'FF06DA b7 WI b6 WE 0 b5 b4 b3 b2 b1 b0 SRST 0 Value after reset: 1 0 0 0 0 0 Bit 7 6 Symbol WI WE Bit Name Write inhibit Write enable Description 0: Writing is permitted. 1: Writing is inhibited. 0: Writing is disabled. 1: Writing is enabled. [Setting condition] When 0 is written to WI and 1 is written to WE. [Clearing condition] When 0 is written to WI and WE. R/W W R/W 5 to 1 0 SRST Reserved Software reset These bits are read as 0. The write value should be 0. 0: Normal operation 1: A software reset is generated. R/W Note: A MOV instruction should be used to write to this register. * WI bit (write inhibit) This register can be written to only when this bit is 0. This bit is always read as 1. * WE bit (write enable) Bit 0 in this register can be written to when this bit is 1. * SRST bit (software reset) A software reset is generated when this bit is 1. Rev. 1.00 Oct. 03, 2008 Page 66 of 962 REJ09B0465-0100 Section 3 Exception Handling 3.3.2 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, VOFR is cleared to H'0000, the T bit in EXR is cleared to 0, and the I bit in EXR and CCR is set to 1. 2. The low-speed on-chip oscillator is selected as a system clock. 3. After the reset exception handling vector address is read and transferred to the PC, program execution starts from the address indicated by the PC. Figure 3.1 shows an example of the reset sequence. Internal Prefetch of first processing program instruction Vector fetch RES Internal address bus (1) (3) (5) Internal read signal Internal write signal Internal data bus (1) (3) (2) (4) (5) (6) High (2) (4) (6) :Reset exeption handling vector address (when reset, (1) = H'000000, (3) = H'000002) :Start address (contents of reset exception handling vector address) :Start address ((5) = (2)(4)) :First program instruction Figure 3.1 Reset Sequence Rev. 1.00 Oct. 03, 2008 Page 67 of 962 REJ09B0465-0100 Section 3 Exception Handling 3.3.3 Interrupts immediately after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 3.3.4 On-Chip Peripheral Functions after Reset Release After release from a reset, MSTCR is initialized, and the DTC and all modules other than timer RE enter module standby mode. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when module standby mode is exited. Rev. 1.00 Oct. 03, 2008 Page 68 of 962 REJ09B0465-0100 Section 3 Exception Handling 3.4 Trace Exception Handling Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 4, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by the interrupt masking bit in CCR. Table 3.3 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and trace mode resumes when control is returned from the trace exception handling routine by the RTE instruction. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 3.3 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode 0 2 1 [Legend] 1: Set to 1 0: Cleared to 0 : Retains value prior to execution. I UI I2 to I0 EXR T Trace exception handling cannot be used. 0 Rev. 1.00 Oct. 03, 2008 Page 69 of 962 REJ09B0465-0100 Section 3 Exception Handling 3.5 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to four priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, see section 4, Interrupt Controller. The interrupt exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. 3.6 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 3.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Rev. 1.00 Oct. 03, 2008 Page 70 of 962 REJ09B0465-0100 Section 3 Exception Handling Table 3.4 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR I2 to I0 T 0 Interrupt Control Mode 0 2 I 1 1 UI [Legend] 1: Set to 1 0: Cleared to 0 : Retains value prior to execution. 3.7 Stack Status after Exception Handling Figure 3.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Advanced Modes SP EXR Reserved* SP CCR PC (24 bits) CCR PC (24 bits) Interrupt control mode 0 Note: * Ignored on return. Interrupt control mode 2 Figure 3.2 Stack Status after Exception Handling Rev. 1.00 Oct. 03, 2008 Page 71 of 962 REJ09B0465-0100 Section 3 Exception Handling 3.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 3.3 shows an example of operation when the SP value is odd. Address CCR SP PC SP R1L H'FFFEFA H'FFFEFB PC H'FFFEFC H'FFFEFD H'FFFEFE SP H'FFFEFF TRAPA instruction executed SP set to H'FFFEFF [Legend] CCR : Condition code register PC : Program counter R1L : General register R1L SP : Stack pointer MOV.B R1L,@-ER7 Instruction executed Data saved above SP Contents of CCR lost Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 3.3 Operation when SP Value Is Odd Rev. 1.00 Oct. 03, 2008 Page 72 of 962 REJ09B0465-0100 Section 4 Interrupt Controller Section 4 Interrupt Controller 4.1 Features * Two interrupt control modes Either of the two interrupt control modes can be selected by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Four priority levels can be set for each module for all interrupts except NMI. NMI and some flash memory interrupts are assigned the highest priority level of 3, and can be accepted at all times. * Independent vector addresses Most interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Nine external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edges can be selected independently for IRQ7 to IRQ0. * DTC control DTC activation is performed by means of interrupt requests. Rev. 1.00 Oct. 03, 2008 Page 73 of 962 REJ09B0465-0100 Section 4 Interrupt Controller A block diagram of the interrupt controller is shown in figure 4.1. INTM1 INTM0 INTCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Internal interrupt sources IAD to ITGUD IPR Interrupt controller Priority determination I I1 to I0 Interrupt request Vector number CPU CCR EXR Figure 4.1 Block Diagram of Interrupt Controller Table 4.1 shows the pin configuration of the interrupt controller. Table 4.1 Name NMI IRQ7 to IRQ0 Pin Configuration I/O Input Input Function Nonmaskable external interrupt Rising or falling edge can be selected. Maskable external interrupts Rising, falling, or both edges can be selected independently. Rev. 1.00 Oct. 03, 2008 Page 74 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.2 * * * * * * * * * * * * * * * * * Register Descriptions Interrupt control register (INTCR) IRQ sense control register H (ISCRH) IRQ sense control register L (ISCRL) IRQ enable register (IER) IRQ status register (ISR) Interrupt priority register A (IPRA) Interrupt priority register B (IPRB) Interrupt priority register C (IPRC) Interrupt priority register D (IPRD) Interrupt priority register E (IPRE) Interrupt priority register F (IPRF) Interrupt priority register G (IPRG) Interrupt priority register H (IPRH) Interrupt priority register I (IPRI) Interrupt vector offset register (VOFR) IRQ noise canceler control register (INCCR) Event link interrupt control status register (ELCSR) Rev. 1.00 Oct. 03, 2008 Page 75 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.2.1 Interrupt Control Register (INTCR) Address: H'FF0520 Bit: b7 b6 b5 INTM[1:0] 0 b4 b3 NMIEG b2 ADTRG1 0 b1 ADTRG0 0 b0 Value after reset: 0 0 0 0 0 Bit 7 6 5 4 Symbol INTM[1:0] Bit Name Reserved Interrupt control select mode 1 and 0 Description These bits are read as 0. The write value should be 0. 00: Interrupt control mode 0 Interrupts are controlled by the I bit. 01: Setting prohibited 10: Interrupt control mode 2 Interrupts are controlled by bits I1 and I0, and IPR. 11: Setting prohibited R/W R/W 3 NMIEG NMI edge select 0: Interrupt request is generated at falling edge of NMI input. 1: Interrupt request is generated at rising edge of NMI input. R/W 2 ADTRG1 ADTRG2 edge select 0: AD1 or AD2 conversion is started at falling edge R/W of ADTRG2 input. 1: AD1 or AD2 conversion is started at rising edge of ADTRG2 input. 1 ADTRG0 ADTRG1 edge select 0: AD1 or AD2 conversion is started at falling edge R/W of ADTRG1 input. 1: AD1 or AD2 conversion is started at rising edge of ADTRG1 input. 0 Reserved This bit is read as 0. The write value should be 0. * INTM1 and INTM0 bits (interrupt control select mode 1 and 0) These bits select the interrupt control mode for the interrupt controller. * NMIEG bit (NMI edge select) Selects the input edge for the NMI pin. Rev. 1.00 Oct. 03, 2008 Page 76 of 962 REJ09B0465-0100 Section 4 Interrupt Controller * ADTRG1 and ADTRG0 bits (ADTRG2 and ADTRG1 edge select) These bits select the input edge for the ADTRG2 and ADTRG1 pins. 4.2.2 Interrupt Priority Registers A to I (IPRA to IPRI) * IPRA to IPRK Address: H'FF0529 to H'FF0531 Bit: b7 IPRn[7:6] Value after reset: 1 1 1 b6 b5 IPRn[5:4] 1 1 b4 b3 IPRn[3:2] 1 1 b2 b1 IPRn[1:0] 1 (n = A to I) b0 Bit 7 6 Symbol IPRn[7:6] Bit Name Description R/W R/W Interrupt priority 00: Priority level 0 (lowest) 7 and 6 01: Priority level 1 10: Priority level 2 11: Priority level 3 (highest) Interrupt priority 00: Priority level 0 (lowest) 5 and 4 01: Priority level 1 10: Priority level 2 11: Priority level 3 (highest) Interrupt priority 00: Priority level 0 (lowest) 3 and 2 01: Priority level 1 10: Priority level 2 11: Priority level 3 (highest) Interrupt priority 00: Priority level 0 (lowest) 1 and 0 01: Priority level 1 10: Priority level 2 11: Priority level 3 (highest) 5 4 IPRn[5:4] R/W 3 2 IPRn[3:2] R/W 1 0 IPRn[1:0] R/W [Legend] n = A to I * IPR7 to IPR0 bits (Interrupt priority 7 to 0) IPR are nine 8-bit readable/writable registers that set priorities (levels 3 to 0) for interrupt sources other than Nonmaskable interrupt request (NMI). The correspondence between interrupt sources and IPR settings is shown in table 4.2. Setting a value in the range from H'0 to H'3 in the 2-bit groups of bits 7 and 6, 5and 4, 3 and 2, and, 1 and 0 determines the priority of the corresponding interrupt requests. Rev. 1.00 Oct. 03, 2008 Page 77 of 962 REJ09B0465-0100 Section 4 Interrupt Controller Table 4.2 Correspondence between Interrupt Sources and IPR Settings Bit 6 Bit 5 Bit 4 WDT IRQ1 IRQ5 A/D converter unit 2*1 SCI3 channel 2 Timer RA Timer RD unit 0 channel 1 Bit 3 Bit 2 LVD IRQ2 IRQ6 DTC SCI3 channel 3 IIC2/SSU Timer RB Timer RD unit 1 channel 2*3 Timer RG Bit 1 Bit 0 CPG IRQ3 IRQ7 ELC Timer RC*2 Timer RD unit 1 channel 3*3 Register Bit 7 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI Flash memory IRQ0 IRQ4 A/D converter unit 1 SCI3 channel 1 Timer RD unit 0 channel 0 Timer RE Notes: : Reserved 1. Provided for the H8S/20223 group only. 2. Provided for the H8S/20103 group only. 3. Not provided for the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 78 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.2.3 IRQ Enable Register (IER) Address: H'FF0521 Bit: b7 IRQ7E b6 IRQ6E 0 b5 IRQ5E 0 b4 IRQ4E 0 b3 IRQ3E 0 b2 IRQ2E 0 b1 IRQ1E 0 b0 IRQ0E 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Bit Name IRQ7 enable IRQ6 enable IRQ5 enable IRQ4 enable IRQ3 enable IRQ2 enable IRQ1 enable IRQ0 enable Description 0: IRQ7 interrupts are disabled. 1: IRQ7 interrupts are enabled. 0: IRQ6 interrupts are disabled. 1: IRQ6 interrupts are enabled. 0: IRQ5 interrupts are disabled. 1: IRQ5 interrupts are enabled. 0: IRQ4 interrupts are disabled. 1: IRQ4 interrupts are enabled. 0: IRQ3 interrupts are disabled. 1: IRQ3 interrupts are enabled. 0: IRQ2 interrupts are disabled. 1: IRQ2 interrupts are enabled. 0: IRQ1 interrupts are disabled. 1: IRQ1 interrupts are enabled. 0: IRQ0 interrupts are disabled. 1: IRQ0 interrupts are enabled. R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 79 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.2.4 IRQ Sense Control Register H and L (ISCRH and ISCRL) * ISCRH Address: H'FF0522 Bit: b7 IRQ7SCB Value after reset: 0 b6 IRQ7SCA 1 b5 IRQ6SCB 0 b4 IRQ6SCA 1 b3 IRQ5SCB 0 b2 IRQ5SCA 1 b1 IRQ4SCB 0 b0 IRQ4SCA 1 * ISCRL Address: H'FF0523 Bit: b7 IRQ3SCB Value after reset: 0 b6 IRQ3SCA 1 b5 IRQ2SCB 0 b4 IRQ2SCA 1 b3 IRQ1SCB 0 b2 IRQ1SCA 1 b1 IRQ0SCB 0 b0 IRQ0SCA 1 * ISCRH Bit 7 6 Symbol IRQ7SCB IRQ7SCA Bit Name IRQ7 sense control B and A Description 00: Reserved (setting prohibited) 01: Interrupt request is generated at falling edge of IRQ7 input. 10: Interrupt request is generated at rising edge of IRQ7 input. 11: Interrupt request is generated at both falling and rising edges of IRQ7 input. 5 4 IRQ6SCB IRQ6SCA IRQ6 sense control B and A 00: Reserved (setting prohibited) 01: Interrupt request is generated at falling edge of IRQ6 input. 10: Interrupt request is generated at rising edge of IRQ6 input. 11: Interrupt request is generated at both falling and rising edges of IRQ6 input. R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 80 of 962 REJ09B0465-0100 Section 4 Interrupt Controller Bit 3 2 Symbol IRQ5SCB IRQ5SCA Bit Name IRQ5 sense control B and A Description 00: Reserved (setting prohibited) 01: Interrupt request is generated at falling edge of IRQ5 input. 10: Interrupt request is generated at rising edge of IRQ5 input. 11: Interrupt request is generated at both falling and rising edges of IRQ5 input. R/W R/W 1 0 IRQ4SCB IRQ4SCA IRQ4 sense control B and A 00: Reserved (setting prohibited) 01: Interrupt request is generated at falling edge of IRQ4 input. 10: Interrupt request is generated at rising edge of IRQ4 input. 11: Interrupt request is generated at both falling and rising edges of IRQ4 input. R/W Rev. 1.00 Oct. 03, 2008 Page 81 of 962 REJ09B0465-0100 Section 4 Interrupt Controller * ISCRL Bit 7 6 Symbol IRQ3SCB IRQ3SCA Bit Name IRQ3 sense control B and A Description 00: Reserved (setting prohibited) 01: Interrupt request is generated at falling edge of IRQ3 input. 10: Interrupt request is generated at rising edge of IRQ3 input. 11: Interrupt request is generated at both falling and rising edges of IRQ3 input. 5 4 IRQ2SCB IRQ2SCA IRQ2 sense control B and A 00: Reserved (setting prohibited) 01: Interrupt request is generated at falling edge of IRQ2 input. 10: Interrupt request is generated at rising edge of IRQ2 input. 11: Interrupt request is generated at both falling and rising edges of IRQ2 input. 3 2 IRQ1SCB IRQ1SCA IRQ1 sense control B and A 00: Reserved (setting prohibited) 01: Interrupt request is generated at falling edge of IRQ1 input. 10: Interrupt request is generated at rising edge of IRQ1 input. 11: Interrupt request is generated at both falling and rising edges of IRQ1 input. 1 0 IRQ0SCB IRQ0SCA IRQ0 sense control B and A 00: Reserved (setting prohibited) 01: Interrupt request is generated at falling edge of IRQ0 input. 10: Interrupt request is generated at rising edge of IRQ0 input. 11: Interrupt request is generated at both falling and rising edges of IRQ0 input. R/W R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 82 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.2.5 IRQ Status Register (ISR) Address: H'FF0524 Bit: b7 IRQ7F b6 IRQ6F 0 b5 IRQ5F 0 b4 IRQ4F 0 b3 IRQ3F 0 b2 IRQ2F 0 b1 IRQ1F 0 b0 IRQ0F 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Bit Name IRQ7 flag IRQ6 flag IRQ5 flag IRQ4 flag IRQ3 flag IRQ2 flag IRQ1 flag IRQ0 flag Description [Setting condition] * When the interrupt source selected by ISCR occurs. R/W R/W R/W R/W [Clearing conditions] * * R/W When 1 is read from the bit and then 0 is written to R/W the same bit. R/W When IRQn interrupt exception handling is R/W executed while falling, rising, or both-edge R/W detection is set. When the DTC is activated by an IRQn interrupt and the DISEL bit in MRB of the DTC is 0. * Rev. 1.00 Oct. 03, 2008 Page 83 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.2.6 IRQ Noise Canceler Control Register (INCCR) Address: H'FF0525 Bit: b7 b6 b5 b4 INCCR[5:4] b3 INCCR[3:2] b2 b1 INCCR[1:0] b0 Value after reset: 0 0 1 1 1 1 1 1 Bit 7 6 5 4 Bit Name INCCR[5:4] Initial Value Reserved Description These bits are always read as 0. The write value should always be 0. R/W R/W Noise cancel 00: TBD performance setting 01: Twice of the TBD 5 and 4 for NMI pin 10: Four times of the TBD 11: Eight times of the TBD Noise cancel 00: TBD performance setting 01: Twice of the TBD 3 and 2 for IRQ7 to 10: Four times of the TBD IRQ4 pins 11: Eight times of the TBD Noise cancel 00: TBD performance setting 01: Twice of the TBD 1 and 0 for IRQ3 to 10: Four times of the TBD IRQ0 pins 11: Eight times of the TBD 3 2 INCCR[3:2] R/W 1 0 INCCR[1:0] R/W Note: Noise cancel performance varies according to the manufacturing condition, temperature, and VCC. Rev. 1.00 Oct. 03, 2008 Page 84 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.2.7 Interrupt Vector Offset Register (VOFR) Address: H'FF0526 Bit: b15 b14 b13 b12 b11 b10 b9 bit9 0 b8 bit8 0 b7 bit7 0 b6 bit6 0 b5 bit5 0 b4 bit4 0 b3 bit3 0 b2 bit2 0 b1 bit1 0 b0 bit0 0 bit15 bit14 Value after reset: 0 0 bit13 bit12 bit11 bit10 0 0 0 0 MSB bit15 bit14 bit13 bit12 bit11 bit10 bit9 LSB bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 VOFR + Interrupt vector base address 0 0 0 0 0 0 0 0 0 0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 Vector address A8 A7 A6 A5 A4 A3 A2 A1 A0 VOFR is a 16-bit readable/writable register that sets an offset for an interrupt vector address. Interrupt vector areas other than the trace interrupt area and trap instruction interrupt area can be varied with the offset. The upper 13 bits are used to set the offset for the interrupt vector address (A23 to A11). Bits 2 to 0 are reserved. The write value should always be 0. This register also can be accessed in 8-bit units. The vector address can be obtained by adding the VOFR value to the interrupt vector base address as shown above, except for the trace interrupt and trap instruction interrupt. This register is initialized to H'0000 by a reset. Rev. 1.00 Oct. 03, 2008 Page 85 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.2.8 Event Link Interrupt Control Status Register (ELCSR) Address: H'FF0528 Bit: b7 b6 b5 b4 b3 ELIE2 0 b2 ELIE1 0 b1 ELF2 0 b0 ELF1 0 Value after reset: 0 0 0 0 Bit 7 to 4 3 2 1 Symbol ELIE2 ELIE1 ELF2 Bit Name Reserved Description These bits are read as 0. The write value should be 0. R/W R/W R/W R/W 1 ELC interrupt 2 0: ELF2 interrupts are disabled. enable 1: ELF2 interrupts are enabled. ELC interrupt 1 0: ELF1 interrupts are disabled. enable 1: ELF1 interrupts are enabled. ELC interrupt flag 2 [Setting condition] * * * When the event selected by ELSR30 occurs* When 1 is read from this bit and then 0 is written to the same bit. When the DTC is activated by an ELF2 interrupt, and the DISEL bit in MRB of the DTC 2 is 0.* [Clearing conditions] 0 ELF1 ELC interrupt flag 1 [Setting condition] * * * When the event selected by ELSR12 occurs* When 1 is read from this bit and then 0 is written to the same bit. When the DTC is activated by an ELF1 interrupt, and the DISEL bit in MRB of the DTC is 0.*2 1 R/W [Clearing conditions] Notes: 1. For details, see section 12, Event Link Controller. 2. When the DTC is activated by an ELF1 or ELF2 interrupt, the event link source module is not affected. Rev. 1.00 Oct. 03, 2008 Page 86 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.3 4.3.1 Interrupt Sources External Interrupt sources There are nine external interrupts: NMI and IRQ7 to IRQ0. These external interrupts can be used to cause the device to exit from standby mode. (1) NMI Interrupt The nonmaskable interrupt request (NMI) is the highest-priority interrupt, and always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. (2) IRQ7 to IRQ0 Interrupts Interrupts IRQ7 to IRQ0 are generated by an input signal at pins IRQ7 to IRQ0. IRQ7 to IRQ0 interrupts have the following features: * Using ISCR, it is possible to select whether an interrupt on the IRQ7 to IRQ0 input pins is generated by a falling edge, rising edge, or both edges. * Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. * The interrupt priority level can be set with IPR. * The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 4.2. Rev. 1.00 Oct. 03, 2008 Page 87 of 962 REJ09B0465-0100 Section 4 Interrupt Controller IRQnE INCCRn IRQnSCB, IRQnSCA IRQnF Noise cancel circuit IRQn input Clear signal Edge detection circuit S R n = 7 to 0 Q IRQn interrupt request Figure 4.2 Block Diagram of IRQ7 to IRQ0 Interrupt 4.3.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR. * The DTC can be activated by a peripheral module interrupt request. * When the DTC is activated by an interrupt request, it is not affected by the interrupt control mode or CPU interrupt mask bit. Rev. 1.00 Oct. 03, 2008 Page 88 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.4 Interrupt Exception Handling Vector Table Table 4.3 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be changed by the IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Rev. 1.00 Oct. 03, 2008 Page 89 of 962 REJ09B0465-0100 Section 4 Interrupt Controller Table 4.3 Origin of Interrupt Source RES Pin WDT VLD Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source Reset 1. RES pin reset 2. WDT overflow 3. LVD reset 4. Software reset Vector 1 Number Vector Address* 0 H'0000 to H'0003 DTCER IPR Priority High CPU External pin CPU Reserved Trace Reserved NMI 1 to 4 5 6 7 H'0004 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'003F H'0040 to H'0043 TRAPA0 (TRAPA #0 8 instruction) TRAPA0 (TRAPA #1 9 instruction) TRAPA0 (TRAPA #2 10 instruction) TRAPA0 (TRAPA #3 11 instruction) FLASH Reserved IFMBSYA (access when flash memory busy) IFLRDY (flash memory ready) 12 to 15 16 17 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 IPRA7 and IPRA6 IPRA5 and IPRA4 IPRA3 and IPRA2 WDT LVD IWDT (WDT periodic 18 interrupt) ILVINT1 (low-voltage 19 detected interrupt 1) ILVINT2 (low-voltage 20 detected interrupt 2) CPG ICKSW (clock switching interrupt) 21 IPRA1 and IPRA0 Low Rev. 1.00 Oct. 03, 2008 Page 90 of 962 REJ09B0465-0100 Section 4 Interrupt Controller Origin of Interrupt Source External pin Interrupt Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Vector 1 Number Vector Address* 22 23 24 25 26 27 28 29 30 31 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'0064 to H'0067 H'0068 to H'006B H'006C to H'006F H'0070 to H'0073 H'0074 to H'0077 H'0078 to H'007B H'007C to H'007F DTCER DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB6 IPR IPRB7 and IPRB6 IPRB5 and IPRB4 IPRB3 and IPRB2 IPRB1 and IPRB0 IPRC7 and IPRC6 IPRC5 and IPRC4 IPRC3 and IPRC2 IPRC1 and IPRC0 IPRD7 and IPRD6 Priority High A/D converter unit 1 IADEND_1 (conversion end) IADCMP_1 (compare condition match) IADEND_2 (conversion end) IADCMP_2 (compare condition match) ISWDTEND (data transfer end) ELC1FP (ELSR12 event generation) ELC2FP (ELSR30 event generation) A/D converter unit 2*2 32 33 H'0080 to H'0083 H'0084 to H'0087 DTCEB5 DTCEB4 IPRD5 and IPRD4 DTC ELC 34 35 36 H'0088 to H'008B H'008C to H'008F H'0090 to H'0093 DTCEB3 DTCEB2 IPRD3 and IPRD2 IPRD1 and IPRD0 Low Rev. 1.00 Oct. 03, 2008 Page 91 of 962 REJ09B0465-0100 Section 4 Interrupt Controller Origin of Interrupt Source Interrupt Source SCI3_1 ERI SCI3 channel 1 1. Overrun error 2. Parity error 3. Framing error SCI3_1 RXI SCI3_1 TXI SCI3_1 TEI SCI3 SCI3_2 ERI channel 2 1. Overrun error 2. Parity error 3. Framing error SCI3_2 RXI SCI3_2 TXI SCI3_2 TEI SCI3 SCI3_3 ERI channel 3 1. Overrun error 2. Parity error 3. Framing error SCI3_3 RXI SCI3_3 TXI SCI3_3 TEI Reserved NAKI STPI 2. Clock synchronous mode Overrun 3. SSU mode Overrun (OEI) Conflict (CEI) RXI TXI TEI IIC2/SSU 1. IIC-BUS mode Vector 1 Number Vector Address* 37 H'0094 to H'0097 DTCER IPR Priority IPRE7 and High IPRE6 38 39 40 41 H'0098 to H'009B H'009C to H'009F H'00A0 to H'00A3 H'00A4 to H'00A7 DTCEB1 DTCEB0 IPRE5 and IPRE4 42 43 44 45 H'00A8 to H'00AB H'00AC to H'00AF H'00B0 to H'00B3 H'00B4 to H'00B7 DTCEC7 DTCEC6 IPRE3 and IPRE2 46 47 48 H'00B8 to H'00BB H'00BC to H'00BF H'00C0 to H'00C3 DTCEC5 DTCEC4 IPRF3 and IPRF2 49 to 58 H'00C4 to H'00EB 59 H'00EC to H'00EF 60 61 62 H'00F0 to H'00F3 H'00F4 to H'00F7 H'00F8 to H'00FB DTCED7 DTCED6 Low Rev. 1.00 Oct. 03, 2008 Page 92 of 962 REJ09B0465-0100 Section 4 Interrupt Controller Origin of Interrupt Source Timer RA/ HW-LIN Interrupt Source Reserved 1. Timer RA ITAUD 2. HW-LIN Bus conflict detection (BCDCT) Sync Break detection (SBDCT) Sync Field measurement end (SFDCT) Vector 1 Number Vector Address* DTCER 63 to 68 H'00FC to H'0113 69 H'0114 to H'0117 IPR IPRG5 and IPRG4 Priority High Timer RB ITBUD 70 71 H'0118 to H'011B H'011C to H'011F DTCED3 IPRG3 and IPRG2 IPRG1 and IPRG0 Timer RC*3 ITCMA (input capture A/compare match A) ITCMB (input capture B/compare match B) ITCMC (input capture C/compare match C) ITCMD (input capture D/compare match D) ITCOV counter overflow Timer RD unit 0 channel 0 ITDMA0_0 (input capture A/compare match A) ITDMB0_0 (input capture B/compare match B) 72 H'0120 to H'0123 DTCED2 73 H'0124 to H'0127 DTCED1 74 H'0128 to H'012B DTCED0 75 76 H'012C to H'012F H'0130 to H'0133 DTCEE7 IPRH7 and IPRH6 77 H'0134 to H'0137 DTCEE6 Low Rev. 1.00 Oct. 03, 2008 Page 93 of 962 REJ09B0465-0100 Section 4 Interrupt Controller Origin of Interrupt Source Timer RD unit 0 channel 0 Interrupt Source ITDMC0_0 (input capture C/compare match C) ITCMD0_0 (input capture D/compare match D) ITDOV0_0 overflow Vector Number Vector Address*1 DTCER 78 H'0138 to H'013B DTCEE5 IPR Priority IPRH7 and High IPRH6 79 H'013C to H'013F DTCEE4 80 H'0140 to H'0143 H'0144 to H'0147 H'0148 to H'014B DTCEE3 IPRH5 and IPRH4 ITDUD0_0 underflow 81 Timer RD unit 0 channel 1 ITDMA0_1 (input capture A/compare match A) ITDMB0_1 (input capture B/compare match B) ITDMC0_1 (input capture C/compare match C) ITCMD0_1 (input capture D/compare match D) ITDOV0_1 overflow Timer RD ITDMA1_2 (input unit 1 capture A/compare 4 channel 2* match A) ITDMB1_2 (input capture B/compare match B) ITDMC1_2 (input capture C/compare match C) ITCMD1_2 (input capture D/compare match D) ITDOV1_2 overflow 82 83 H'014C to H'014F DTCEE2 84 H'0150 to H'0153 DTCEE1 85 H'0154 to H'0157 DTCEE0 86 87 H'0158 to H'015B H'015C to H'015F DTCEF7 IPRH3 and IPRH2 88 H'0160 to H'0163 DTCEF6 89 H'0164 to H'0167 DTCEF5 90 H'0168 to H'016B DTCEF4 91 H'016C to H'016F H'0170 to H'0173 Low ITDUD1_2 underflow 92 Rev. 1.00 Oct. 03, 2008 Page 94 of 962 REJ09B0465-0100 Section 4 Interrupt Controller Origin of Interrupt Source Interrupt Source Vector 1 Number Vector Address* DTCER 93 H'0174 to H'0177 DTCEE3 IPR Priority Timer RD ITDMA1_3 (input unit 1 capture A/compare channel 3*3 match A) ITDMB1_3 (input capture B/compare match B) ITDMC1_3 (input capture C/compare match C) ITCMD1_3 (input capture D/compare match D) ITDOV1_3 overflow Timer RE Reserved Second interrupt Minute interrupt Hour interrupt Day interrupt Week interrupt Compare match Timer RG Reserved ITGMA (input capture A/compare match A) ITGMB (input capture B/compare match B) ITGOV ITGUD Notes: 1. 2. 3. 4. IPRH1 and High IPRH0 94 H'0178 to H'017B DTCEE2 95 H'017C to H'017F DTCEE1 96 H'0180 to H'0183 DTCEE0 97 98, 99 100 101 102 103 104 105 106 to 108 109 H'0184 to H'0187 H'0188 to H'018F H'0190 to H'0193 H'0194 to H'0197 DTCEG4 DTCEG3 IPRI7 and IPRI6 H'0198 to H'019B DTCEG2 H'019C to H'019F DTCEG1 H'01A0 to H'01A3 DTCEG0 H'01A4 to H'01A7 H'01A8 to H'01B3 H'01B4 to H'01B7 DTCEH3 IPRI3 and IPRI2 110 H'01B8 to H'01BB DTCEH2 111 112 H'01BC to H'01BF H'01C0 to H'01C3 Low Lower 16 bits of the vector address when VOFR = H'0000 Provided for the H8S/20223 group only. This area is reserved for the other groups. Provided for the H8S/20103 group only. This area is reserved for the other groups. Not provided for the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 95 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.5 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 4.4 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 4.4 Interrupt Control Modes Priority Setting Registers Default Interrupt Mask Bits I Interrupt Control Mode 0 Description The priorities of interrupt sources are fixed at the default settings. Interrupt sources except for NMI is masked by the I bit. 2 IPR I1 and I0 Four priority levels except for NMI can be set with IPR. Four-level interrupt mask control is performed by bits I1 and I0. 4.5.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit in CCR of the CPU. Figure 4.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared, an interrupt request is accepted. 3. When interrupt requests are sent to the interrupt controller, the highest-ranked interrupt request according to the priority system is accepted, and other interrupt requests are retained. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The I bit in CCR is set to 1. This masks all interrupts except NMI. 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the start address in the vector table. Rev. 1.00 Oct. 03, 2008 Page 96 of 962 REJ09B0465-0100 Section 4 Interrupt Controller Program execution status Interrupt generated Yes Yes No NMI No Yes IFMBSYA* No No Retained I=0 Yes No IRQ0 Yes No IRQ1 Yes ITGUD Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Note: * Access interrupt when flash memory busy. Figure 4.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 1.00 Oct. 03, 2008 Page 97 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.5.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is executed in four levels for interrupt requests except NMI by comparing the EXR interrupt mask level (I1 and I0 bits*) in the CPU and the IPR setting. Figure 4.4 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If the same priority are generated at the same time, the interrupt request is selected according to the default priority system shown in table 4.3. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'3. 7. The CPU generates a vector address for the accepted interrupt request and starts execution of the interrupt handling routine at the address indicated by the contents of the start address in the vector table. Note: * The I2 bit does not affect the mask control. Rev. 1.00 Oct. 03, 2008 Page 98 of 962 REJ09B0465-0100 Section 4 Interrupt Controller Program execution status Interrupt generated Yes Yes NMI No Yes IFMBSYA* No No No Level 3 interrupt Yes Mask level 2 or below Yes Level 2 interrupt No Yes No Level 1 interrupt Mask level 1 or below Yes Mask level 0 Yes No Yes No No Save PC, CCR, and EXR Retained Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Note: * Access interrupt when flash memory busy. Figure 4.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev. 1.00 Oct. 03, 2008 Page 99 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.5.3 Interrupt Exception Handling Sequence Figure 4.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0, the program area, and stack area are in on-chip memory. Rev. 1.00 Oct. 03, 2008 Page 100 of 962 REJ09B0465-0100 Interrupt acceptance Internal operation Stack Vector fetch Interrupt level determination Instruction Wait for end of instruction prefetch Interrupt handling Internal routine instruction operation prefetch Interrupt request signal Internal address bus (1) (3) (5) (7) (9) (11) (13) Internal read signal Internal write signal (2) (4) (6) (8) (10) (12) (14) Figure 4.5 Interrupt Exception Handling (6) (8) (9) (11) (10) (12) (13) (14) Internal data bus Section 4 Interrupt Controller Rev. 1.00 Oct. 03, 2008 Page 101 of 962 (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 Saved PC and saved CCR Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine REJ09B0465-0100 Section 4 Interrupt Controller 4.5.4 Interrupt Response Time Table 4.5 shows interrupt response time, the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 4.5 No. 1 2 3 4 5 6 Interrupt Response Times Interrupt Control Mode 0 3 1 to 21 2 2 2 4 Execution Status Interrupt priority determination*1 Number of wait states until executing 2 instruction ends* PC, CCR, EXR stack Vector fetch Instruction fetch*3 Internal processing* Interrupt Control Mode 2 3 2 12 to 32 13 to 33 Total (using on-chip memory) Notes: 1. 2. 3. 4. Two states in case of internal interrupt Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch Internal processing after interrupt acceptance and internal processing after vector fetch 4.5.5 DTC Activation by Interrupt The DTC can be activated by an interrupt request. In this case, the following options are available: 1. 2. 3. Interrupt request to CPU Activation request to DTC Both of the above For details of interrupt requests that can be used to activate the DTC, see table 4.3 and section 11, Data Transfer Controller (DTC). Rev. 1.00 Oct. 03, 2008 Page 102 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.6 4.6.1 Usage Notes Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask interrupt requests, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned is still enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed after completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling with the higher-priority interrupt is executed, and that lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 4.6 shows an example in which the IRQ0E bit in IER is cleared to 0. The above conflict does not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. IER write cycle by CPU IRQ0 exception handling Internal address bus IER address Internal write signal IRQ0E IRQ0 flag IRQ0 interrupt signal Figure 4.6 Conflict between Interrupt Generation and Disabling Rev. 1.00 Oct. 03, 2008 Page 103 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.6.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid after two states that execution of the instruction ends. 4.6.3 Time when Interrupts are Disabled There are time when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 4.6.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 Rev. 1.00 Oct. 03, 2008 Page 104 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.6.5 Changing PMR, ISCRH, ISCRL and INCCR When the PMR, ISCRH, ISCRL, and INCCR are modified to change an IRQ7 to IRQ0 interrupt function, the interrupt request flag bit may be set to 1 at an unintended time. To prevent this, the pin function should be changed when the interrupt request is disabled, then the interrupt request flag should be cleared to 0 after a specific interval time*. Figure 4.7 shows the procedure to modify PMR (port mode register), ISCRH, ISCRL, and INCCR and clear the interrupt request flags. Note: Two states + a minimum interval for input (tIH/tIL) Set I bit in CCR to 1. The interrupt is disabled. (Interrupts can also be disabled by setting IER.) Modify PMR, ISCRH, ISCRL, and INCCR. Wait for a specific period. After setting each register, the interrupt request flag should be cleared to 0 after waiting for a specific period. Clear interrupt request flag to 0. Clear I bit in CCR to 0. The Interrupt is enabled. Figure 4.7 Procedure to Modify PMR, ISCRH, ISCRL, and INCCR and Clear Interrupt Request Flag 4.6.6 IRQ Status Register (ISR) Depending on the pin state after a reset, IRQnF may be set to 1. Therefore, always read ISR and clear it to 0 after resets. Rev. 1.00 Oct. 03, 2008 Page 105 of 962 REJ09B0465-0100 Section 4 Interrupt Controller 4.6.7 NMI Pin The NMI pin is also used to set up entry to boot mode on exit from the reset state. In using the NMI pin, note that the low-level should not be being applied to the NMI pins on exit from the reset state (including power-on reset). In general, it is recommended that the connection of a pullup resistor to the NMI pin. Rev. 1.00 Oct. 03, 2008 Page 106 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator Section 5 Clock Pulse Generator The clock pulse generator is comprised of a high-speed on-chip oscillator (OCO), a 1/2 divider for the high-speed OCO, the main oscillator, a duty correction circuit, a low-speed, OCO, a suboscillator, a clock selection circuit, a system clock divider, a PSC divider for peripheral modules, and a s divider for the bus master and memory. Table 5.1 lists clock source symbols and their meanings used in this manual. Table 5.1 Symbol 40 hoco loco osc sub high low base s Clock Source Symbols Description High-speed OCO output High-speed OCO frequency/2 Low-speed OCO output Main oscillator output clock Sub-oscillator output clock High-speed clock (hoco or osc) Low-speed clock (loco or sub) System base clock System operation clock Bus master operation clock Rev. 1.00 Oct. 03, 2008 Page 107 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.1 Overview * Choice of four clock sources: loco, sub, hoco and osc * Choice of two frequencies of the high-speed OCO by the user software: 40 MHz and 32 MHz The signal generated by dividing the above clock by 2 can be used as a base and the above clock can be used as the clock source for timer RA, timer RC, timer RD, and timer RG. * Trimmable high-speed OCO oscillation frequencies Although the high-speed OCO is trimmed to 40 MHz in its initial state, it can also be trimmed to accommodate specific user operation conditions. * Main oscillation backup function By detecting a osc stop, it is possible to automatically switch the system clock to either hoco or low. * Clock switching interrupt function When the system clock is switched from osc to hoco or loco, a CPU interrupt can be generated if enabled. Figure 5.1 shows a block diagram of the clock pulse generation circuit. To timers RA, RC, RD, and RG Highspeed OCO 40 hoco 1/2 divider Highspeed clock select circuit /2 high base base/2 base/4 High-speed/ low-speed clock select circuit Lowspeed clock select circuit low base System clock divider base/8 base/16 base/32 base/64 base/128 s divider PSC divider /4 . . . /8192 Peripheral module OSC1 OSC2 Main clock oscillator Duty correction circuit osc /2 /4 /8 /16 s CPU DTC internal memory Lowspeed OCO Subclock oscillator loco X1 X2 Noise canceller sub Clock select circuit /32 To WDT To WDT, timer RA, and timer RE Clock pulse generator Figure 5.1 Block Diagram of Clock Pulse Generation Circuit Rev. 1.00 Oct. 03, 2008 Page 108 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator The system base clock (base) is the basic clock on which the CPU and on-chip peripheral modules operate. base can be divided by a value from 1 to 128 in the system clock divider, and the divided clock is supplied as the system clock . The system clock is divided by a value from 2 to 8192 in the PSC divider, and the divided clock can be supplied to on-chip peripheral modules. The system clock is also divided by a value from 1 to 32 in the s divider, and the divided clock can be supplied to the bus master and memory. After release from a reset, base is switched to the low-speed OCO. Rev. 1.00 Oct. 03, 2008 Page 109 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.2 * * * * * * * * * * * * Register Descriptions Backup control register (BAKCR) System clock control register (SYSCCR) Power-down control register 1 (LPCR1) Power-down control register 2 (LPCR2) Power-down control register 3 (LPCR3) OSC oscillation settling control status register (OSCCSR) High-speed OCO control register (HOCR) High-speed OCO trimming data protect register (HOTRMDPR) High-speed OCO trimming data register 1 (HOTRMDR1) High-speed OCO trimming data register 2 (HOTRMDR2) High-speed OCO trimming data register 3 (HOTRMDR3) High-speed OCO trimming data register 4 (HOTRMDR4) Rev. 1.00 Oct. 03, 2008 Page 110 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.2.1 Backup Control Register (BACKR) Address: H'FF06D4 Bit: b7 WI b6 WE 0 b5 OSCBAKE 0 b4 BAKCKSEL 0 b3 CKSWIE 0 b2 CKSWIF 0 b1 OSCHLT 0 b0 Value after reset: 1 0 Bit 7 6 Symbol WI WE Bit Name Write inhibit Write enable Description 0: Writing is permitted. 1: Writing is inhibited. 0: Writing is disabled. 1: Writing is enabled. [Setting condition] When 0 is written to WI and 1 is written to WE at the same time. [Clearing condition] When 0 is written to WI and WE at the same time. R/W W R/W 5 4 OSCBAKE External clock backup enable 0: External clock backup is disabled. 1: External clock backup is enabled. R/W R/W BAKCKSEL Backup 0: low destination clock 1: hoco source select CKSWIE CKSWIF Clock switching 0: Interrupt requests are disabled. interrupt enable 1: Interrupt requests are enabled. Clock switching 0: A clock switching interrupt request has not been interrupt flag generated. 1: A clock switching interrupt request has been generated. [Setting condition] When the system clock for the LSI is switched from osc to hoco or low while OSCBAKE is 1. [Clearing condition] When 1 is read from the bit and then 0 is written to the same bit. 3 2 R/W R/W Rev. 1.00 Oct. 03, 2008 Page 111 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator Bit 1 Symbol OSCHLT Bit Name Description R/W R Main oscillator 0: The external main oscillator is oscillating. stop detect flag 1: The external main oscillator is stopped. [Setting condition] When the external main oscillator is stopped while OSCBAKE is 1. 0 Note: Reserved This bit is read as 0. The write value should be 0. A MOV instruction should be used to write to this register. * WI bit (write inhibit) This register can be written to only when this bit is 0. This bit is always read as 1. * WE bit (write enable) Bits 5 to 2 in this register can be written to when this bit is 1. * OSCBAKE bit (external clock backup enable) The main oscillator stop detect circuit is enabled when this bit is 1. When this LSI operates at the external main oscillator clock, the backup function is enabled. By detecting a osc stop, the system clock is automatically switched to either hoco or low. * CKSWIE bit (clock switching interrupt enable) The main clock switching interrupt requests are enabled when this bit is 1. * CKSWIF bit (clock switching interrupt enable) This is a clock switching interrupt request flag. * OSCHLT bit (main oscillator stop detect flag) When the OSCBAKE bit is 1, this bit indicates the results of external oscillator stop detection. This bit, however, simply indicates whether the oscillator is active or not; it does not indicate a stable oscillation. When OSCBAKE is 0, this bit is always read as 0. An oscillator stop is detected when the external oscillator is between 0 to 2 MHz. Rev. 1.00 Oct. 03, 2008 Page 112 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.2.2 System Clock Control Register (SYSCCR) Address: H'FF06D0 Bit: b7 WI b6 WE 0 b5 PHIHSEL 0 b4 PHILSEL 0 b3 b2 b1 SUBNC[1:0] b0 Value after reset: 1 0 0 0 0 Bit 7 6 Symbol WI WE Bit Name Write inhibit Write enable Description 0: Writing is permitted. 1: Writing is inhibited. 0: Writing is disabled. 1: Writing is enabled. [Setting condition] When 0 is written to WI and 1 is written to WE at the same time. [Clearing condition] When 0 is written to WI and WE at the same time. R/W W R/W 5 PHIHSEL high clock source select 0: hoco 1: osc [Setting condition] When 1 is written to this bit while CKSWIF in BAKCR is 0. [Clearing conditions] * * When 0 is written to this bit. When the main oscillator stop state is detected while the system clock selects osc and OSCBAKE and BAKCKSEL in BAKCR are 1, respectively. 0: loco 1: sub This bit is read as 0. The write value should be 0. R/W 4 3 PHILSEL low clock source select Reserved R/W Rev. 1.00 Oct. 03, 2008 Page 113 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator Bit 2, 1 Symbol SUBNC [1:0]* Bit Name sub noise canceler sampling function setting Reserved Description 00: The sampling circuit is disabled. 01: Sampling is performed at base/4. 10: Sampling is performed at base/16. 11: Setting prohibited This bit is read as 0. The write value should be 0. R/W R/W 0 Note: * A MOV instruction should be used to write to this register. When the operation clock of the CPU selects low, the sampling circuit is disabled regardless of this bit setting. * WI bit (write inhibit) This register can be written to only when this bit is 0. This bit is always read as 1. * WE bit (write enable) Bits 5, 4, 2, and 1 in this register can be written to when this bit is 1. * PHIHSEL bit (high clock source select) This bit is 1 when 0 is written to the WI bit in BAKCR at CKSWIF = 0 and WE = 1 and then 1 is written to this bit. If 0 is written to WI and this bit at WE = 1, this bit remains 0. If the main oscillator stop is detected while the system clock selects osc and OSCBAKE and BAKCKSEL in BAKCR are 1, respectively, this bit is 0. * PHILSEL bit (low clock source select) When 0 is written to WI and 1 is written to this bit at WE = 1, this bit is 1. When 0 is written to WI and this bit at WE = 1, this bit is 0. * SUBNC1 and SUBNC0 bits (sub noise canceler sampling function setting) Selects a sampling clock for the subclock oscillator noise canceler. The sampling circuit is disabled in standby mode, when base is stopped during clock switching, and when low has been selected as base, regardless of the setting of this bit. When timer RE is to be used in real-time clock mode, the sampling circuit should be enabled. Note: The frequency of the low-speed on-chip oscillator varies greatly according to the power supply voltage and operating temperature. In designing application systems, allow sufficient margins for frequency variation. Rev. 1.00 Oct. 03, 2008 Page 114 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.2.3 Power-Down Control Register 1 (LPCR1) Address: H'FF06D1 Bit: b7 WI b6 WE 0 b5 SSBY 0 b4 PSCSTP 1 b3 SLEEPRS 0 b2 STBYRS 0 b1 b0 PHIBSEL 0 Value after reset: 1 0 Bit 7 6 Symbol WI WE Bit Name Write inhibit Write enable Description 0: Writing is permitted. 1: Writing is inhibited. 0: Writing is disabled. 1: Writing is enabled. [Setting condition] When 0 is written to WI and 1 is written to WE at the same time. [Clearing condition] When 0 is written to WI and WE at the same time. R/W W R/W 5 4 3 SSBY PSCSTP Software standby 0: A transition is made to sleep mode. 1: A transition is made to standby mode. PSC divider stop 0: PSC divider is operating. 1: PSC divider is stopped*. R/W R/W R/W SLEEPRS source select for 0: low recovery from 1: high sleep mode STBYRS source select for 0: low recovery from 1: high standby mode Reserved 2 R/W 1 This bit is read as 0. The write value should be 0. Rev. 1.00 Oct. 03, 2008 Page 115 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator Bit 0 Symbol PHIBSEL Bit Name base clock source select Description 0: low 1: high [Setting conditions] * * * When 1 is written to this bit. When the system returns from sleep mode while SLEEPRS is 1. When the system returns from standby mode while STBYRS is 1. When 0 is written to this bit. When the main oscillator backup is generated while BAKCKSEL in BAKCR is 0. When the system returns from sleep mode while SLEEPRS is 0. When the system returns from standby mode while STBYRS is 0. R/W R/W [Clearing conditions] * * * * Note: A MOV instruction should be used to write to this register. * Operations of the peripheral modules using the clock are not affected by this bit setting. * WI bit (write inhibit) This register can be written to only when this bit is 0. This bit is always read as 1. * WE bit (write enable) Bits 5 to 2 in this register can be written to when this bit is 1. * SSBY bit (software standby) Selects a mode to be entered after the SLEEP instruction is executed. * PSCSTP bit (PSC divider stop) Stops the PSC divider circuit when this bit is 1. Peripheral modules using /2 to /8192 clocks stop operation. (The register values are retained.) * SLEEPRS bit ( source select for recovery from sleep mode) Selects a clock source to be used when a transition is made from sleep mode to active mode. Rev. 1.00 Oct. 03, 2008 Page 116 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator * STBYRS bit ( source select for recovery from standby mode) Selects a clock source to be used when a transition is made from standby mode to active mode. * PHIBSEL bit (base clock source select) Selects a clock source for the base to be used in active mode or sleep mode. 5.2.4 Power-Down Control Register 2 (LPCR2) Address: H'FF06D2 Bit: b7 WI Value after reset: 1 b6 WE 0 b5 b4 b3 b2 b1 PHI[2:0] b0 0 0 0 0 0 0 Bit 7 6 Symbol WI WE Bit Name Write inhibit Write enable Description 0: Writing is permitted. 1: Writing is inhibited. 0: Writing is disabled. 1: Writing is enabled. [Setting condition] When 0 is written to WI and 1 is written to WE at the same time. [Clearing condition] When 0 is written to WI and WE at the same time. R/W W R/W 5 to 3 2 to 0 PHI[2:0] Reserved These bits are read as 0. The write value should be 0. R/W System clock 000: base select 001: base/2 010: base/4 011: base/8 100: base/16 101: base/32 110: base/64 111: base/128 Note: A MOV instruction should be used to write to this register. Rev. 1.00 Oct. 03, 2008 Page 117 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator * WI (write inhibit) This register can be written to only when this bit is 0. This bit is always read as 1. * WE bit (write enable) Bits 2 to 0 in this register can be written to when this bit is 1. * PHI2 bit to PHI0 bit (system clock select) Selects a clock source for the system clock to be used in active mode or sleep mode. The clock is changed immediately after this bit is set. 5.2.5 Power-Down Control Register 3 (LPCR3) Address: H'FF06D3 Bit: b7 WI Value after reset: 1 b6 WE 0 b5 STBYINT 0 b4 SLEEPINT 0 b3 b2 b1 PHIS[2:0] b0 0 0 0 0 Bit 7 6 Symbol WI WE Bit Name Write inhibit Write enable Description 0: Writing is permitted. 1: Writing is inhibited. 0: Writing is disabled. 1: Writing is enabled. [Setting condition] When 0 is written to WI and 1 is written to WE at the same time. [Clearing condition] When 0 is written to WI and WE at the same time. R/W W R/W 5 STBYINT Standby mode 0: No interrupt has occurred in standby mode. interrupt 1: An interrupt has occurred in standby mode. generation flag [Setting condition] When an interrupt is generated in standby mode. [Clearing condition] When an interrupt is generated in states other than standby mode. R/W Rev. 1.00 Oct. 03, 2008 Page 118 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator Bit 4 Symbol SLEEPINT Bit Name Description R/W R/W Sleep mode 0: No interrupt has occurred in sleep mode. interrupt 1: An interrupt has occurred in sleep mode. generation flag [Setting condition] When an interrupt is generated in sleep mode. [Clearing condition] When an interrupt is generated in states other than sleep mode. 3 2 to 0 PHIS[2:0] Reserved This bit is read as 0. The write value should be 0. R/W Bus master 000: operation clock 001: /2 s select 010: /4 011: /8 100: /16 101: /32 110: Setting prohibited 111: Setting prohibited Note: A MOV instruction should be used to write to this register. * WI bit (write inhibit) This register can be written to only when this bit is 0. This bit is always read as 1. * WE bit (write enable) Bits 2 to 0 in this register can be written to when this bit is 1. * STBYINT bit (standby mode interrupt generation flag) This bit is set to 1 when an interrupt is generated in standby mode. This bit is cleared to 0 when an interrupt is generated in the other state. * SLEEPINT bit (sleep mode interrupt generation flag) This bit is set to 1 when an interrupt is generated in sleep mode. This bit is cleared to 0 when an interrupt is generated in the other state. * PHIS2 bit to PHIS0 bit (bus master operation clock s select) Selects a clock source for the bus master operation clock s to be used in active mode or sleep mode. The clock is changed immediately after this bit is set. Rev. 1.00 Oct. 03, 2008 Page 119 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.2.6 OSC Oscillation Settling Control Status Register (OSCCSR) Address: H'FF06D5 Bit: b7 b6 b5 b4 b3 b2 STS[3:0] b1 b0 Value after reset: 0 0 0 0 1 1 1 1 Bit 7 6 to 4 3 to 0 Symbol STS[3:0] Bit Name Reserved Reserved Description This bit is read as unknown value. The write value should be 0. These bits are read as 0. The write value should be 0. R/W R/W osc oscillation Specifies the number of wait states for a stable osc settling time oscillation. For the relationship between assigned select 3 to 0 values and the numbers of wait states, see table 5.2. * STS3 bit to STS0 bit (osc oscillation settling time select 3 to 0) Specifies the number of wait states for a stable osc oscillation. The count clock is osc. Table 5.2 shows the relationship between assigned values and the numbers of wait states. If the system base clock is osc when the system returns from the standby mode, or when the system base clock is switched to osc, set these bits so that wait time will be 6.5 ms or greater depending on the frequency of the oscillator. If the osc is already oscillating stably or the osc is an external clock input, wait time can be selected from 16 states (STS[3:0]=B'0000). Rev. 1.00 Oct. 03, 2008 Page 120 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator Table 5.2 Bit STS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Relationship between Operation Frequency and Number of Wait States Number of Wait States 16 states 32 states 64 states 128 states 256 states 512 states 1024 states 2048 states 4096 states 8192 states 16384 states 32768 states 65536 states Operation Frequency 20 MHz 16 MHz 10 MHz 8 MHz 0.00 0.00 0.00 0.01 0.01 0.03 0.05 0.10 0.20 0.41 0.82 1.64 3.28 0.00 0.00 0.00 0.01 0.02 0.03 0.06 0.13 0.26 0.51 1.02 2.05 4.10 8.19 16.38 0.00 0.00 0.01 0.01 0.03 0.05 0.10 0.20 0.41 0.82 1.64 3.28 6.55 13.11 26.21 0.00 0.00 0.01 0.02 0.03 0.06 0.13 0.26 0.51 1.02 2.05 4.10 8.19 16.38 32.77 4 MHz 0.00 0.01 0.02 0.03 0.06 0.13 0.26 0.51 1.02 2.05 4.10 8.19 16.38 32.77 65.54 STS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 STS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 STS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 131072 states 6.55 262144 states 13.11 Reserved 5.2.7 High-Speed OCO Control Register (HOCR) Address: H'FF062A Bit: b7 HOCOE b6 b5 b4 b3 b2 b1 b0 Value after reset: 0 0 0 0 0 0 0 0 Bit 7 6 to 0 Symbol HOCOE Bit Name High-speed OCO enable Reserved Description 0: The high-speed OCO is not used (standby state). 1: The high-speed OCO is used. These bits are read as 0. The write value should be 0. R/W R/W * HOCOE bit (high-speed OCO enable) Controls operation of the high-speed OCO. Rev. 1.00 Oct. 03, 2008 Page 121 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.2.8 High-Speed OCO Trimming Data Protect Register (HOTRMDPR) Address: H'FF062B Bit: b7 WI b6 WE 0 b5 LOCKDW 0 b4 TRMDRWE 0 b3 b2 b1 b0 Value after reset: 1 0 0 0 0 Bit 7 6 Symbol WI WE Bit Name Write inhibit Description 0: Writing is permitted. 1: Writing is inhibited. R/W W R/W Write enable 0: Writing is disabled. 1: Writing is enabled. [Setting condition] When 0 is written to WI and 1 is written to WE at the same time. [Clearing condition] When 0 is written to WI and WE at the same time. 5 LOCKDW Trimming 0: HOTRMDR1 can be written to. data register 1: HOTRMDR1 cannot be written to. lock down [Setting condition] When 0 is written to WI and 1 is written to LOCKDW while WE is 1. [Clearing condition] Reset. R/W 4 TRMDRWE Trimming 0: Writing to HOTRMDR1 is prohibited. data register 1: Writing to HOTRMDR1 is permitted. write enable [Setting condition] When 0 is written to WI and 1 is written to TRMDRWE while WE is 1. [Clearing condition] When 0 is written to WI and TRMDRWE while WE is 1. R/W 3 to 0 Note: Reserved These bits are read as 0. The write value should be 0. A MOV instruction should be used to write to this register. Rev. 1.00 Oct. 03, 2008 Page 122 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator * WI bit (write inhibit) This register can be written to only when this bit is 0. This bit is always read as 1. * WE bit (write enable) Bits 5 and 4 in this register can be written to when this bit is 1. * LOCKDW bit (trimming data register lock down) HOTRMDR1 cannot be written to when this bit is 1. Once this bit is set to 1, writing to HOTRMDR1 is prohibited, even if 0 is written to this bit, until a reset is applied. * TRMDRWE bit (trimming data register write enable) Writing to HOTRMDR1 is enabled when LOCKDW is 0 and TRMDRWE is 1. 5.2.9 High-Speed OCO Trimming Data Register 1 (HOTRMDR1) Address: H'FF062C Bit: b7 b6 b5 b4 b3 b2 b1 b0 HOTRMDR1[7:0] Value after reset: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit 7 to 0 Symbol HOTRMDR1 [7:0] Bit Name Trimming data 1 Description High-speed OCO frequency trimming data (40 MHz) R/W R/W * HOTRMDR17 bit to HOTRMDR10 bit (trimming data 17 to 10) Immediately after a reset, trimming data that produces a 40-MHz oscillation is loaded into the LSI, and the data is written to this register. Reading these bits yields an undefined value. If this register is to be used for timing a 32-MHz oscillation, before setting the HOCOE bit in HOCR to 1, write the value stored in HOTRMDR3 into HOTRMDR1. By rewriting bits 7 to 0 of this register, the high-speed OCO can be trimmed to the desired frequency. When these bits are rewritten, the oscillator frequency of the high-speed OCO is modified after the oscillation has become stable. The frequency changes as follows: B'00000000 (minimum frequency) B'11111111 (maximum frequency) Rev. 1.00 Oct. 03, 2008 Page 123 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.2.10 High-Speed OCO Trimming Data Register 2 (HOTRMDR2) Address: H'FF062D Bit: b7 b6 b5 b4 b3 b2 b1 b0 HOTRMDR2[7:0] Value after reset: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit 7 to 0 Note: Symbol HOTRMDR2 [7:0] Bit Name Trimming data 2 Description High-speed OCO frequency trimming data (40 MHz) R/W R/W Bit 7 should not be modified when the frequency is trimmed to a desired frequency. * HOTRMDR27 bit to HOTRMDR20 bit (trimming data 27 to 20) Immediately after a reset, trimming data that produces a 40-MHz oscillation is loaded into the LSI, and the data is written to this register. Reading these bits yields an undefined value. If this register is to be used for timing a 32-MHz oscillation, before setting the HOCOE bit in HOCR to 1, write the value stored in HOTRMDR4 into HOTRMDR2. 5.2.11 High-Speed OCO Trimming Data Register 3 (HOTRMDR3) Address: H'FF062E Bit: b7 b6 b5 b4 b3 b2 b1 b0 HOTRMDR3[7:0] Value after reset: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit 7 to 0 Note: Symbol Bit Name Description High-speed OCO frequency trimming data (32 MHz) R/W R/W HOTRMDR3 Trimming [7:0] data 3 Bit 7 should not be modified when the frequency is trimmed to a desired frequency. * HOTRMDR37 bit to HOTRMDR30 bit (trimming data 37 to 30) Immediately after a reset, trimming data that produces a 32-MHz oscillation is loaded into the LSI, and the data is written to this register. Reading these bits yields an undefined value. If 32-MHz oscillation is required then before setting the HOCOE bit in HOCR to 1, copy the value stored in this register to HOTRMDR1. Rev. 1.00 Oct. 03, 2008 Page 124 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.2.12 High-Speed OCO Trimming Data Register 4 (HOTRMDR4) Address: H'FF062F Bit: b7 b6 b5 b4 b3 b2 b1 b0 HOTRMDR4[7:0] Value after reset: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit 7 to 0 Note: Symbol HOTRMDR4 [7:0] Bit Name Trimming data 4 Description R/W High-speed OCO frequency trimming data (32 MHz) R/W Bit 7 should not be modified when the frequency is trimmed to a desired frequency. * HOTRMDR47 bit to HOTRMDR40 bit (trimming data 47 to 40) Immediately after a reset, trimming data that produces a 32-MHz oscillation is loaded into the LSI, and the data is written to this register. Reading these bits yields an undefined value. If 32-MHz oscillation is required, then before setting the HOCOE bit in HOCR to 1, copy the value stored in this register to HOTRMDR2. Rev. 1.00 Oct. 03, 2008 Page 125 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.3 Operation of Selection of System Base Clock After a reset, this LSI enters active mode operating in low-speed clocks. The user, by means of software, can change the system base clock from a low-speed OCO clock to a high-speed OCO clock, the main oscillator clock, or a sub-oscillator clock. Figure 5.2 shows a transition diagram between system base clock states. Table 5.3 shows conditions under which clock sources can be switched. Reset state Reset released Operation at low-speed OCO clock PHIBSEL=0 PHIHSEL=X PHILSEL=0 Operation at high-speed OCO clock PHIBSEL=1 PHIHSEL=0 PHILSEL=X Operation at sub-clock PHIBSEL=0 PHIHSEL=X PHILSEL=1 Operation at main oscillator clock PHIBSEL=1 PHIHSEL=1 PHILSEL=X The LSI operates on low. The LSI operates on high. [Legend] X: Don't care Figure 5.2 Transition Diagram between LSI System Base Clock States Rev. 1.00 Oct. 03, 2008 Page 126 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator Table 5.3 Bit PHIBSEL 0 0 1 1 01 10 01 10 01 10 01 10 Clock Source Switching PHIHSEL Don't care Don't care 01 10 0 0 0 0 1 1 1 1 PHILSEL 01 10 Don't care Don't care 0 0 1 1 0 0 1 1 Switching Operation loco sub sub loco hoco osc osc hoco loco hoco hoco loco sub hoco hoco sub hoco osc osc hoco sub osc osc sub Rev. 1.00 Oct. 03, 2008 Page 127 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator Table 5.4 shows the high-speed OCO, low-speed OCO, main oscillator, and sub-oscillator operation states in each operating mode (system state). Table 5.4 Clock Operation States in Each Operating Mode High-Speed System Clock OCO Sate Stopped Oscillating Depending on user setting*1 Depending on 1 user setting* Depending on user setting*1 Stopped hoco osc loco sub Standby mode None Main Oscillator State Stopped Depending on user setting*2 Depending on user setting*3 Depending on user setting*2 Depending on user setting*2 Stopped Low-Speed OCO State Oscillating Oscillating Oscillating Oscillating Oscillating Oscillating Sub-Oscillator State Oscillating* 4 System State Reset released loco Active mode, sleep mode Notes: 1. Can be set with the HOCOE bit in HOCR. 2. Can be set with the PMRJ[1:0] bits in PMRJ. 3. Backup operation is performed by selecting the oscillation stop with the PMRJ[1:0] bits in PMRJ when the backup function is enabled. 4. A crystal resonator should be connected when a sub-oscillator clock is used. To switch the system base clock to sub immediately after the power-on, oscillation settling time for the sub-oscillator should be ensured. Rev. 1.00 Oct. 03, 2008 Page 128 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.3.1 Switching System Base Clock to hoco Figure 5.3 shows a flowchart of the process in which the LSI automatically ensures oscillation settling time for the high-speed OCO and switches from loco to a high-speed OCO. Figure 5.4 shows a flowchart of the process in which a user ensures high-speed OCO settling time and switches from loco to a high-speed OCO. The LSI operates at the low-speed OCO clock. Start (Reset) [1] Setting PHIBSEL to 1 switches base from low to high. Set PHIBSEL in LPCR1 to 1. [1] [2] hoco is used for counting during oscillation setting time. The LSI stops operation until oscillation is stable. The LSI stops and waits for high-speed OCO oscillation settling time. [2] The LSI operates at the high-speed OCO clock. The LSI operates at high-speed OCO clock. Figure 5.3 Flowchart for Automatically Ensuring Oscillation Settling Time and Switching from loco to High-Speed OCO Rev. 1.00 Oct. 03, 2008 Page 129 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator The LSI operates at the low-speed OCO clock. [1]Setting HOCOE to 1 starts the high-speed OCO oscillation. [1] [2]At least T.B.D s of wait time should be ensured for a stable oscillation. [3]Setting PHIBSEL to 1 switches base from low to high. Start (Reset) Set HOCOE in HOCR to 1. Wait for the high-speed OCO settling time (T.B.D s or more). [2] Set PHIBSEL in LPCR1 to 1. [3] The LSI operates at the high-speed OCO clock. The LSI operates at the high-speed OCO clock. Figure 5.4 Flowchart for Ensuring Oscillation Settling Time by User and Switching from loco to High-Speed OCO Rev. 1.00 Oct. 03, 2008 Page 130 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.3.2 Switching System Base Clock to osc Figure 5.5 shows a flowchart of the process in which the system base clock is switched from loco to osc. The LSI operates at the low-speed OCO clock. Start (Reset) Set oscillation settling time with STS[3:0] in OSCCSR. [1] [1] Set at least 6.5 ms of oscillation settling time according to the oscillation frequency. [2] Set the PJ1 and PJ0 pins to oscillation pins. [3] Setting PHIBSEL to 1 switches high from hoco to osc. [4] Setting PHIBSEL to 1 switches base from low to high. [5] Counting is driven by osc during the oscillation settling time. LSI operation is stopped until oscillation is stable. Set PMRJ[1:0] in PMJR. [2] Set PHIHSEL in SYSCCR to 1. [3] Set PHIBSEL in LPCR1 to 1. [4] LSI operation is stopped over the stabilization period of the main oscillator. [5] LSI operation is driven by the main oscillator clock. LSI operation is driven by the main oscillator clock. Figure 5.5 Flowchart of Clock Switching from loco to osc Rev. 1.00 Oct. 03, 2008 Page 131 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.3.3 (1) Clock Change Timing Switching Division Ratio for the Same Clock Source Figure 5.6 shows a division ratio switching timing chart for the same clock source. base PHI[2:0] 000 (divided by 1) 010 (divided by 4) 001 (divided by 2) Figure 5.6 Timing of Division Ratio Switching for the Same Clock Source Rev. 1.00 Oct. 03, 2008 Page 132 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator (2) Switching System Base Clock Source Figures 5.7 and 5.8 show clock source switching timing charts for the system base clock. CLKA CLKB SELA SELB base Operation at CLKA Clock switching time Operation at CLKB Clock switching time Operation at CLKA [Legend] CLKA: Clock A CLKB: Clock B SELA: CLKA select signal SELB: CLKB select signal base: System base clock Note: Clock switching time is a period from the clock select signal change to the second high level of the destination clock. Figure 5.7 Timing of Clock Source Switching (When the switching destination clock source is active) Rev. 1.00 Oct. 03, 2008 Page 133 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator CLKA CLKB SELA SELB base Operation at CLKA Oscillation settling wait time Operation at CLKB [Legend] CLKA: Clock A CLKB: Clock B SELA: CLKA select signal SELB: CLKB select signal base: System base clock Note: The oscillation settling time differs according to the clock source. Figure 5.8 Timing of Clock Source Switching (When the switching destination clock source is stopped) Oscillation stabilization wait time varies with switching destination clock sources. If the destination clock is osc, wait time is specified by the STS[3:0] bit of the OSCCSR. For oscillation stabilization wait time values, see table 5.2. If the destination clock is hoco, wait time is automatically fixed to approximately TBD us. During oscillation stabilization wait time, the base stops; therefore, any module that operates with the base as a base, including the bus master, stops. The register retains the pre-switching value. Rev. 1.00 Oct. 03, 2008 Page 134 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.3.4 Backup Operation If the operating clock for the system is osc and the backup function is enabled, when the main oscillator detects an oscillation halt condition, the system clock automatically switches to either hoco or low, according to BAKCKSEL in BAKCR. The period from the stopping of the main oscillator to the time the system clock is operating from hoco or low will be clock halt detection time + oscillation stabilization wait time for the backup clock. Time to wait for oscillation stabilization is 0 ms if the target backup clock is already oscillating when stopping of the main oscillator is detected. To reduce power consumption, it is also possible to set the target backup clock to a stopped state when the backup function is enabled. In that case, the target backup clock is automatically activated when stopping of the main clock oscillator is detected. The system clock is then changed after a certain amount of oscillation settling time (approximately T.B.D. s in the case of hoco). This LSI circuit may malfunction during operation with the back-up function. Accordingly, usage with the watchdog timer is recommended. OSC OSCHLT BAKCLK base Operation at main oscillator clock OSC stops Clock switching time Operation at backup destination clock [Legend] OSC: Main oscillator clock OSCHLT: Main oscillator clock stop detection signal BAKCLK: Backup destination clock base: System base clock Figure 5.9 Timing of Backup Operation When Main Oscillator Stops at High Level (When the backup destination clock is active) Rev. 1.00 Oct. 03, 2008 Page 135 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator OSC OSCHLT BAKCLK base Operation at main oscillator clock OSC stops Clock switching time Operation at backup destination clock [Legend] OSC: Main oscillator clock OSCHLT: Main oscillator clock stop detection signal BAKCLK: Backup destination clock base: System base clock Figure 5.10 Timing of Backup Operation When Main Oscillator Stops at Low Level (When the backup destination clock is active) Rev. 1.00 Oct. 03, 2008 Page 136 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator OSC OSCHLT BAKCLK base Operation at main oscillator clock OSC stops. Oscillation settling time Clock switching time Operation at backup destination clock [Legend] OSC: Main oscillator clock OSCHLT: Main oscillator clock stop detection signal BAKCLK: Backup destination clock base: System base clock Figure 5.11 Timing of Backup Operation When Main Oscillator Stops at High Level (When the backup destination clock is stopped) Rev. 1.00 Oct. 03, 2008 Page 137 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator OSC OSCHLT BAKCLK base Operation at main oscillator clock OSC stops. Oscillation settling time Clock switching time Operation at backup destination clock [Legend] OSC: Main oscillator clock OSCHLT: Main oscillator clock stop detection signal BAKCLK: Backup destination clock base: System base clock Figure 5.12 Timing of Backup Operation When Main Oscillator Stops at Low Level (When the backup destination clock is stopped) Rev. 1.00 Oct. 03, 2008 Page 138 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.4 5.4.1 High-Speed On-Chip Oscillator Procedures for Switching to 32MHz After release from a reset, the high-speed OCO is trimmed so that it will oscillate at 40 MHz. Figure 5.13 shows a flowchart for the switching of the oscillation frequency of the high-speed OCO to 32 MHz. Frequencies should be changed when the high-speed OCO is at reset. Start Read HOTRMDR3. [1] Write the 32-MHz trimming value in HOTRMDR3 to HOTRMDR1. [2] Write 32-MHz trimming value in HOTRMDR4 to HOTRMDR2. [3] Set the HOCOE bit in HOCR to 1 to enable the high-speed OCO. [1] Write the HOTRMDR3 value to HOTRMDR1. Read HOTRMDR4. [2] Write the HOTRMDR4 value to HOTRMDR2. [3] Set HOCOE in HOCR to 1. End Figure 5.13 Flowchart for Switching High-Speed OCO Frequency to 32 MHz Rev. 1.00 Oct. 03, 2008 Page 139 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.4.2 Trimming of High-Speed OCO Users can trim the on-chip oscillator frequency, supplying the external reference pulses with the input capture function in the on-chip timer. An example of trimming flow using timer RC and a timing chart are shown in figures 5.14 and 5.15, respectively. Because HOTRMDR1 is initialized by a reset, when users have trimmed the oscillators, some operations after a reset are necessary, such as trimming it again or saving the trimming value in an external device for later reloading. Start Set timer RC GRA: Input capture GRC: GRA buffer Set bit7 to bit0 in HOTRMDR1 to 0. Supply reference pulse to P30/FTIOA. Capture 1 Capture 2 Modify HOTRMDR1*. Frequency calculation No Desired frequency? Yes End Note: Compare the measured frequency and desired frequency, and determine the HOTRMDR1 value, bit by bit, from the MSB. Figure 5.14 Example of Flow for Trimming High-Speed OCO Frequency Rev. 1.00 Oct. 03, 2008 Page 140 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 40 FTIOA input capture input tA (s) Timer RC TRCCNT M-1 M M+1 M+ GRA N M M+ GRC N Capture 1 M Capture 2 Figure 5.15 Timing Chart of Trimming of High-Speed OCO Frequency The high-speed OCO frequency is obtained by the expression below. Since the input-capture input is sampled at the rate of the high-speed OCO, the calculated result includes a sampling error of 1 clock cycle. Foco = (M + ) - M tA (MHz) Foco = High-speed OCO frequency tA = Cycle of base clock (us) M = Timer RC counter value Note: For the H8S/20203 and H8S/20223 groups, timer RD should be used instead of timer RC. Rev. 1.00 Oct. 03, 2008 Page 141 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.5 Main Clock Oscillator This LSI has two methods to supply external clock pulses into it: connecting a crystal or ceramic resonator, and an external clock. For setting the oscillation pins PJ0/OSC1 and PJ1/OSC2/CLKOUT to resonator pins or an external clock input pin, see section 10.10.1, Port Mode Register J (PMRJ). Figure 5.16 shows a block diagram of the Main clock oscillator. OSC2 STBY OSC1 [Legend] STBY: Standby mode Figure 5.16 Block Diagram of Main Clock Oscillator 5.5.1 Connecting Crystal Resonator Figure 5.17 shows an example of connecting a crystal resonator. An AT-cut parallel-resonance crystal resonator should be used. A damping resistor Rd should be added, if necessary. Since the resistor values vary depending on the resonator, use values recommended by the resonator manufacturer. C1 PJ0/OSC1 C2 PJ1/OSC2/CLKOUT Rd C1 = C2 = 10 to 22 pF Figure 5.17 Example of Connection to Crystal Resonator Rev. 1.00 Oct. 03, 2008 Page 142 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.5.2 Connecting Ceramic Resonator Figure 5.18 shows an example of connecting a ceramic resonator. A damping resistor Rd should be added, if necessary. Since the resistor values vary depending on the resonator, use values recommended by the resonator manufacturer. C1 PJ0/OSC1 C2 PJ1/OSC2/CLKOUT Rd C1 = C2 = 5 to 30 pF Figure 5.18 Example of Connection to Ceramic Resonator 5.5.3 External Clock Input Method To use the external clock, input the external clock on pin OSC1. Figure 5.19 shows an example of connection. The duty cycle of the external clock signal must be 45 to 55%. PJ0/OSC1 External clock input PJ1/OSC2/CLKOUT Open Figure 5.19 Example of External Clock Input Note: To input the external clock, set the PMRJ[1:0] bits to 01. Do not input the external clock while PMRJ[1:0] bits are set to 11. Rev. 1.00 Oct. 03, 2008 Page 143 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.6 Subclock Generator Figure 5.20 shows a block diagram of the subclock generator. X2 X1 Figure 5.20 Block Diagram of Subclock Generator 5.6.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.21. A damping resistor Rd should be added, if necessary. Since the resistor values vary depending on the resonator, use values recommended by the resonator manufacturer. C1 X1 C2 X2 Rd C1 = C2 = 15 pF (typ.) Figure 5.21 Typical Connection to 32.768-kHz Crystal Resonator 5.6.2 Pin Connection when not Using Subclock When the subclock is not used, connect pin X1 to VSS and leave pin X2 open, as shown in figure 5.22. X1 VSS X2 Open Figure 5.22 Pin Connection when not Using Subclock Rev. 1.00 Oct. 03, 2008 Page 144 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.7 Prescaler The prescaler is a 13-bit counter using the system clock () as its input clock. The outputs, which are divided clocks, are used as internal clocks by the on-chip peripheral modules. The prescaler is initialized to H'0000 and stops counting after a reset. It starts counting when the PSCSTP bit in LPCR1 is cleared. The prescaler counter cannot be accessed by the CPU. The outputs from the prescaler is shared by the on-chip peripheral modules. The division ratio can be set separately for each on-chip peripheral module. The clock input to the prescaler is a system clock with the division ratio specified by bits PHI2 to PHI0 in LPCR2. Rev. 1.00 Oct. 03, 2008 Page 145 of 962 REJ09B0465-0100 Section 5 Clock Pulse Generator 5.8 5.8.1 Usage Notes Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit parameters will differ depending on the resonator element, stray capacitance of the PCB, and other factors. Suitable values should be determined in consultation with the resonator element manufacturer. Design the circuit so that the resonator element never receives voltages exceeding its maximum rating. 5.8.2 Notes on Board Design When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to pins OSC1 and OSC2. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5.23). Prohibited Signal A Signal B C1 PJ0/OSC1 C2 PJ1/OSC2/CLKOUT Figure 5.23 Example of Incorrect Board Design Rev. 1.00 Oct. 03, 2008 Page 146 of 962 REJ09B0465-0100 Section 6 Power-Down Modes Section 6 Power-Down Modes In addition to normal active mode, this LSI can enter either of the two power-down modes after release from a reset, in which power consumption is reduced. As other measures for reduced power consumption, this LSI also has a bus-master-clock division function for the low-speedoperation of bus masters, module standby function which allows the selective stopping of on-chip peripheral modules, and a PSC-divider stopping function. Further power consumption is possible by selecting the low-speed on-chip oscillator clock loco, or sub-oscillator clock sub as the source of the system clock to operate the LSI at a low speed. After release from a reset, all of the peripheral functions except timer RE are in the module standby state. Make the settings for the operation of module in the corresponding registers after the module standby state is released. * Active Mode The CPU and on-chip peripheral modules operate on the system clock . The system clock frequency can be selected from among base to base/128, where base is the system base clock. * Sleep Mode The CPU is stopped. On-chip peripheral modules operate on the system clock . * Standby Mode The CPU and all the on-chip peripheral modules are stopped. However, timer RE (TMRE) can operate when the realtime clock mode is selected. The watchdog timer (WDT) also operates when the low-speed OCO is selected as the WDT clock source. * Bus Master Clock Division Function For the bus masters CPU and DTC, ROM, and RAM, the operating clock s can be divided independently of the clock supplied to the peripheral modules. The bus master clock s can be selected from among to /32. * PSC Divider Stop Function The PSC divider can be stopped through software setting. Specifically, the peripheral modules using /2 to /8192 are stopped (register values are retained), whereas the ones using remain operating. * Module Standby Function Power consumption can be reduced by halting individual on-chip peripheral modules that are not in use. Rev. 1.00 Oct. 03, 2008 Page 147 of 962 REJ09B0465-0100 Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are listed below. * * * * * * Power-down control register 1 (LPCR1) Power-down control register 2 (LPCR2) Power-down control register 3 (LPCR3) Module standby control register 1 (MSTCR1) Module standby control register 2 (MSTCR2) Module standby control register 3 (MSTCR3) Power-Down Control Registers 1, 2, and 3 (LPCR1, LPCR2, LPCR3) 6.1.1 LPCR1, LPCR2, and LPCR3 control power-down modes. For details, see section 5, Clock Pulse Generator. 6.1.2 Module Standby Control Register 1 (MSTCR1) Address: H'FFFFDC Bit: b7 MSTWDT Value after reset: 1 b6 b5 MSTAD1 1 b4 MSTAD2 1 b3 MSTDA 1 b2 MSTDTC 1 b1 b0 1 1 1 Bit 7 6 5 Symbol MSTWDT MSTAD1 Bit Name Description R/W R/W R/W Watchdog timer 0: Operating state module standby 1: Standby state Reserved A/D converter unit 1 module standby A/D converter unit 2 module standby* This bit is read as 0. The write value should be 0. 0: Operating state 1: Standby state 0: Operating state 1: Standby state 4 MSTAD2 R/W 3 MSTDA D/A converter 0: Operating state module standby 1: Standby state R/W Rev. 1.00 Oct. 03, 2008 Page 148 of 962 REJ09B0465-0100 Section 6 Power-Down Modes Bit 2 1, 0 Symbol MSTDTC Bit Name DTC module standby Reserved Description 0: Operating state 1: Standby state R/W R/W These bits are read as 0. The write value should be 0. Notes: * When a peripheral module is in the module standby state, the registers of the module cannot be accessed. * MSTWDT bit (watchdog timer module standby) When this bit is set to 1, the WDT enters the standby state. Note that if the low-speed OCO is selected as the WDT count clock, the WDT operates regardless of the setting of this bit but the WDT registers cannot be accessed. * MSTAD1 bit (A/D converter unit 1 module standby) When this bit is set to 1, A/D converter unit 1 enters the standby state. * MSTAD2 bit (A/D converter unit 2 module standby) When this bit is set to 1, A/D converter unit 2 enters the standby state. A/D converter unit 2 is not available on the H8S/20103 and H8S/20203 groups; this bit is reserved on these devices. For a write-access, write 1 to this bit. * MSTDA bit (D/A converter module standby) When this bit is set to 1, the D/A converter enters the standby state. * MSTDTC bit (DTC module standby) When this bit is set to 1, the DTC enters the standby state. Rev. 1.00 Oct. 03, 2008 Page 149 of 962 REJ09B0465-0100 Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 2 (MSTCR2) Address: H'FFFFDD Bit: b7 b6 b5 b4 b3 b2 MSTICSU 1 b1 b0 MSTSCI3_1 MSTSCI3_2 MSTSCI3_3 Value after reset: 1 1 1 1 1 1 1 Bit 7 6 5 4, 3 2 1, 0 Symbol Bit Name Description R/W R/W R/W R/W R/W MSTSCI3_1 SCI3 channel 1 0: Operating state module standby 1: Standby state MSTSCI3_2 SCI3 channel 2 0: Operating state module standby 1: Standby state MSTSCI3_3 SCI3 channel 3 0: Operating state module standby 1: Standby state MSTICSU Reserved These bits are read as 1. The write value should be 1. IIC2/SSU 0: Operating state module standby 1: Standby state Reserved These bits are read as 1. The write value should be 1. Notes: 1. When a peripheral module is in the module standby state, the registers of the module cannot be accessed. 2. When writing to this register, write 1s to the reserved bits. * MSTSCI3_1 (SCI3 channel 1 module standby) When this bit is set to 1, SCI3 channel 1 enters the standby state. * MSTSCI3_2 (SCI3 channel 2 module standby) When this bit is set to 1, SCI3 channel 2 enters the standby state. * MSTSCI3_3 (SCI3 channel 3 module standby) When this bit is set to 1, SCI3 channel 3 enters the standby state. * MSTICSU (IIC2/SSU module standby) When this bit is set to 1, the IIC2 or SSU enters the standby state. Rev. 1.00 Oct. 03, 2008 Page 150 of 962 REJ09B0465-0100 Section 6 Power-Down Modes 6.1.4 Module Standby Control Register 3 (MSTCR3) Address: H'FFFFDE Bit: b7 MSTTMRA b6 MSTTMRB 1 b5 MSTTMRC 1 b4 b3 b2 b1 b0 MSTTMRE 0 MSTTMRD1 MSTTMRD2 MSTTMRG 1 1 1 Value after reset: 1 1 Bit 7 6 5 4 3 2 1 0 Symbol MSTTMRA MSTTMRB Bit Name Description R/W R/W R/W R/W R/W R/W R/W R/W Timer RA 0: Operating state module standby 1: Standby state Timer RB 0: Operating state module standby 1: Standby state MSTTMRC Timer RC 0: Operating state module standby 1: Standby state MSTTMRD1 Timer RD unit 0 0: Operating state module standby 1: Standby state MSTTMRD2 Timer RD unit 1 0: Operating state module standby 1: Standby state MSTTMRG Timer RG 0: Operating state module standby 1: Standby state MSTTMRE Reserved This bit is read as 1. The write value should be 1. Timer RE 0: Operating state module standby 1: Standby state Notes: 1. When a peripheral module is in the module standby state, the registers of the module cannot be accessed. 2. When writing to this register, write 1s to the reserved bits. Rev. 1.00 Oct. 03, 2008 Page 151 of 962 REJ09B0465-0100 Section 6 Power-Down Modes * MSTTMRA bit (timer RA module standby) When this bit is set to 1, timer RA enters the standby state. * MSTTMRB bit (timer RB module standby) When this bit is set to 1, timer RB enters the standby state. * MSTTMRC bit (timer RC module standby) When this bit is set to 1, timer RC enters the standby state. Timer RC is not available on the H8S/20203 and H8S/20223 groups; this bit is reserved on these devices. For a write-access, write 1 to this bit. * MSTTMRD1 bit (timer RD unit 0 module standby) When this bit is set to 1, timer RD unit 0 enters the standby state. * MSTTMRD2 bit (timer RD unit 1 module standby) When this bit is set to 1, timer RD unit 1 enters the standby state. Timer RD unit 1 is not available on the H8S/20103 group; this bit is reserved on the device. For a write-access, write 1 to this bit. * MSTTMRG bit (timer RG module standby) When this bit is set to 1, timer RG enters the standby state. * MSTTMRE bit (timer RE module standby) When this bit is set to 1, timer RE enters the standby state. Note that if the sub is selected as the count clock in realtime clock mode or output-compare mode, timer RE operates regardless of the setting of this bit but the timer RE registers cannot be accessed. Rev. 1.00 Oct. 03, 2008 Page 152 of 962 REJ09B0465-0100 Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among the operating modes. SLEEP instructions are used to cause a transition from the program execution state to the program halt state. Interrupts are used to return from the program halt state to the program execution state. When the RES pin is driven low or any other internal reset occurs, this LSI is placed in the reset state from any mode. After release from a reset, this LSI is placed in active mode. Reset state Operating clock: loco Program stop state Peripheral functions unavailable SSBY = 1 SLEEP instruction Interrupt Program execution state SSBY = 0 SLEEP instruction Interrupt Program halt state Peripheral functions available Standby mode Active mode Sleep mode Selectable clock sources: hoco osc loco sub Figure 6.1 Mode Transition Diagram Rev. 1.00 Oct. 03, 2008 Page 153 of 962 REJ09B0465-0100 Section 6 Power-Down Modes Table 6.1 shows the internal states of the LSI in each mode. Table 6.1 Internal State in Each Operating Mode LPCR1 PSCSTP = 0 Function System clock CPU Instruction execution Registers DTC ELC RAM I/O ports LPCR1 PSCSTP = 1 Active Mode Sleep Mode Active Mode Sleep Mode Standby Mode Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Stopped Retained Functioning Functioning 1 Functioning Stopped Retained Functioning 1 Stopped Stopped Retained Stopped Functioning Functioning Functioning Functioning* Functioning* Retained Functioning Functioning Functioning Functioning Functioning Functioning Retained Register contents are retained, but output goes to the highimpedance state. Functioning Retained External interrupts IRQ7 to IRQ0, NMI Functioning Functioning Functioning Functioning Retained*2 Functioning Retained*2 Peripheral Timer RA, Functioning modules timer RB, timer RC, timer RD_0, timer RD_1 Timer RE Functioning Functioning Functioning in realtime clock mode and retained in output-compare mode. Functioning Retained*2 Functioning Retained* 3 Functioning Timer RG Watchdog timer SCI3_1, SCI3_2, SCI3_3 Functioning Functioning Functioning Retained*2 Retained* 3 Retained Retained*3 Reset Functioning Retained*2 Retained*2 Rev. 1.00 Oct. 03, 2008 Page 154 of 962 REJ09B0465-0100 Section 6 Power-Down Modes LPCR1 PSCSTP = 0 Function LPCR1 PSCSTP = 1 Active Mode Sleep Mode Active Mode Sleep Mode Standby Mode Functioning Retained Functioning Retained*4 Retained Retained*4 Reset Reset Peripheral IIC2/SSU Functioning modules A/D Functioning converter_1, A/D converter_2 D/A converter Functioning Functioning Functioning Functioning Reset Notes: 1. The timers are stopped if /2 to /8192 is selected as the clock source of the eventgeneration timer. 2. The timers operate if is selected as the count clock. The timers are stopped if /2 to /8192 is selected as the count clock. 3. The WDT operates if the low-speed OCO is selected as its clock source. 4. The A/D converters operate when A/D conversion time = 43 states (max) is selected. The A/D converters are retained when the other conversion time is set. 6.2.1 Active Mode In active mode, the CPU, DTC, and all the on-chip peripheral modules operate on the system clock . The system clock frequency can be selected from among base, base/2, base/4, base/8, base/16, base/32, base/64, and base/128 according to the PHI[2:0] setting in LPCR2. 6.2.2 Sleep Mode When a SLEEP instruction is executed in active mode with the SSBY bit = 0 in LPCR1, a transition to sleep mode is made. In sleep mode, the CPU is stopped but the DTC and all the onchip peripheral modules operate on the system clock. CPU register contents are retained. When an interrupt is requested, sleep mode is canceled causing a transition to active mode and interrupt exception handling starts. Sleep mode cannot be canceled if the I bit in CCR is 1 or the requested interrupt is masked by the interrupt enable bit. After sleep mode is canceled, the highspeed or low-speed clock is selected as the system clock source depending on the SLEEPRS bit setting in LPCR1. When the RES pin is driven low or any other internal reset occurs, sleep mode is canceled causing a transition to the reset state. Rev. 1.00 Oct. 03, 2008 Page 155 of 962 REJ09B0465-0100 Section 6 Power-Down Modes 6.2.3 Standby Mode When a SLEEP instruction is executed in active mode with the SSBY bit = 1 in LPCR1, a transition to standby mode is made. In standby mode, clock oscillation is stopped and thus the CPU, DTC, and all the on-chip peripheral modules (except timer RE and WDT) are stopped. However, as long as the rated voltage is supplied, the following contents are retained: the CPU registers, the registers of some on-chip peripheral modules, and on-chip RAM. Additionally, onchip RAM contents will be retained as long as the voltage rated as the RAM data retention voltage is provided. The I/O ports go to the high-impedance state. When an interrupt is requested, standby mode is canceled causing a transition to active mode and interrupt exception handling starts. Standby mode cannot be canceled if the I bit in CCR is 1 or the requested interrupt is masked by the interrupt enable bit. After standby mode is canceled, the highspeed or low-speed clock is selected as the system clock source depending on the STBYRS bit setting in LPCR1. When the RES pin is driven low or any other internal reset occurs, standby mode is canceled causing a transition to the reset state. 6.3 Bus Master Clock Division Function In active or sleep mode, the operating clock for the CPU, DTC, on-chip ROM, and on-chip RAM can be divided independently of the clock supplied to the peripheral modules. Using a divided clock can reduce power consumption. The operating clock s for the bus masters and the on-chip ROM and on-chip RAM can be selected from among , /2, /4, /8, /16, and /32 according to the PHIS[2:0] setting in LPCR3. 6.3.1 Reset States For reset states, see section 3.3, Reset. Rev. 1.00 Oct. 03, 2008 Page 156 of 962 REJ09B0465-0100 Section 6 Power-Down Modes 6.4 Module Standby Function The module standby function is available for any peripheral module. When a module is set to the module standby state, the clock supply to the module stops placing the module in the power-down state. Setting the corresponding bit to the module in MSTCR to 1 places the module in the module standby state and clearing the bit cancels the module standby state. After release from a reset, all the modules except timer RE are in the module standby state; to use a module, cancel the module standby state of it. Note that the registers of the module in the module standby state cannot be accessed. 6.5 PSC Divider Stop Function When the peripheral modules do not use the PSC divider output, the PSC divider can be stopped by setting the PSCSTP bit in LPCR1 to 1. When the PSC divider is stopped, the peripheral modules using /2 to /8192 can be stopped as shown in table 6.1 (register values are retained). Before setting the PSCSTP bit to 1, set the peripheral modules using the PSC divider output to the module standby state. After release from a reset, the PSC divider is stopped since the PSCSTP bit is set to 1. For the PSCSTP bit, see section 5.2.3, Power-Down Control Register 1 (LPCR1). Rev. 1.00 Oct. 03, 2008 Page 157 of 962 REJ09B0465-0100 Section 6 Power-Down Modes Rev. 1.00 Oct. 03, 2008 Page 158 of 962 REJ09B0465-0100 Section 7 ROM Section 7 ROM The features of the on-chip flash memory are described below. 7.1 Overview * Programming/erasing method Four bytes are programmed simultaneously. A single block is erased at a time; only one block should be erased at a time even when the entire ROM area is to be erased. * Programming/erasing time Program ROM programming time: 150 s (typ.) for 4-byte simultaneous programming, i.e., 38 s (typ.) per byte Data flash programming time: 300 s (typ.) for 4-byte simultaneous programming, i.e., 75 s (typ.) per byte Erasing time: 200 ms (typ.) per block for the program ROM and data flash areas. * Reprogramming capability: The program ROM area can be reprogrammed up to 1000 times and the data flash area can be reprogrammed up to 10000 times. * Two on-board programming modes Boot mode: The on-chip SCI can be used for programming/erasing the user ROM area. In this mode, the communication bit rate between the host and this LSI can be automatically adjusted. User mode: Any interface can be used for programming/erasing the user ROM area. * Programmer mode A PROM programmer is used for programming/erasing. * Protection function Flash memory can be protected against erroneous programming and erasure. Lock-bit protection function can be set through software. * PROM-programmer protection/Boot-mode protection By writing specified data to a specified address range in user ROM, protection of the userROM area in boot mode and PROM-programmer mode can be established. * Access cycle Program ROM: One state Data flash: Two states Rev. 1.00 Oct. 03, 2008 Page 159 of 962 REJ09B0465-0100 Section 7 ROM 7.2 Block Configuration Figure 7.1 shows the blocks of the flash memory. The user ROM area contains the program ROM area for storing the microcomputer's operating program and the data flash area for storing data. In the figure, the thick-line frames each indicate an erasure block (erasing unit); the thin-line frames each indicate a programming unit. The values in the frames are addresses. Erasure can be done in erasure-block units shown in the figure 7.1. Programming can be done in 2-word or 4-byte units, each of which begins at the address whose lower four-bit value is H'0, H'4, H'8, or H'C. Rev. 1.00 Oct. 03, 2008 Page 160 of 962 REJ09B0465-0100 Section 7 ROM H8S/20103, H8S/20203, and H8S/20223 (program ROM: 128 kbytes, data flash: 8 kbytes) Programming unit: 4 bytes H'000000 Program ROM block 1 (erasing unit: 16 kbytes) H'000001 H'000005 H'000009 H'00000D H'000002 H'000006 H'00000A H'00000E H'000003 H'000007 H'00000B H'00000F H'000004 H'000008 H'00000C H'003FFC Program ROM block 2 (erasing unit: 32 kbytes) H'003FFD H'004001 H'003FFE H'004002 H'003FFF H'004003 H'004000 H'00BFFC Program ROM block 3 (erasing unit: 32 kbytes) H'00BFFD H'00C000 H'00BFFE H'00C000 H'00BFFF H'00C000 H'00C000 H'013FFC Program ROM block 4 (erasing unit: 32 kbytes) H'013FFD H'014001 H'013FFE H'014002 H'013FFF H'014003 H'014000 H'01BFFC Program ROM block 5 (erasing unit: 16 kbytes) H'01BFFD H'01C001 H'01BFFE H'01C002 H'01BFFF H'01C003 H'01C000 H'01FFFC H'01FFFD H'01FFFE H'01FFFF Data flash A (erasing unit: 4 kbytes) H'F00000 H'F00001 H'F00002 H'F00003 H'F00FFC Data flash B (erasing unit: 4 kbytes) H'F00FFD H'F01001 H'F00FFE H'F01002 H'F00FFF H'F01003 H'F01000 H'F01FFC H'F01FFD H'F01FFE H'F01FFF Figure 7.1 Block Configuration of Flash Memory (1) Rev. 1.00 Oct. 03, 2008 Page 161 of 962 REJ09B0465-0100 Section 7 ROM H8S/20102, H8S/20202, and H8S/20222 (program ROM: 96 kbytes, data flash: 8 kbytes) Programming unit: 4 bytes H'000000 Program ROM block 1 (erasing unit: 16 kbytes) H'000001 H'000005 H'000009 H'00000D H'000002 H'000006 H'00000A H'00000E H'000003 H'000007 H'00000B H'00000F H'000004 H'000008 H'00000C H'003FFC Program ROM block 2 (erasing unit: 32 kbytes) H'003FFD H'004001 H'003FFE H'004002 H'003FFF H'004003 H'004000 H'00BFFC Program ROM block 3 (erasing unit: 32 kbytes) H'00BFFD H'00C000 H'00BFFE H'00C000 H'00BFFF H'00C000 H'00C000 H'013FFC Program ROM block 4 (erasing unit: 16 kbytes) H'013FFD H'014001 H'013FFE H'014002 H'013FFF H'014003 H'014000 H'017FFC H'017FFD H'017FFE H'017FFF Data flash A (erasing unit: 4 kbytes) H'F00000 H'F00001 H'F00002 H'F00003 H'F00FFC Data flash B (erasing unit: 4 kbytes) H'F00FFD H'F01001 H'F00FFE H'F01002 H'F00FFF H'F01003 H'F01000 H'F01FFC H'F01FFD H'F01FFE H'F01FFF Figure 7.1 Block Configuration of Flash Memory (2) Rev. 1.00 Oct. 03, 2008 Page 162 of 962 REJ09B0465-0100 Section 7 ROM 7.3 CPU Reprogramming Mode In CPU reprogramming mode, the user ROM area can be reprogrammed by executing the software commands by the CPU. The software commands should be issued to the specific area to be reprogrammed in the user ROM area. If an interrupt is requested during erasure operation in CPU reprogramming mode, erasure can be suspended to process the interrupt. This is referred to as erase-suspend function. In erase-suspend mode, the user ROM area can be read through programming. The CPU has two reprogramming modes, EW0 mode and EW1 mode. Table 7.1 shows differences between the two modes. Table 7.1 Item Differences between EW0 Mode and EW1 Mode EW0 Mode EW1 Mode User ROM area A reprogramming-control program can be executed in the user ROM area. User ROM area excluding the blocks in which a reprogramming-control program is located. The program and erasure commands must not be executed on any block in which a reprogramming-control program is located. Read-array mode Area in which a reprogramming- User ROM area control program can be located Area in which a reprogramming- A reprogramming-control control program can be program must be transferred to executed RAM before execution. Area which can be reprogrammed User ROM area Limitations on software commands None Mode after software command execution Read-array mode Rev. 1.00 Oct. 03, 2008 Page 163 of 962 REJ09B0465-0100 Section 7 ROM Item CPU state during autoprogramming and auto-erasure EW0 Mode Operating state EW1 Mode Hold state (I/O ports retain the states in which they have been before the command is executed.) Flash memory state detection Read the FMPRSF, FMERSF, and FMEBSF bits in FLMSTR in a program. Conditions of transition to erase- Both the FMSPEN and The FMSPEN bit in FLMCR2 is suspend state FMSPREQ bits in FLMCR2 are set to 1 and an interrupt is set to 1. requested. Or, both the FMSPEN and FMISPE bits in FLMCR2 are set to 1 and an interrupt is requested. Conditions of Interrupt generation * The flash memory returns from the busy state to the ready state*1. The user ROM area is read 1 in the busy state* . Usable*2*3 Use of interrupts prohibited. * Usage of DTC Note: Usable*2 1. To avoid the generation of access to the user ROM area, set VOFR so that the variable vectors and interrupt processing routines are allocated to RAM. 2. Allocate DTC vectors and processing routines to RAM. Do not use the DTC for access to the user ROM area during E/W processing. If this is ignored, values read will be invalid. 3. Do not use the DTC if the reprogramming-control program is allocated to RAM. Rev. 1.00 Oct. 03, 2008 Page 164 of 962 REJ09B0465-0100 Section 7 ROM 7.3.1 EW0 Mode EW0 mode can be selected by transferring the reprogramming-control program to the RAM, branching to the program in the RAM, setting the FMEWMOD bit in FLMCR1 to 0, and setting the FMCMDEN bit in FLMCR1 to 1 (to enable software commands), in this order. Programming and erasure operations can be controlled through software commands. Completion of the software command and related information can be read out from the FLMSTR register. To cause a transition to erase-suspend mode during erasure, set both the FMSPEN and FMSPREQ bits in FLMCR2 to 1 (to enable a transition to erase-suspend mode and to request a transition to erase-suspend mode, respectively). Then wait for the transition time to erase-suspend mode (approximately 50 s), check that the FMRDY bit in FLMSTR is 1 (ready state), and access the user ROM area. Setting the FMSPREQ bit to 0 resumes erasure. When the interrupt is used, set the interrupt vector offset register (VOFR) such that access to the user ROM area is not generated. That is, the vectors should have addresses within the RAM and point to interrupt processing routine that are also in the RAM. 7.3.2 EW1 Mode EW1 mode can be selected by setting the FMEWMOD bit in FLMCR1 to 1, and then setting the FMCMDEN bit in FLMCR1 to 1 (to enable software commands). Programming and erasure operations can be controlled through software commands. Completion of the software command and related information can be read out from the FLMSTR register. To cause a transition to erase-suspend mode during erasure, set the FMSPEN bit in FLMCR2 to 1 (to enable a transition to erase-suspend mode), and then execute the erasure command. Note that the interrupt for causing a transition to erase-suspend mode must be enabled beforehand. This allows the interrupt request to be accepted when the transition time to erase-suspend mode has elapsed after the erasure command is executed. When an interrupt is requested, the FMSPREQ bit is automatically set to 1 (to request a transition to erase-suspend mode), thus suspending erasure. If erasure has not been completed at the end of interrupt processing (FMERCF = 1 in FLMSTR), resume erasure by setting the FMSPREQ bit to 0. Rev. 1.00 Oct. 03, 2008 Page 165 of 962 REJ09B0465-0100 Section 7 ROM 7.4 * * * * Register Descriptions Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Flash memory data flash protect register (DFPR) Flash memory status register (FLMSTR) Flash Memory Control Register 1 (FLMCR1) Address: H'FF0660 Bit: b7 7.4.1 b6 b5 b4 b3 FMLBD 0 b2 FMWUS 1 b1 FMEWMOD 0 b0 FMCMDEN 0 Value after reset: 0 0 0 0 Bit 7, 6 5, 4 3 2 Symbol FMLBD*1*2 FMWUS Bit Name Reserved Reserved Lock bit disable Description These bits are read as 0. The write value should be 0. 0: The lock bits are enabled. 1: The lock bits are disabled. R/W R/W R/W CPU 0: Reprogramming through byte instructions reprogramming- 1: Reprogramming through word instructions instruction select 0: EW0 mode 1: EW1 mode 1 0 FMEWMOD EW mode select FMCMDEN *1*2*3*4 R/W Flash memory 0: Flash memory software commands are disabled. R/W software 1: Flash memory software commands are enabled. command enable Notes: 1. When setting the bit to 1, first clear the bit to 0 and then immediately set the bit to 1; do not allow any interrupt to be generated between these operations. 2. The bit is cleared to 0 when the FMRDY bit changes from 0 to 1. 3. Set the FMEWMOD bit and then set the FMCMDEN bit to 1. 4. When setting the FMCMDEN bit to 1 while the FMEWMOD bit is 0, be sure to execute the program in the RAM. FLMCR1 enables/disables reprogramming/erasure, selects the reprogramming/erasure mode, enables/disables lock bits, and selects the reprogramming unit of the flash memory. For specific use, see section 7.6, Programming/Erasing. Rev. 1.00 Oct. 03, 2008 Page 166 of 962 REJ09B0465-0100 Section 7 ROM * FMLBD bit (lock bit disable) This bit disables the lock-bit function. Setting FMLBD to 1 enables erasing/programming the block to which the lock-bit protection is applied. For the relationship between the FMLBD bit and the lock bit for the block, see table 7.2 below. Command sequence error occurs when the erasing/programming command is executed while disabling the erase program. Table 7.2 FMLBD 1 0 Relationship between FMLBD, Lock Bit, and Corresponding Erasure/Programming Operation Lock Bit 1 (erased state) 0 (programmed state) Erasure/programming impossible Erasure/Programming Operation Erasure/programming possible * FMWUS bit (CPU reprogramming-instruction select) Setting the FMWUS bit to 0 enables software commands to be issued through byte instructions. Setting the FMWUS bit to 1 enables software commands to be issued through word instructions. For software commands, see section 7.6.1, Software Commands. * FMEWMOD bit (EW mode select) Setting the FMEWMOD bit to 0 and the FMCMDEN bit to 1 selects EW0 mode. Setting the FMEWMOD and FMCMDEN bits to 1 selects EW1. * FMCMDEN bit (flash memory software command enable) Setting the FMCMDEN bit to 1 enables software commands to be accepted. For issuing software commands to the data flash areas, appropriately set the flash memory data flash protect register (DFPR), which is described in section 7.4.3. Rev. 1.00 Oct. 03, 2008 Page 167 of 962 REJ09B0465-0100 Section 7 ROM 7.4.2 Flash Memory Control Register 2 (FLMCR2) Address: H'FF0661 Bit: b7 b6 b5 b4 FMRDYIE 0 b3 FMBSYRDIE 0 b2 FMISPE 0 b1 FMSPREQ 0 b0 FMSPEN 0 Value after reset: 0 0 0 Bit 7, 6 5 4 3 2 Symbol FMRDYIE *1*2 *1*3 FMISPE* 4 Bit Name Reserved Reserved Flash read-ready interrupt enable interrupt enable Description These bits are read as 0. The write value should be 0. 0: The ready interrupt is disabled. 1: The ready interrupt is enabled. 0: The busy-read interrupt is disabled. 1: The busy-read interrupt is enabled. R/W R/W R/W R/W FMBSYRDIE Flash busy-read Suspend-request 0: Transition to erase-suspend mode by an enable by interrupt interrupt request is disabled. request 1: Transition to erase-suspend mode by an interrupt request is enabled. Erase suspend Erase-suspend enable 0: Erasure is resumed. 1: Transition to erase-suspend mode is made. 0: Erase suspend is disabled. 1: Erase suspend is enabled. 1 0 FMSPREQ *1*5*6*7 FMSPEN *4*8 R/W R/W Notes: 1. 2. 3. 4. 5. 6. 7. 8. For programming the flash memory, set the FMSPEN bit to 1. The FMRDYIE bit is cleared to 0 when the FMRDY bit changes from 0 to 1. The FMBSYRDIE bit is cleared to 0 when the FMRDY bit changes from 0 to 1. When setting the bit to 1, first clear the bit to 0 and then immediately set the bit to 1; do not allow any interrupt to be generated between these operations. The FMSPREQ bit is set to 1 when an interrupt is generated if the FMSPEN bit is 1 in EW1 mode. The FMSPREQ bit is set to 1 when an interrupt is generated if the FMSPEN and FMISPE bits are 1 in EW0 mode. The FMSPREQ bit is cleared to 0 when the FMRDY bit changes from 0 to 1 upon completion of E/W. The FMSPEN bit is cleared to 0 when the FMRDY bit changes from 0 to 1 if the FMSPREQ bit is 0. Rev. 1.00 Oct. 03, 2008 Page 168 of 962 REJ09B0465-0100 Section 7 ROM FLMCR2 enables/disables flash memory interrupts, enables/controls a transition to erase-suspend mode. * FMRDYIE bit (flash read-ready interrupt enable) Setting the FMRDYIE bit to 1 enables an interrupt to be generated when the flash memory changes from the busy state to the ready state. * FMBSYRDIE bit (flash busy-read interrupt enable) Setting the FMBSYRDIE bit to 1 enables an interrupt to be generated when the user ROM area is accessed while the flash memory is in the busy state. * FMISPE bit (suspend-request enable by interrupt request) Setting the FMISPE bit to 1 in EW0 mode allows the FMSPREQ bit to be automatically set to 1 (to request a transition to erase-suspend mode) thus causing a transition to erase-suspend mode when an interrupt is requested. * FMSPREQ bit (erase suspend) Setting the FMSPREQ bit to 1 causes a transition to erase-suspend mode. To resume erasure, set the FMSPREQ bit to 0. * FMSPEN bit (erase-suspend enable) Setting the FMSPEN bit to 1 enables a transition to erase-suspend mode. Rev. 1.00 Oct. 03, 2008 Page 169 of 962 REJ09B0465-0100 Section 7 ROM 7.4.3 Flash Memory Data Flash Protect Register (DFPR) Address: H'FF0662 Bit: b7 b6 0 b5 0 b4 0 b3 0 b2 0 b1 DFPR1 0 b0 DFPR0 0 Value after reset: 0 Bit Symbol Bit Name Reserved Data flash B E/W disable*1*2 Data flash A E/W disable*1*2 Description These bits are read as 0. The write value should be 0. 0: E/W of data flash B is enabled. 1: E/W of data flash B is disabled. 0: E/W of data flash A is enabled. 1: E/W of data flash A is disabled. R/W R/W R/W 7 to 2 1 0 DFPR1 DFPR0 Notes: 1. When setting the bit to 0, first set the bit to 1 and then immediately set the bit to 0; do not allow any interrupt to be generated between these operations. 2. The DFPR bits are set to 1 when the FMCMDEN bit changes from 0 to 1. DFPR enables/disables reprogramming of data flash areas in block units. Before reprogramming the data flash areas, cancel the protection against reprogramming. * DFPR1 bit (data flash B E/W disable) Setting the DFPR1 bit to 1 disables software commands to be issued to data flash B. Setting the DFPR1 bit to 0 enables software commands to be issued to data flash B. * DFPR0 bit (data flash A E/W disable) Setting the DFPR0 bit to 1 disables software commands to be issued to data flash A. Setting the DFPR0 bit to 0 enables software commands to be issued to data flash A. Rev. 1.00 Oct. 03, 2008 Page 170 of 962 REJ09B0465-0100 Section 7 ROM 7.4.4 Flash Memory Status Register (FLMSTR) Address: H'FF0663 Bit: b7 FMRDYIF b6 FMBSYRDIF 0 b5 FMEBSF 0 b4 FMERSF 0 b3 FMPRSF 0 b2 b1 b0 FMRDY 1 Value after reset: 0 0 1 Bit 7 Symbol FMRDYIF *1*2*3 Bit Name Flash readready interrupt request flag Description 0: The flash read-ready interrupt is not being requested. 1: The flash read-ready interrupt is being requested. [Setting condition] * FMRDY changes from 0 to 1. [Clearing condition] * "1" is read from FMRDYIF and then the bit is cleared to 0. R/W R/W 6 FMBSYRDIF Flash busy- *2*3*4 read interrupt request flag 0: The flash busy-read interrupt is not being requested. 1: The flash busy-read interrupt is being requested. [Setting condition] * The user ROM area is accessed while the FMRDY is 0. [Clearing condition] * "1" is read from FMBSYRDIF and then the bit is cleared to 0. R/W 5 FMEBSF *3*5 Erasure/blank- 0: Successful end checking status 1: End with an error flag [Setting condition] The erasure command is executed and results in unsuccessful erasure. * The blank-checking command is executed and it is detected that the specified block is not blank. [Clearing condition] * The clear-status command is issued. * R Rev. 1.00 Oct. 03, 2008 Page 171 of 962 REJ09B0465-0100 Section 7 ROM Bit 4 Symbol FMERSF Bit Name Description R/W R Erase-suspend 0: Erase-suspend function is not being used. flag 1: Erase-suspend function is being used. [Setting condition] * Erase-suspend mode is being used. [Clearing condition] * Erase-suspend mode is not being used. 3 FMPRSF *3*5 Programming status flag 0: Successful end 1: End with an error [Setting conditions] * The programming command is executed and results in unsuccessful programming. * The lock-bit programming command is executed and results in unsuccessful programming. [Clearing condition] * The clear-status command is issued. R 2 1 0 FMRDY Reserved Reserved Flash memory ready/busy status flag This bit is read as 0. The write value should be 0. Reading this bit returns the value same as the FMRDY value. The write value should be 1. 0: Busy (programming or erasure in progress) 1: Ready [Setting condition] * The flash memory is not being programmed or erased. [Clearing condition] * The flash memory is being programmed or erased. R Notes: 1. 2. 3. 4. The FMRDYIF bit is set to 1 when the FMRDY bit changes from 0 to 1. When setting the bit to 0, first read 1 from the bit and then write 0 to the bit. The bit cannot be set to 1 through software. The FMBSYRDIF bit is set to 1 when the ROM area is accessed while the FMRDY bit is 0. 5. The bit is cleared to 0 when the clear-status command is executed. Rev. 1.00 Oct. 03, 2008 Page 172 of 962 REJ09B0465-0100 Section 7 ROM * FMRDYIF (flash read-ready interrupt request flag) The FMRDYIF bit indicates that the flash memory has changed from the busy state to the ready state. When the FMRDYIF bit is set to 1 while the FMRDYIE bit is 1, an interrupt request is generated. * FMBSYRDIF (flash busy-read interrupt request flag) The FMBSYRDIF bit indicates that the user ROM area is accessed while the flash memory is in the busy state. When the FMBSYRDIF bit is set to 1 while the FMBSYRDIE bit is 1, an interrupt request is generated. * FMEBSF (erasure/blank-checking status flag) The FMEBSF bit is a read-only bit indicating the state when erasure/blank-checking command is executed. * FMERSF (erase-suspend flag) The FMERSF bit is a read-only bit indicating the state of erase-suspend mode. * FMPRSF (programming status flag) The FMPRSF bit is a read-only bit indicating the state when programming command is executed. * FMRDY (flash memory ready/busy status flag) The FMRDY bit indicates the state of flash memory operation. Rev. 1.00 Oct. 03, 2008 Page 173 of 962 REJ09B0465-0100 Section 7 ROM 7.5 On-Board Programming The flash memory can be programmed/erased on board (boot mode and user mode), or by using a PROM programmer (programmer mode). When the reset is released, this LSI enters one of these modes depending on the levels of the signals input on the TEST, NMI, and ports, as shown in table 7.3. The levels of these signals must be fixed at least TBD states before the reset is released. When this LSI enters boot mode, the built-in boot program is initiated. The boot program transfers the programming-control program to the on-chip RAM, erases the flash memory areas entirely, and then executes the programming-control program. Boot mode is useful for on-board initial programming as well as forced recovery when programming/erasure in user mode is disabled. User mode is useful for erasing and reprogramming the specified blocks, which function is achieved by branching to the programming/erasure processing programs prepared by the user. Table 7.3 TEST 0 0 1 Note: NMI 1 0 x Pin Levels and Programming Mode Selection P85 x 1 x PB3 x x 0 PB2 x x 0 PB1 x x 0 PB0 x x 0 LSI Modes after Release from a Reset User mode Boot mode Programmer mode x: Do not care. 7.5.1 Boot Mode In boot mode, control commands and data for programming are transmitted from the externally connected host via SCI3_1 to program/erase the user ROM area. In boot mode, it is necessary to prepare the tool for transmitting control commands and data for programming, and the data for programming in the host. Asynchronous mode is used for serial communication. Figure 7.2 shows the system configuration in boot mode. Although interrupt requests are ignored in boot mode, interrupt requests should be disabled by the system. Rev. 1.00 Oct. 03, 2008 Page 174 of 962 REJ09B0465-0100 Section 7 ROM This LSI On-chip control-command analysis execution software Flash memory Host Programming tool and programming data Control commands and programming data RxD SCI Returned response TxD On-chip ROM Figure 7.2 System Configuration in Boot Mode (1) Serial Interface Settings by Host SCI3_1 is set to asynchronous mode, in which the serial transmission/reception format is set to 8bit data, one stop-bit, and no parity. When this LSI enters boot mode, the built-in boot program is initiated. When the boot program is initiated, this LSI measures the low-level period of asynchronous serial communication data (H'00) transmitted continuously from the host. This LSI then calculates the bit rate of transmission from the host, and adjusts the SCI bit rate so that it should match that of the host. After completing the bit rate adjustment, this LSI transmits one H'00 byte to the host to signal completion of bit rate adjustment. When successfully having received this completion signal, the host should transmit one H'55 byte to this LSI. When not, boot mode should be initiated again. Depending on the combination of the host's transfer bit rate and system clock frequency of this LSI, there might be a discrepancy between the bit rates of the host and this LSI. To prevent this, the transfer bit rate of the host and system clock frequency of this LSI should be set in the range of the value listed in table 7.4. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Measures low-level period (9 bits) (data: H'00) High-level period of 1 or more bits Figure 7.3 Automatic Adjustment of Bit Rates Rev. 1.00 Oct. 03, 2008 Page 175 of 962 REJ09B0465-0100 Section 7 ROM Table 7.4 System Clock Frequencies at which Automatic Adjustment of Bit Rates is Possible System Clock Frequency Range of LSI On-chip oscillator (10 MHz) Host Bit Rate 9600 bps 4800 bps 2400 bps Rev. 1.00 Oct. 03, 2008 Page 176 of 962 REJ09B0465-0100 Section 7 ROM (2) State Transition Figure 7.4 shows the state transitions in boot mode. (Adjusts bit rates.) Receives H'00, ..., H'00. Transmits H'00. (Signals adjustment completion.) Boot mode is initiated. (reset in boot mode) Adjusts bit rates. 1. Receives H'55. 2. Waits for an inquiry/ selection command. Receives an inquiry/ selection command. Responds to the inquiry/ selection command. Executes processing in response to the inquiry/ selection command. 3. (Receives an programming/ erasure status transition command) Erases the entire user ROM area. Receives a reading/checking command. 4. Waits for a programming/ erasure command. Responds to the command. Executes processing in response to the reading/ checking command. (Completes programming.) (Completes erasure.) (Receives a programming selection command.) (Receives an erasure selection command.) (The erasure block is specified.) Waits for erasure block information. Waits for the programming data. Figure 7.4 State Transitions in Boot Mode Rev. 1.00 Oct. 03, 2008 Page 177 of 962 REJ09B0465-0100 Section 7 ROM 1. After boot mode is initiated, this LSI adjusts the SCI3_1 bit rate so that it should match the host's bit rate. 2. This LSI sends the requested information to the host in response to inquiries regarding the size, configuration, and start addresses of the user ROM areas, information on the supported devices, etc. 3. On receiving transmission of a programming/erasure status command, this LSI erases the entire user ROM area automatically. 4. When completing erasure of the user ROM area, this LSI enters the programming/erasurecommand wait state. After transmission of the programming selection command, the host should transmit the address at which the programming should start and the programming data. When programming is completed, the host should transmit H'FFFFFFFF as the programming start address to terminate programming. This allows this LSI to return to the programming/erasure-command wait state from the programming-data wait state. If the above programming-termination command is once issued to an area in an erasure block and when that block is to be programmed again, erase the block before programming. Figure 7.5 shows an example of an erasure block containing the area that has been already programmed. On receiving an erasure selection command, this LSI enters the erasure-block-information wait state. After transmission of the erasure selection command, the host should transmit the erasure block number. When erasure is completed, the host should transmit H'FF as the erasure block number. This allows this LSI to return to the programming/erasure-command wait state from the erasure-block-information wait state. Note that erasure is necessary only when programming is once done in boot mode and then only a specific block is to be reprogrammed without applying a reset-start. If the necessary programming can be done in a single operation, such erasure processing is unnecessary because all the blocks are erased before this LSI enters the wait state for programming, erasure, or other commands. In addition to the programming/erasure commands, there are commands for sum checking and blank checking (erasure checking) of the user ROM areas, memory reading, and acquiring the current state information. Note that data can be read from the user ROM area only after the MAT has been automatically erased and then programmed. Rev. 1.00 Oct. 03, 2008 Page 178 of 962 REJ09B0465-0100 Section 7 ROM EB2 EB3 Programming end area EB4 Before reprogramming erase blocks EB3 and EB4 on which the programming end command is issued, erase the blocks (EB3 and EB4). EB5 Figure 7.5 Example of Erase Block Including Programmed Area Rev. 1.00 Oct. 03, 2008 Page 179 of 962 REJ09B0465-0100 Section 7 ROM 7.5.2 Specifications of Standard Serial Communication Interface in Boot Mode The boot program activated in boot mode communicates with the host via the on-chip SCI3_1. The following describes the specifications of the serial communication interface between the host and the boot program. The boot program has three states. 1. Bit-rate adjustment state In this state, the boot program adjusts the SCI3_1 bit rate to match that of the host to perform serial communication with the host. When this LSI is started up in boot mode, the boot program is activated and enters the bit-rate adjustment state, in which it receives command from the host and adjusts the bit rate accordingly. After bit rate adjustment is completed, the boot program enters the inquiry/selection state. 2. Inquiry/selection state In this state, the boot program responds to inquiry commands from the host. The device, clock mode, and bit rate are selected. Upon completion of selection, the boot program enters the programming/erasure state in response to the command for transition-to-programming/erasure state. Before entering the programming/erasure state, the boot program transfers the erasurerelated libraries to the on-chip RAM and erases the user ROM areas. 3. Programming/erasure state In this state, the boot program executes programming/erasure. The boot program transfers the program for programming/erasure to the on-chip RAM according to the command transmitted from the host and executes programming/erasure. The boot program also executes sum checking and blank checking as directed using the corresponding commands. Rev. 1.00 Oct. 03, 2008 Page 180 of 962 REJ09B0465-0100 Section 7 ROM Figure 7.6 shows the boot program states and processing flow. Reset Bit-rate adjustment state Inquiry/selection state Enters the programming/ erasure state. Inquiry Processes inquiry. Selection Processes selection. Processes userROM-area erasure. Programming/ erasure state Programming Processes programming. Erasure Processes erasure. Checking Processes checking. Figure 7.6 Boot Program States and Processing Flow Rev. 1.00 Oct. 03, 2008 Page 181 of 962 REJ09B0465-0100 Section 7 ROM (1) Bit-Rate Adjustment State In the bit-rate adjustment state, the boot program measures the low-level period of H'00 transmitted from the host and calculates the bit rate according to the measurement. The bit rate can be changed using the new-bit-rate selection command. On completion of bit rate adjustment, the boot program enters the inquiry/selection state. Figure 7.7 shows the sequence of bit rate adjustment. Host H'00 (30 times max.) Boot program Measures the length of one bit. H'00 (Adjustment completed) H'55 H'E6 (Response) H'FF (Error) Figure 7.7 Sequence of Bit Rate Adjustment (2) Communication Protocol 1. One-character command or one-character response A command or response consisting of one character used for inquiry or ACK code indicating a successful end. 2. n-character command or n-character response A command or response requiring 128 bytes of data used as a selection command or a response to an inquiry. The length of programming data is defined separately and so data size (length) is omitted here. 3. Error response Response to a command which has caused an error; two bytes, consisting of the error response and error code. 4. 128-byte programming command This command does not include its data size information. The data size can be acquired from the response to the programming-size inquiry command. Rev. 1.00 Oct. 03, 2008 Page 182 of 962 REJ09B0465-0100 Section 7 ROM 5. Response to memory reading command This response includes 4-byte size information. One-character command or one-character response Command or response n-character command or n-character response Data Data size Command or response Checksum Error response Error code Error response 128-byte programming command Address Command Data (128 bytes) Checksum Response to memory reading command Data size Response Data Checksum Figure 7.8 Formats in Communication Protocol * Command (1 byte): Inquiry, selection, programming, erasure, checking, etc. * Response (1 byte): Response to an inquiry * Size (1 or 2 bytes): The size of transmit/receive data excluding the command code, response, size, and checksum. * Data (n bytes): Particular data for a command or response * Checksum (1 byte): This is set so that the total sum of the values from the command- code field or response through the SUM field should be H'00. * Error response (1 byte): Error response to a command * Error code (1 byte): Type of an error that has occurred * Address (4 bytes): Address for programming * Data (128 bytes): Data for programming * Data size (4 bytes): Four-byte length included in the response to the memory reading command. Rev. 1.00 Oct. 03, 2008 Page 183 of 962 REJ09B0465-0100 Section 7 ROM (3) Inquiry/Selection State In this state, the boot program returns the information on the flash ROM in response to inquiry commands from the host, and selects the device, clock mode, and bit rate in response to the relevant selection commands. Table 7.5 lists inquiry/selection commands. Table 7.5 Command H'20 H'10 H'21 H'11 H'22 Inquiry/Selection Commands Command Name Supported-device inquiry Device selection Clock mode inquiry Clock mode selection Frequency-division-ratio inquiry Function Inquires about the device code and product name. Selects the device (code). Inquires about the number of selectable clock modes and each clock mode's value. Selects the clock mode. Inquires about the number of frequency types, the number of frequency division ratios, and the specific frequency division ratio values. Inquires about the maximum and minimum operating frequencies for the main and peripheral clocks. Inquires about the number of user ROM areas and first and last addresses of each MAT area. Inquires about the number of blocks and first and last addresses of each block Inquires about the size of a unit for programming. Selects the new bit rate. Erases the user ROM areas and enters the programming/erasure state. Inquires about the processing state of the boot program. H'23 Operating-frequency inquiry H'25 User-ROM-area information inquiry H'26 H'27 H'3F H'40 H'4F Erasure-block information inquiry Programming-size inquiry New bit-rate selection Transition-to-programming/erasure state Boot-program state inquiry The selection commands should be transmitted from the host in the following order: device selection (H'10), clock mode selection (H'11), and new bit-rate selection (H'3F). If the same selection command is transmitted more than one time, the last one is valid. Rev. 1.00 Oct. 03, 2008 Page 184 of 962 REJ09B0465-0100 Section 7 ROM All the commands in table 7.5 except for the boot-program-state inquiry command (H'4F) are valid until the boot program accepts the transition-to-programming/erasure-state command (H'40). That is, until the transition command is accepted, the host can repeatedly send inquiry and selection commands in table 7.5. The boot-program-state inquiry command (H'4F) is valid even after the boot program accepts the transition-to-programming/erasure-state command (H'40). (a) Inquiry about Supported Devices In response to the command for inquiry about the supported devices, the boot program returns the device codes of the supported devices and the product name of the boot program. Command H'20 * Command H'20 (1 byte): Inquiry about supported devices Response H'30 Size Number of devices Number of Device code characters Product name SUM * Response H'30 (1 byte): Response to the inquiry about supported devices * Size (1 byte): The size of transmit/receive data excluding the response-command, size, and checksum fields. Here, it refers to the total size used by the number-of-devices, number-ofcharacters, device-code, and product-name fields. * Number of devices (1 byte): The number of device types supported by the boot program in the microcomputer. * Number of characters (1 byte): The number of characters in the device-code and product-name fields. * Device code (4 bytes): Product names of the supported devices (ASCII code) * Product name (128 bytes): Product code of the boot program (ASCII code) * SUM (1 byte): Checksum This is set so that the total sum of the values from the response-code field through the SUM field should be H'00. Rev. 1.00 Oct. 03, 2008 Page 185 of 962 REJ09B0465-0100 Section 7 ROM (b) Device Selection In response to the device selection command, the boot program sets the specified supported device as the selected device. The boot program will return the information on the selected device in response to the subsequent inquiries. Command H'10 Size Device code SUM * Command H'10 (1 byte): Device selection * Size (1 byte): The number of characters in the device-code field (fixed to four). * Device code (4 bytes): The device code that has been returned in response to the inquiry about supported devices (ASCII code) * SUM (1 byte): Checksum Response H'06 * Response H'06 (1 byte): Response to device selection The ACK code is returned when the specified device code corresponds to one of the supported devices. Error response H'90 ERROR * Error response H'90 (1 byte): Error response to device selection * ERROR (1 byte): Error code H'11: Checksum error H'21: Device code error indicating device code disagreement (c) Inquiry about Clock Modes In response to the command for inquiry about clock modes, the boot program returns the information on the selectable clock modes. Command H'21 * Command H'21 (1 byte): Inquiry about clock modes Response H'31 Size Mode ... SUM Rev. 1.00 Oct. 03, 2008 Page 186 of 962 REJ09B0465-0100 Section 7 ROM * * * * (d) Response H'31 (1 byte): Response to the inquiry about clock modes Size (1 byte): The total size of the number-of-modes and mode fields Mode (1 byte): Selectable clock modes (example: H'01 denotes clock mode 1) SUM (1 byte): Checksum Clock Mode Selection In response to the command for clock mode selection, the boot program sets the specified clock mode as the selected clock mode. The boot program will return the information on the selected clock mode in response to the subsequent inquiries. The clock-mode selection command should be transmitted after the device selection command (H'10). Command H'11 Size Mode SUM * Command H'11 (1 byte): Clock mode selection * Size (1 byte): The number of characters in the mode field (fixed to one). * Mode (1 byte): The clock mode that has been returned in response to the inquiry about clock modes. * SUM (1 byte): Checksum Response H'06 * Response H'06 (1 byte): Response to clock mode selection The ACK code is returned when the specified clock mode corresponds to one of the selectable clock modes. Error response H'91 ERROR * Error response H'91 (1 byte): Error response to clock mode selection * ERROR (1 byte): Error code H'11: Checksum error H'22: Clock mode error indicating clock mode disagreement Even if value H'00 or H'01 has been returned in response to the clock-mode inquiry command as the number of modes, it is required to select the clock mode for each value. Rev. 1.00 Oct. 03, 2008 Page 187 of 962 REJ09B0465-0100 Section 7 ROM (e) Inquiry about Frequency Division Ratios In response to the command for inquiry about frequency division ratios, the boot program returns the information on the selectable frequency division ratios. Command H'22 * Command H'22 (1 byte): Inquiry about frequency division ratios Response H'32 Size Number of types Number of Frequency ... Frequency division ratio division ratios ... SUM * Response H'32 (1 byte): Response to the inquiry about frequency division ratios * Size (1 byte): The total size of the number-of-types, number-of-frequency-division-ratios, and frequency-division-ratio fields. * Number of types (1 byte): The number of operating clock signals for which frequency division ratios can be selected for the device. (For example, the value is H'02 if frequency division ratio settings can be made for the frequencies of the main and peripheral module operating clock signals.) * Number of frequency division ratios (1 byte): The number of selectable frequency division ratios for each operating clock signal. (For example, the number of selectable frequency division ratios for the main or peripheral module operating clock signal.) * Frequency division ratio (1 byte): The negative numerical value by which the frequency is divided. (Example: H'FE (-2) when the frequency is divided by two.) As many frequency-division-ratio fields are repeated as the number of corresponding frequency division ratios; and the combinations of the former and latter fields are repeated as many times as the number of types (= number of operating clock signals). * SUM (1 byte): Checksum Rev. 1.00 Oct. 03, 2008 Page 188 of 962 REJ09B0465-0100 Section 7 ROM (f) Inquiry about Operating Frequencies In response to the command for inquiry about operating frequencies, the boot program returns the number of operating frequency types and the respective maximum and minimum frequencies. Command H'23 * Command H'23 (1 byte): Inquiry about operating frequencies Response H'33 Size Number of operating frequencies Minimum operating Maximum operating frequency frequency ... SUM * Response H'33 (1 byte): Response to the inquiry about operating frequencies * Size (1 byte): The total size of the number-of-operating-frequencies, maximum-frequency, and minimum-frequency fields. * Number of operating frequencies (1 byte): The number of operating frequency types required for the device (For example, the value is H'02 if the main and peripheral module operating frequencies are required.) * Minimum operating frequency (2 bytes): The minimum frequency of a frequency-multiplied or divided clock signal The values in the minimum- and maximum-operating-frequency fields are obtained by multiplying the operating frequency (MHz; to the second decimal place) by 100. (For example, when the frequency is 20.00 MHz, 20.00 is multiplied by 100 to be 2000, and so H'07D0 is returned here.) * Maximum operating frequency (2 bytes): The maximum frequency of a frequency-multiplied or divided clock signal. As many pairs of the minimum- and maximum-operating-frequency fields are continued as the number of operating frequencies (= number of operating frequency types). * SUM (1 byte): Checksum Rev. 1.00 Oct. 03, 2008 Page 189 of 962 REJ09B0465-0100 Section 7 ROM (g) Inquiry about User ROM Area In response to the command for inquiry about the user ROM area, the boot program returns the number of user ROM areas and their addresses. Command H'25 * Command H'25 (1 byte): Inquiry about user ROM area Response H'35 Size Number of areas Last address of the area First address of the area ... SUM * Response H'35 (1 byte): Response to the inquiry about user ROM area * Size (1 byte): The total size of the number-of-areas, first-address-of-the-area, and last-addressof-the-area fields. * Number of areas (1 byte): The number of consecutive user ROM areas (H'01 is returned when the user ROM areas are continuous.) * First address of the area (4 bytes): The first address of the area * Last address of the area (4 bytes): The last address of the area As many pairs of the first-address-of-the-area and last-address-of-the-area fields are continued as the number of areas. * SUM (1 byte): Checksum (h) Inquiry about Erasure Blocks In response to the command for inquiry about erasure blocks, the boot program returns the number of erasure blocks and their addresses. Command H'26 * Command H'26 (1 byte): Inquiry about erasure blocks Rev. 1.00 Oct. 03, 2008 Page 190 of 962 REJ09B0465-0100 Section 7 ROM Response H'36 Size Number of blocks Last address of the block First address of the block ... SUM * Response H'36 (1 byte): Response to the inquiry about erasure blocks * Size (2 bytes): The total size of the number-of-blocks, first-address-of-the-block, and lastaddress-of-the-block fields. * Number of blocks (1 byte): The number of flash memory blocks to be erased * First address of the block (4 bytes): The first address of the block * Last address of the block (4 bytes): The last address of the block As many pairs of the first-address-of-the-block and last-address-of-the-block fields are continued as the number of blocks. * SUM (1 byte): Checksum (i) Inquiry about Programming Size In response to the command for inquiry about programming size, the boot program returns the size of a unit for programming. Command H'27 * Command H'27 (1 byte): Inquiry about programming size Response H'37 Size Programming size SUM * Response H'37 (1 byte): Response to the inquiry about programming size * Size (1 byte): The number of characters in the programming-size field (fixed to 2) * Programming size (2 bytes): The size of a unit for programming Programming data is received in the unit specified here. * SUM (1 byte): Checksum Rev. 1.00 Oct. 03, 2008 Page 191 of 962 REJ09B0465-0100 Section 7 ROM (j) New Bit-Rate Selection In response to the command for new bit-rate selection, the boot program changes the bit rate settings to those of the specified one, and responds to the acknowledgement from the host at the new bit rate. The new bit-rate selection command should be transmitted after the clock-mode selection command. Command H'3F Size Bit rate Input frequency Number of Frequency Frequency division frequency division ratio 2 division ratio 1 ratio types SUM * Command H'3F (1 byte): New bit-rate selection * Size (1 byte): The total size of the bit-rate, input-frequency, number-of-frequency-divisionratio-types, and frequency-division-ratio fields. * Bit rate (2 bytes): New bit rate The value to be set here is obtained by dividing the desired bit rate by 100. (For example, to select the bit rate of 19200 bps, 19200 is divided by 100 to be 192, and so H'00C0 should be set.) * Input frequency (2 bytes): The frequency of the clock input to the boot program. The value to be set here is obtained by multiplying the input frequency (MHz; to the second decimal place) by 100. (For example, to select the input frequency of 20.00 MHz, 20.00 is multiplied by 100 to be 2000, and so H'07D0 should be set.) * Number of frequency division ratio types (1 byte): The number of selectable frequency division ratios for the device. (The value is usually H'02 because the main and peripheral module operating frequencies can be usually selected.) * Frequency division ratio 1 (1 byte): Frequency division ratio for the main operating frequency. The negative numerical value by which the frequency is divided. (Example: H'FE (-2) when the frequency is divided by two.) * Frequency division ratio 2 (1 byte): Frequency division ratio for the peripheral operating frequency. The negative numerical value by which the frequency is divided. (Example: H'FE (-2) when the frequency is divided by two.) Rev. 1.00 Oct. 03, 2008 Page 192 of 962 REJ09B0465-0100 Section 7 ROM * SUM (1 byte): Checksum Response H'06 * Response H'06 (1 byte): Response to the new bit-rate selection command The ACK code is returned when selection is possible. Error response H'BF ERROR * Error response H'BF (1 byte): Error response to new bit-rate selection * ERROR (1 byte): Error code H'11: Checksum error H'24: Bit-rate selection error indicating that the specified bit rate is not selectable. H'25: Input frequency error indicating that the specified input frequency is not within the range from the minimum to maximum values. H'26: Frequency division ratio error indicating disagreement of frequency division ratios H'27: Operating frequency error indicating that the specified operating frequency is not within the range from the minimum to maximum values. (4) Checking Received Data The following describes how the received data is checked. 1. Input frequency The value of the received input frequency is checked to see if it is within the range from minimum to maximum values of the input frequency of the selected clock mode of the selected device. If not, an input frequency error is generated. 2. Frequency division ratio The value of the received frequency division ratio is checked to see if it corresponds to the frequency division ratio value of the selected clock mode of the selected device. If not, a frequency division ratio error is generated. Rev. 1.00 Oct. 03, 2008 Page 193 of 962 REJ09B0465-0100 Section 7 ROM 3. Operating frequency The operating frequency is calculated from the received input frequency and frequency division ratio. The input frequency is the frequency of the clock signal supplied to the LSI, whereas the operating frequency is the frequency at which the LSI actually operates. The following formula is used for the calculation. Operating frequency = input frequency/frequency division ratio The obtained operating frequency is checked to see if it is within the range from the minimum to maximum values of the operating frequency of the selected clock mode of the selected device. If not, an operating frequency error is generated. 4. Bit rate From the peripheral operating frequency () and bit rate (B), the value (n) of the clock select bits (CKS) in the serial mode register (SMR) and the value (N) in the bit rate register (BRR) are calculated to determine the error. The error determined is checked to see if it is smaller than 4%. If not, a bit-rate selection error is generated. The following formula is used for the calculation. x 106 Error (%) = (N + 1) x B x 64 x 22n-1 -1 x 100 When selection of the new bit rate is possible, the boot program returns an ACK code to the host and then makes the necessary register settings to select the new bit rate. The host then transmits an ACK code at the new bit rate and the boot program responds to it at the new bit rate. Acknowledge H'06 * Acknowledge H'06 (1 byte): Acknowledgement of the new bit rate Response H'06 * Response H'06 (1 byte): Response to acknowledgement of the new bit rate Figure 7.9 shows the sequence of new bit-rate selection. Rev. 1.00 Oct. 03, 2008 Page 194 of 962 REJ09B0465-0100 Section 7 ROM Host Selects the new-bit-rate selection command. H'06 (ACK) Waits for one-bit period at the selected bit rate. Boot program Sets the new bit rate. H'06 (ACK) at the new bit rate H'06 (ACK) at the new bit rate Sets the new bit rate. Figure 7.9 Sequence of New Bit-Rate Selection (5) Transition to Programming/Erasure State In response to the command for transition-to-programming/erasure state, the boot program transfers the erasure program to erase the data in the user ROM area. On completion of this erasure, the boot program returns the ACK code and enters the programming/erasure state. Before transmitting the programming selection command and data for programming, the host should select the device, clock mode, and new bit rate for this LSI using the device selection, clock-mode selection, and new-bit-rate selection commands; and then transmit a transition-toprogramming/erasure-state command to the boot program. Command H'40 * Command H'40 (1 byte): Transition to programming/erasure state Response H'06 * Response H'06 (1 byte): Response to the transition-to-programming/erasure-state command. The ACK code is returned when the user ROM area have been successfully erased after transfer of the erasure program. Error response H'C0 H'51 * Error response H'C0 (1 byte): Error response to the transition-to-programming/erasure-state command. Rev. 1.00 Oct. 03, 2008 Page 195 of 962 REJ09B0465-0100 Section 7 ROM * Error code H'51 (1 byte): Erasure error indicating that erasure was unsuccessful because of an error. (6) Command Errors Command errors are caused by undefined commands, incorrect command sequence, and unacceptable commands. For example, sending a clock-mode selection command before a device selection command and sending an inquiry command after a transition-to-programming/erasurestate command both cause command errors. Error response H'80 H'xx * Error response H'80 (1 byte): Command error * Command H'xx (1 byte): Received command (7) Order of Commands In the inquiry/selection state, commands should be sent in the following order. 1. Send the supported-device inquiry command (H'20) to get the list of supported devices. 2. Select a device according to the returned device information, and send the device selection command (H'10). 3. Send the clock-mode inquiry command (H'21) to inquire about clock modes. 4. Select a clock mode from among the returned clock modes, and send the clock-mode selection command (H'11). 5. After selection of the device and clock mode, send the frequency-division-ratio inquiry command (H'22) and operating-frequency inquiry command (H'23) to get the information necessary for selecting a new bit rate. 6. Select a new bit rate according to the returned information on the frequency division ratios and operating frequencies, send the new bit-rate selection command (H'3F). 7. After selection of the new bit rate, send the user-ROM-area-information inquiry command (H'25), erasure-block-information inquiry command (H'26), and programming-size inquiry command (H'27) to get the information necessary for programming/erasing the user ROM area. 8. After each inquiry of step [7], send the transition-to-programming/erasure-state command (H'40) to cause a transition to the programming/erasure state. Rev. 1.00 Oct. 03, 2008 Page 196 of 962 REJ09B0465-0100 Section 7 ROM (8) Programming/Erasure State In the programming/erasure state, the boot program selects the form of programming in response to the programming selection command and then writes the data in response to the 128-byte programming command; or the boot program erases the desired blocks in response to the erasure selection and block erasure commands. Table 7.6 lists the programming/erasure commands. Table 7.6 Command H'43 H'50 H'48 H'58 H'52 H'4B H'4D H'4F Programming/Erasure Commands Command Name User-ROM-area programming selection 128-byte programming Erasure selection Block erasure Memory reading Sum checking of user ROM area Blank checking of user ROM area Boot-program state inquiry Function Transfers the control program for user-ROM area programming. Executes 128-byte programming. Transfers the erasure-control program. Erases the block data. Reads data from memory. Executes sum checking of the user ROM area. Executes blank checking of the user ROM area. Inquires about the processing state of the boot program. 1. Programming Programming is performed by using the programming selection command and the 128-byte programming command. First, the host sends the user-ROM-area-programming selection command. Next, the host sends the 128-byte programming command. The boot program assumes that the 128 bytes of data included in the 128-byte programming command should be programmed according to the form of programming selected by the preceding programming selection command. To program more than 128 bytes, repeatedly send 128-byte programming commands. To terminate programming, the host should send the 128-byte programming command with address H'FFFFFFFF. On completion of programming, the boot program waits for the next programming/erasure selection command. To perform programming according to a different form of programming or to program a different MAT area subsequently, start the process by sending a programming selection command. The sequence of programming by the programming selection command and 128-byte programming command is shown in figure 7.10. Rev. 1.00 Oct. 03, 2008 Page 197 of 962 REJ09B0465-0100 Section 7 ROM Host Programming selection (H'43) Boot program Transfers the programming-control program. ACK 128-byte programming (address and data) Repeats the steps. Performs programming. ACK 128-byte programming (address = H'FFFFFFFF) ACK Figure 7.10 Programming Sequence 2. Erasure Erasure is performed by using the erasure selection command and the block erasure command. First, select erasure by the erasure selection command and then actually erase a specific block using the block erasure command. To erase multiple blocks, repeatedly send block erasure commands. To terminate erasure, the host should send the block erasure command with block number H'FF. On completion of erasure, the boot program waits for the next programming/erasure selection command. The sequence of erasure by the erasure selection command and block erasure command is shown in figure 7.11. Rev. 1.00 Oct. 03, 2008 Page 198 of 962 REJ09B0465-0100 Section 7 ROM Host Erasure selection (H'48) Boot program Transfers the erasurecontrol program. ACK Block erasure (block number) Repeats the steps. Performs erasure. ACK Block erasure (block number = H'FF) ACK Figure 7.11 Erasure Sequence (a) Selection of User-Rom Area Programming In response to the command for selection of user-ROM area programming, the boot program transfers the relevant programming-control program according to which the user ROM area is programmed. Command H'43 * Command H'43 (1 byte): Selection of programming the user ROM area Response H'06 * Response H'06 (1 byte): Response to the user-ROM-area programming selection command. The ACK code is returned upon completion of transferring the programming-control program. Error response H'C3 ERROR * Error response H'C3 (1 byte): Error response to the user-ROM-area programming selection command * ERROR (1 byte): Error code H'54: Selection processing error (processing was not completed because of a transfer error) Rev. 1.00 Oct. 03, 2008 Page 199 of 962 REJ09B0465-0100 Section 7 ROM (b) 128-Byte Programming In response to the 128-byte programming command, the boot program programs the user ROM area according to the programming-control program transferred in response to the user-ROM-area programming selection command. Command H'50 Data ... SUM Address ... * Command H'50 (1 byte): 128-byte programming * Address for programming (4 bytes): Address at which programming starts The address should be the multiple of the size returned in response to the programming-size inquiry command. [Example] H'00, H01, H'00, H'00: H'00010000 * Programming data (128 bytes): Data for programming The size of the programming data is the size returned in response to the programming-size inquiry command. * SUM (1 byte): Checksum Response H'06 * Response H'06 (1 byte): Response to the 128-byte programming command. The ACK code is returned upon completion of the requested programming. Error response H'D0 ERROR * Error response H'D0 (1 byte): Error response to the 128-byte programming command * ERROR (1 byte): Error code H'11: Checksum error H'53: Programming error (programming failed because of an error in programming) The specified address should be on a boundary corresponding to the unit of programming (programming size). For example, when the programming size is 128 bytes, the lower 8 bits of the address should be either H'00 or H'80. When less than 128 bytes of data are to be programmed, the host should transmit the data after padding the vacant bytes with H'FF. Rev. 1.00 Oct. 03, 2008 Page 200 of 962 REJ09B0465-0100 Section 7 ROM To terminate programming, send the 128-byte programming command with H'FFFFFFFF in the address-for-programming field. This informs the boot program that the data has been completely sent; the boot program then waits for the next programming/erasure selection command. Command H'50 Address SUM * Command H'50 (1 byte): 128-byte programming * Address for programming (4 bytes): Terminating code (H'FF, H'FF, H'FF, H'FF) * SUM (1 byte): Checksum Response H'06 * Response H'06 (1 byte): Response to the 128-byte programming command. The ACK code is returned upon termination of the programming process. Error response H'D0 ERROR * Error response H'D0 (1 byte): Error response to the 128-byte programming command * ERROR (1 byte): Error code H'11: Checksum error H'53: Programming error (programming failed because of an error in programming) (c) Erasure Selection In response to the erasure selection command, the boot program transfers the relevant erasurecontrol program. The data in the user ROM area is erased using the transferred erasure-control program. Command H'48 * Command H'48 (1 byte): Erasure selection Response H'06 * Response H'06 (1 byte): Response to the erasure selection command. The ACK code is returned upon completion of transferring the erasure-control program. Rev. 1.00 Oct. 03, 2008 Page 201 of 962 REJ09B0465-0100 Section 7 ROM Error response H'C8 ERROR * Error response H'C8 (1 byte): Error response to Erasure selection command * ERROR (1 byte): Error code H'54: Selection processing error (processing was not completed because of a transfer error) (d) Block Erasure In response to the block erasure command, the boot program erases the data in the specified block. Command H'58 Size Block number SUM * * * * Command H'58 (1 byte): Block erasure Size (1 byte): The number of characters in the block-number field (fixed to 1) Block number (1 byte): The number specific to the block to be erased SUM (1 byte): Checksum H'06 Response * Response H'06 (1 byte): Response to the block erasure command. The ACK code is returned when the specified block has been erased. Error response H'D8 ERROR * Error response H'D8 (1 byte): Error response to the block erasure command * ERROR (1 byte): Error code H'11: Checksum error H'29: Block number error (the specified block number is incorrect) H'51: Erasure error (an error occurred during erasure) On receiving the command with H'FF as the block number, the boot program terminates erasure processing and waits for the next programming/erasure selection command. Command H'58 Size Block number SUM Rev. 1.00 Oct. 03, 2008 Page 202 of 962 REJ09B0465-0100 Section 7 ROM * * * * Command H'58 (1 byte): Block erasure Size (1 byte): The number of characters in the block number field (fixed to 1) Block number (1 byte): H'FF (erasure terminating code) SUM (1 byte): Checksum H'06 Response * Response H'06 (1 byte): Response to the block erasure command for terminating erasure processing; ACK code is returned upon termination of the erasure process. To perform erasure again after issuing the command with H'FF as the block number, start the process by sending an erasure selection command. (e) Memory Reading In response to the memory reading command, the boot program returns the data stored in the specified address. Command H'52 Size Area Address for reading SUM Reading size * Command H'52 (1 byte): Memory reading * Size (1 byte): The total size of the area, address-for-reading, and reading-size fields (fixed to 9) * Area (1 byte): H'01: User ROM area Specifying an incorrect area causes an address error. * Address for reading (4 bytes): Address where reading starts * Reading size (4 bytes): The amount of data to be read * SUM (1 byte): Checksum Response H'52 Data SUM Reading address ... Rev. 1.00 Oct. 03, 2008 Page 203 of 962 REJ09B0465-0100 Section 7 ROM * * * * Response H'52 (1 byte): Response to the memory reading command Reading size (4 bytes): The amount of data to be read Data (128 bytes): The specified amount of data to be read out starting at the specified address SUM (1 byte): Checksum Error response H'D2 ERROR * Error response H'D2 (1 byte): Error response to the memory reading command * ERROR (1 byte): Error code H'11: Checksum error H'2A: Address error (the specified address for reading is not in the MAT) H'2B: Size error (the specified size (amount) is greater than the size of the MAT) (f) Sum Checking of User ROM Area In response to the command for sum checking of the user ROM area, the boot program adds all the data bytes in the user ROM area and returns the result. Command H'4B * Command H'4B (1 byte): Sum checking of the user ROM area Response H'5B Size Checksum for the MAT SUM * Response H'5B (1 byte): Response to the command for sum checking of the user ROM area * Size (1 byte): The number of characters in the checksum-for-the-MAT field (fixed to 4) * Checksum for the MAT (4 bytes): Result of checksum calculation for the user ROM area; the total of all the data in the MAT, in byte units. * SUM (1 byte): Checksum (for this response) (g) Blank Checking of User ROM Area In response to the command for blank checking of the user ROM area, the boot program checks to see if the whole area of the user ROM area is blank and returns the result. Command H'4D Rev. 1.00 Oct. 03, 2008 Page 204 of 962 REJ09B0465-0100 Section 7 ROM * Command H'4D (1 byte): Blank checking of the user ROM area Response H'06 * Response H'06 (1 byte): Response to the command for blank checking of the user ROM area. The ACK code is returned when the whole area is blank (all bytes are H'FF). Error response H'CD H'52 * Error response H'CD (1 byte): Error response to the command for blank checking of the user ROM area * Error code H'52 (1 byte): Non-erased error (h) Inquiry about Boot Program State In response to the command for inquiry about the boot program state, the boot program returns its current state and error information. This inquiry can be made either in the inquiry/selection state or the programming/erasure state. Command H'4F * Command H'4F (1 byte): Inquiry about boot program state Response H'5F Size STATUS ERROR SUM Response H'5F (1 byte): Response to the inquiry about boot program state Size (1 byte): The number of characters in the STATUS and ERROR fields (fixed to 2) STATUS (1 byte): State of the boot program ERROR (1 byte): Error information ERROR = 0: Success ERROR 0: Error * SUM (1 byte): Checksum * * * * Rev. 1.00 Oct. 03, 2008 Page 205 of 962 REJ09B0465-0100 Section 7 ROM Table 7.7 Code H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F State Codes Description Waiting for device selection Waiting for clock mode selection Waiting for bit rate selection Waiting for transition to programming/erasure state (bit rate selection completed) Programming or erasure state (programming/erasure in progress) Waiting for programming/erasure selection (erasure completed) Waiting to receive data for programming (programming completed) Waiting for erasure block specification (erasure completed) Table 7.8 Code H'00 H'11 H'12 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF Error Codes Description No error Checksum error Programming size error Device-code disagreement error Clock-mode disagreement error Bit-rate selection disable error Input frequency error Frequency division ratio error Operating frequency error Block number error Address error Data size error Erasure error Non-erased error Programming error Selection processing error Command error Bit-rate-adjustment acknowledge error Rev. 1.00 Oct. 03, 2008 Page 206 of 962 REJ09B0465-0100 Section 7 ROM 7.5.3 Programming/Erasing in User Mode On-board programming/erasing of individual flash memory blocks is also possible in user mode by branching to the user programming/erasure-control program. The user must set the branching conditions and provide the on-board means of supplying the programming data. The flash memory must contain the user programming/ erasure-control program or a program that allows the user programming/erasure-control program to be supplied externally. As the flash memory itself cannot be read during programming/erasing, transfer the user programming/erasure-control program to the on-chip RAM to execute, as in boot mode. Figure 7.12 shows a sample procedure for programming/erasing in user mode. Prepare user programming/erasure-control program in accordance with the description in section 7.6, Programming/Erasing. Reset-start No Programming/erasing Yes Transfer the programming/erasurecontrol program to RAM. Branch to the application program in flash memory. Branch to the programming/erasurecontrol program in RAM. Execute the programming/erasurecontrol program (reprogram the flash memory). Branch to the application program in flash memory. Figure 7.12 Sample Programming/Erasing Procedure in User Mode (EW0 Mode) Rev. 1.00 Oct. 03, 2008 Page 207 of 962 REJ09B0465-0100 Section 7 ROM 7.6 Programming/Erasing The CPU reprogramming method is employed to program and erase flash memory on board, in which the CPU executes software commands. 7.6.1 Software Commands Table 7.9 shows a list of software commands through word instructions and table 7.10 shows a list of software commands through byte instructions. Whether an instruction is to be byte-length or word-length is specified by the FMWUS bit in FLMCR1. Table 7.9 Software Commands (in Word Instructions: FMWUS = 1) First Command Cycle Mode Addr. Data Software Command Erasure Programming Blank checking Lock-bit programming Read-array Clear-status Lock-bit reading Second Command Cycle Mode Addr. Data Third Command Command Use in Cycle Modes Mode Addr. Data EW0 EW1 Write x Write WA Write x Write x Write x Write x Write x H'2020 H'4141 H'2525 H'7777 Write BA Write WA Write BA Write BA H'D0D0 Possible Possible WD2 Possible Possible Possible Possible Possible Possible Possible Possible Possible WD1 Write WA H'D0D0 H'D0D0 H'FFFF H'5050 H'7171 Read BA H'xxxx Possible Impossible [Legend] x: Arbitrary address in the user ROM area xx: Eight-bit arbitrary data BA: Arbitrary address in a block WA: Programming address. (The lower two bits of an address are ignored. WA should be the same in each command cycle.) WDn: Programming data (16 bits) Rev. 1.00 Oct. 03, 2008 Page 208 of 962 REJ09B0465-0100 Section 7 ROM Table 7.10 Software Commands (in Byte Instructions: FMWUS = 0) First Command Cycle Mode Addr. Data Software Command Erasure Programming Third Command Second to Fifth Command Use in Command Cycle Command Cycle Modes Mode Addr. Data Mode Addr. Data EW0 EW1 Write x Write WA H'20 Write BA H'41 Write WA H'D0 WD1 Write WA Possible Possible WD2 Possible Possible to WD4 Possible Possible Possible Possible Possible Possible Possible Possible Blank checking Lock-bit programming Read-array Clear-status Lock-bit reading Write x Write x Write x Write x Write x H'25 Write BA H'77 Write BA H'FF H'50 H'71 Read BA H'D0 H'D0 H'xx Impossible [Legend] x: Arbitrary address in the user ROM area xx: Eight-bit arbitrary data BA: Arbitrary address in a block WA: Programming address. (The lower two bits of an address are ignored. WA should be the same in each command cycle.) WDn: Programming data (8 bits) Rev. 1.00 Oct. 03, 2008 Page 209 of 962 REJ09B0465-0100 Section 7 ROM (1) Initialization for CPU Reprogramming Mode Before software commands are issued, settings for CPU reprogramming mode must be made and issuing of software commands must be permitted. Figure 7.13 shows initialization for CPU reprogramming mode. Rev. 1.00 Oct. 03, 2008 Page 210 of 962 REJ09B0465-0100 Section 7 ROM Flow of initialization for EW0 mode*1 Start 1 Transfer the overwriting program to RAM. Command issued for the program region? No Yes Set the interrupt vector offset by VOFR and place the interrupt vectors in RAM.*1 FMLBD = 1 Jump to the overwriting program in RAM. Command issued for data flash? No Yes FMEWMOD = 0 DFPR[x] = 0*2 FMCMDEN = 1 To processing for issuing commands 1 Flow of initialization for EW1 mode*1 Start FMEWMOD = 1 FMCMDEN = 1 Command issued for the program region? No Yes FMLBD = 1 Command issued for data flash? No Yes DFPR[x] = 0*2 To processing for issuing commands Notes: For any interrupts that are in use, allocate the interrupt vector entries and interrupt routines to RAM. If interrupts are not to be used, allocation to RAM is not necessary. 1. Within the flow, set the CPU overwriting unit selection bit (FMWUS) to select the unit of overwriting. 2. Set the DFPR according to the area of data-flash memory for which commands are to be issued. Figure 7.13 Initialization for E/W Mode Rev. 1.00 Oct. 03, 2008 Page 211 of 962 REJ09B0465-0100 Section 7 ROM (2) Erasure When H'20 is written in the first command cycle and H'D0 is written to any address in the block in the second command cycle, erase/erase-verify of the specified block is automatically started. Completion of erasure is indicated by the FMRDY bit in FLMSTR. The FMRDY bit is read as 0 during erasure, and read as 1 after erasure completion. After erasure completion, the erasure result can be checked by reading the FMEBSF bit in FLMSTR. (See the description in (9) below, Full Status Checking.) Note that if the lock bit is 0 (locked) in the specified block and the FMLBD bit is 0 (lock bit enabled), an erasure command is not accepted for the specified block. Figures 7.14 and 7.15 show the flowcharts when the erase-suspend function is not used and when used, respectively. When the erase-suspend function is being employed and erasure is resumed immediately after a period in erase-suspend mode, instruction fetching with normal incrimination of the program counter will not be possible. To avoid this problem, add two NOP instructions immediately after the instruction that writes FMSPRE = 0. Furthermore, do not use the DTC when erasure has been suspended in EW1 mode and the reprogramming control program has been allocated to RAM. In EW1 mode, do not execute this command for the block in which the reprogramming-control program is located. The FMRDY bit in FLMSTR changes to 0 when erasure is started, and changes to 1 when completed. Rev. 1.00 Oct. 03, 2008 Page 212 of 962 REJ09B0465-0100 Section 7 ROM Start Write software command H'20. Write H'D0 to any address in the specified block. FMRDY = 1? Yes Full status check No Erasure end Figure 7.14 Flowchart When Erase-Suspend Function is Not Used Rev. 1.00 Oct. 03, 2008 Page 213 of 962 REJ09B0465-0100 Section 7 ROM (EW0 mode) Start Interrupt request*1*2 FMSPEN = 1 FMSPREQ = 1 Write software command H'20. FMRDY = 1? Yes No Write H'D0 to any address in the specified block. Access to flash memory FMSPREQ = 0 FMRDY = 1? Yes Full status check No RTE Erasure end (EW1 mode) Start Interrupt request*2 FMSPEN = 1 Access to flash memory Write software command H'20. RTE Write H'D0 to any address in the specified block. FMSPREQ = 0 NOP NOP FMRDY = 1? Yes Full status check No Erasure end Notes: 1. In EW0 mode, set VOFR and, locate the vector and handling routines of the used interrupts in the RAM. 2. When an interrupt request is generated, it takes the transition time to erase-suspend mode for the request to be accepted. To allow a transition to the erase-suspend state, enable the relevant interrupt beforehand. Figure 7.15 Flowchart When Erase-Suspend Function is Used Rev. 1.00 Oct. 03, 2008 Page 214 of 962 REJ09B0465-0100 Section 7 ROM (3) Programming A program command is used to program data in the flash memory in 4-byte units. Command or data size can be set depending on the FMWUS bit in FLMCR1. Setting the FMWUS bit to 0 enables using byte instructions. When H'41 is written in the first command cycle and data is written to the programming address in the second through fifth command cycles, programming and verifying are automatically started*. Setting the FMWUS bit to 1 enables using word instructions. When H'4141 is written in the first command cycle and data is written to the programming address in the second and third command cycles, programming and verifying are started*. Completion of programming is indicated by the FMRDY bit in FLMSTR. The FMRDY bit is read as 0 during programming, and read as 1 after programming completion. After programming completion, the programming result can be checked by reading the FMPRSF bit in FLMSTR. (See the description in (9) below, Full Status Checking.) Figure 7.16 shows the programming flowchart. Do not additionally program the already-programmed addresses. Note that if the lock bit is 0 (locked) in the specified block and the FMLBD bit is 0 (lock bit enabled), a programming command is not accepted for the specified block. In EW1 mode, do not execute this command for the block in which the reprogramming-control program is located. The FMRDY bit in FLMSTR changes to 0 when programming is started, and changes to 1 when completed. Note: * The lower two bits of the programming addresses are ignored. Rev. 1.00 Oct. 03, 2008 Page 215 of 962 REJ09B0465-0100 Section 7 ROM Start Write software command H'41 to the programming address. Write data to the programming address. FMRDY = 1? Yes Full status check No Programming end Figure 7.16 Programming Flowchart Rev. 1.00 Oct. 03, 2008 Page 216 of 962 REJ09B0465-0100 Section 7 ROM (4) Blank Checking When H'25 is written in the first command cycle and H'D0 is written to any address in the block in the second command cycle, blank checking of the specified block is started. Completion of blank checking is indicated by the FMRDY bit in FLMSTR. The FMRDY bit is read as 0 during blank checking, and read as 1 after blank checking completion. After blank checking completion, the blank checking result can be checked by reading the FMEBSF bit in FLMSTR. (See the description in (9) below, Full Status Checking.) Figure 7.17 shows the blank checking flowchart. The FMRDY bit in FLMSTR changes to 0 when blank checking is started, and changes to 1 when completed. Start Write software command H'25. Write H'D0 to an address in the specified block. FMRDY = 1? Yes Full status check No Blank checking end Figure 7.17 Blank Checking Flowchart Rev. 1.00 Oct. 03, 2008 Page 217 of 962 REJ09B0465-0100 Section 7 ROM (5) Lock-Bit Programming When H'77 is written in the first command cycle and H'D0 is written to any address in the block in the second command cycle, lock-bit programming of the specified block is started. Completion of lock-bit programming is indicated by the FMRDY bit in FLMSTR. The FMRDY bit is read as 0 during lock-bit programming, and read as 1 after lock-bit programming completion. After lock-bit programming completion, the lock-bit programming result can be checked by reading the FMPRSF bit in FLMSTR. (See the description in (9) below, Full Status Checking.) Figure 7.18 shows the lock-bit programming flowchart. The FMRDY bit in FLMSTR changes to 0 when lock-bit programming is started, and changes to 1 when completed. Start Write software command H'77. Write H'D0 to an address in the specified block. FMRDY = 1? Yes Full status check No Lock-bit programming end Figure 7.18 Lock-Bit Programming Flowchart Rev. 1.00 Oct. 03, 2008 Page 218 of 962 REJ09B0465-0100 Section 7 ROM (6) Read-Array Command A read-array command is to cause a transition to a mode in which data can be read from flash memory. When H'FF is written in the first command cycle, a transition to read array mode is caused. When the specified addresses are read out in the subsequent command cycles, data is read from the specified addresses. Since read-array mode is retained until any other command is written, multiple addresses can be read successively. (7) Lock-Bit Reading Command A lock-bit reading command is to cause a transition to a mode in which the lock bit in flash memory can be read. When H'71 is written in the first command cycle and H'D0 is written to any address in the block in the second command cycle, lock-bit reading of the specified block is started. After transition to lock-bit read mode, reading the specified block address BA returns the lock-bit value in the bit 14 value to be read. Do not execute a lock-bit read command in the ROM. (8) Status Clearing Command A clear-status command is used to clear the status flag to 0. When H'50 is written in the first command cycle, the FMPRSF and FMEBSF bits in FLMSTR are cleared to 0. (9) Full Status Checking When any command (other than the read-array command, lock bit reading command and clearstatus command) is issued, full-status checking is performed to confirm whether or not there was an error. When an error occurs, the FMPRSF and FMEBSF bits in FLMSTR are set to 1, indicating the occurrence of the relevant errors. Table 7.11 shows the bit values in FLMSTR and the corresponding errors. Figure 7.19 shows the full status checking flowchart and procedures of handling each error. Rev. 1.00 Oct. 03, 2008 Page 219 of 962 REJ09B0465-0100 Section 7 ROM Table 7.11 Bit Values in FLMSTR and Corresponding Errors Bit Values in FLMSTR FMEBSF 0 0 FMPRSF 0 1 Error Successful end Programming error The programming command is executed and results in unsuccessful programming. The lock-bit programming command is executed and results in unsuccessful programming. The erasure command is executed and results in unsuccessful erasure. The blank checking command is executed and it is detected that the specified block is not blank. * * A command is not written correctly. A data value other than H'D0 and H'FF is written in the last cycle of the command that consists of two command cycles. The erasure command is input in erase-suspend mode. The programming command is input for the suspended block in erase-suspend mode. Error Generation Conditions Lock-bit programming error 1 0 Erasure error Blank checking error 1 1 Command sequence error * * Rev. 1.00 Oct. 03, 2008 Page 220 of 962 REJ09B0465-0100 Section 7 ROM Full status check FMEBSF = 1 and FMPRSF = 1 No Yes Command sequence error Erasure/blank-checking status flag FMEBSF = 1 No Yes Erasure error or blank checking error Programming status flag FMPRSF = 1 Yes Programming error or lock-bit programming error Full status check end Command sequence error Erasure error Execute the clear-status command. (Clear the status flag to 0). Execute the clear-status command. (Clear the status flag to 0). Check that the command is input correctly. Has the erase command been re-executed three or less times? The target block is unavailable. Re-execute the erasure command. Re-execute the erasure command. Programming error Lock-bit programming error Execute the clear-status command. (Clear the status flag to 0). Execute the clear-status command. (Clear the status flag to 0). Specify the different address from the address having caused an error as the programming address. Has the lock-bit programming command been executed 1000 or less times in total? The target block is unavailable. Re-execute the erasure command. Re-execute the lock-bit programming command. Figure 7.19 Full Status Checking Flowchart and Procedures of Handling Errors Rev. 1.00 Oct. 03, 2008 Page 221 of 962 REJ09B0465-0100 Section 7 ROM (10) Example of Issuing Commands Figures 7.20 and 7.21 show examples of issuing programming commands and erasure commands, respectively. Figure 7.22 shows examples of issuing read-array commands. Using word-length instructions to issue programming commands (FMWUS = 1) [Programming Example] @MOV.W #H'4141,R0 @MOV.W #H'1234,R1 @MOV.W #H'5678,R2 @MOV.W R0, @H'00004000 @MOV.W R1, @H'00004000 @MOV.W R2, @H'00004000 Target address for writing Data H'12 H'34 H'56 H'78 H'004000 H'004001 H'004002 H'004003 ; Programming command ; Writing of data ; Writing of data ; First command ; Second command ; Third command Prefetching and other Prefetching and other internal processing internal processing Issuing of third Programming of flash Issuing of second Issuing of first command ROM starts command command Internal address bus Internal data bus H'004000 H'4141 H'004000 H'1234 H'004000 H'5678 Using byte-length instructions to issue programming commands (FMWUS = 0) [Programming Example] @MOV.B #H'41, R0L @MOV.W #H'1234,R1 @MOV.W #H'5678,R2 @MOV.B R0L, @H'00004000 @MOV.B R1H, @H'00004000 @MOV.B R1L, @H'00004000 @MOV.B R2H, @H'00004000 @MOV.B R2L, @H'00004000 Target address for writing Data H'12 H'34 H'56 H'78 H'004000 H'004001 H'004002 H'004003 ; Programming command ; Writing of data ; Writing of data ; First command ; Second command ; Third command ; Fourth command ; Fifth command Prefetching and other Prefetching and other Prefetching and other Prefetching and other internal processing internal processing internal processing internal processing Issuing of fourth Issuing of fifth Issuing of first Issuing of second Issuing of third command command command command command Programming of flash ROM starts Internal address bus Internal data bus H'004000 H'41 H'004000 H'12 H'004000 H'34 H'004000 H'56 H'004000 H'78 Figure 7.20 Examples of Issuing Programming Commands Rev. 1.00 Oct. 03, 2008 Page 222 of 962 REJ09B0465-0100 Section 7 ROM Using word-length instructions to issue erasure commands (FMWUS = 1) [Erasure Setting] Erasure block = Data flash A [Programming Example] @MOV.W @MOV.W @MOV.W @MOV.W #H'2020,R0 #H'D0D0,R1 R0,@H'00F00000 R1,@H'00F00000 ; Erasure command ; Erasure command ; First command ; Second command Prefetching and other internal processing Issuing of first Issuing of second command command Programming of flash ROM starts Internal address bus Internal data bus H'F00000 H'2020 H'F00000 H'D0D0 Using byte-length instructions to issue erasure commands (FMWUS = 0) [Erasure Setting] Erasure block = Data flash A [Programming Example] @MOV.B @MOV.B @MOV.B @MOV.B #H'20, R0L #H'D0, R0H R0L,@H'00F00000 R0H,@H'00F00000 ; Erasure command ; Erasure command ; First command ; Second command Prefetching and other internal processing Issuing of second Programming of flash Issuing of first command command ROM starts Internal address bus Internal data bus H'F00000 H'20 H'F00000 H'D0 Figure 7.21 Examples of Issuing Erasure Commands Rev. 1.00 Oct. 03, 2008 Page 223 of 962 REJ09B0465-0100 Section 7 ROM Using word-length instructions to issue read-array commands (FMWUS = 1) [Read-Array Setting] Address = Program-ROM area [Programming Example] ; Read-array command @MOV.W #H'FFFF, R0 @MOV.W R0, @H'00000000 ; First command Issuing of first command Reading can proceed. Address bus Data bus H'000000 H'FFFF Using byte-length instructions to issue read-array commands (FMWUS = 0) [Read-Array Setting] Address = Program-ROM area [Programming Example] ; Read-array command @MOV.B #H'FF, R0L @MOV.B R0L,@H'00000000 ; First command Issuing of first command Reading can proceed. Address bus Data bus H'000000 H'FF Figure 7.22 Examples of Issuing Read-Array Commands Rev. 1.00 Oct. 03, 2008 Page 224 of 962 REJ09B0465-0100 Section 7 ROM 7.7 Protection Three modes are available to protect the flash memory against reading, programming, and erasing: software protection, lock-bit protection, and protection to restrict access in programmer mode and boot mode. 7.7.1 Software Protection Software commands can be disabled by clearing the FMCMDEN bit in the flash memory control register (FLMCR1) through software. In this state, no software commands are executed even if input. Data flash areas can be protected in block units by using the flash memory data flash protect register (DFPR). Setting bits DFPR1 and DFPR0 in DFPR to 1 places all the data flash areas in protect mode. 7.7.2 Lock-Bit Protection The programming/erasure commands can be disabled by programming the lock bits using the lock-bit programming command. In this state, the erasure/programming commands are not executed even if input. This prevents flash memory from being erroneously erased or programmed due to CPU runaway. The protection function can be temporarily disabled by setting the FMLBD bit in FLMCR1 to 1. To clear the lock bit, erase the specified block. Note that lock bits are unavailable in data flash areas. Rev. 1.00 Oct. 03, 2008 Page 225 of 962 REJ09B0465-0100 Section 7 ROM 7.7.3 PROM Programmer Protection/Boot Mode Protection PROM programmer protection/boot mode protection is enabled by writing the specified data to the user ROM area shown in the table 7.12. The protection function can be disabled by using a PROM programmer or on-board programmer to delete the entire user ROM area. Table 7.13 shows the specifications for PROM programmer protection and table 7.14 shows the specifications of protection in boot mode. Table 7.12 Address Range of the Protection Code in User ROM H'000004 H'000005 H'000006 H'000007 H'000010 H'000011 H'000012 H'000013 PROM programmer Boot mode Control code Not used Authentication ID code (56 bits) Table 7.13 Specifications for PROM Programmer Protection Control code* H'FF Protection State PROM programmer protection is disabled. Operation to be Carried Out Possible operations; reading/programming/ erasing by PROM programmer. Possible operations; programming/erasing by PROM programmer. However, reading is not possible. Other than above PROM programmer protection is enabled. Note: * Used together with control code for boot mode protection. Rev. 1.00 Oct. 03, 2008 Page 226 of 962 REJ09B0465-0100 Section 7 ROM Table 7.14 Specifications for Boot Mode Protection Control code* Protection State Other than above H'45 Protection is disabled. ID authentication protection 1*2 Operation in Serial Connection Entire blocks are deleted. Possible for reading/programming/erasing if the ID was authenticated. If the ID was not authenticated, entire blocks are deleted. Possible for reading/programming/erasing if the ID was authenticated. If the ID was not authenticated, authentication is performed again. If control code is H'52 and the special code (H'50, H'72, H'6F, H'74, H'65, H'63 and H'74) is written to the authentication ID bytes, processing for serial connections will not be accepted. H'52 ID authentication protection 2 ID authentication protection 2+*3 Note: 1. Used together with the control code for the PROM programmer. 2. Re-authentication can be performed up to 3 times in case of error in the ID code. 3. Once this setting has been made, serial connections are not accepted unless a PROM programmer is used to delete the setting. 7.8 Programmer Mode In programmer mode, flash memory areas can be programmed/erased using a PROM programmer via a socket adapter, just as a discrete flash memory can be. Use the PROM programmer that supports the Renesas Technology microcomputer device type with the on-chip 128-kbyte flash memory. Rev. 1.00 Oct. 03, 2008 Page 227 of 962 REJ09B0465-0100 Section 7 ROM 7.9 (1) Usage Notes Prohibited Instruction In EW0 mode, the following instruction cannot be used because it refers to the data in the flash memory area. * TRAP (2) Interrupts Table 7.15 shows interrupt handling in CPU reprogramming mode. Table 7.15 Interrupt Handling in CPU Reprogramming Mode When Watchdog Timer Reset, LVD Reset, Software Reset, or When Interrupt Request is Pin Reset, Interrupt Request is Received Generated Immediately after a reset is generated, a software command is forcibly terminated, and flash memory and LSI are reset. Because of the forced termination, it might be impossible to read correct values from the block or address for which the software command has been executed; execute erasure again after restarting and confirm that erasure is completed successfully. The watchdog timer does not stop even during command execution; initialize the timer periodically. Mode State EW0 During erasure command Interrupts can be handled if interrupt vectors are located During programming in the RAM. For details, see command section 4.2.7, Interrupt During lock-bit vector offset register programming command (VOFR). During blank checking command Rev. 1.00 Oct. 03, 2008 Page 228 of 962 REJ09B0465-0100 Section 7 ROM Mode State EW1 When Watchdog Timer Reset, LVD Reset, Software Reset, or When Interrupt Request is Pin Reset, Interrupt Request is Received Generated Immediately after a reset is generated, a software command is forcibly terminated, and flash memory and LSI are reset. Because of the forced termination, it might be impossible to read correct values from the block or address for which the software command has been executed; execute erasure again after restarting and confirm that erasure is completed successfully. Since the watchdog timer does not stop even during command execution, set the overflow time of the watchdog timer longer than the erasure/programming execution time. During erasure command Erasure is given priority, (erase-suspend function keeping the interrupt not used) request waiting. When erasure is completed, execution of the interrupt processing is started. During erasure command After the transition time to (erase-suspend function erase-suspend mode, used) erasure is suspended starting execution of the interrupt processing. When the interrupt processing is completed, setting the FMSPREQ bit in FLMCR2 to 0 resumes erasure. During programming command During lock-bit programming command During blank checking command A software command is given priority, keeping the interrupt request waiting. When the software command is completed, execution of the interrupt processing is started. (3) Method of Access When writing values to the protected bits indicated below, start by writing 0 to the bit and then write 1 to it or by writing 1 to the bit and then write 0 to it. Do not allow the generation of any interrupt or any access to other I/O registers between the two operations. For writing, always use the MOV instruction. (a) Bits that are set to 1 by writing 0 and then 1 consecutively * FLMCR1: FMLBD and FMCMDEN bits * FLMCR2: FMISPE and FMSPEN bits (b) Bits that are cleared to 0 by writing 1 and then 0 consecutively * DFPR: DFPR1 and DFPR0 bits Rev. 1.00 Oct. 03, 2008 Page 229 of 962 REJ09B0465-0100 Section 7 ROM The example below is of code for use when the FMCMDEN and FMLBD bits in FLMCR1 are to be changed from 0 to 1. MOV.B MOV.B BSET BSET MOV.B MOV.B @FLMCR1,R0L @FLMCR1,R0H #0,R0H #3,R0H R0L,@FLMCR1 R0H,@FLMCR1 :FLMCR1=H'04 :FLMCR1=H'04 :FLMCR1=H'04 :FLMCR1=H'04 :FLMCR1=H'04 :FLMCR1=H'0D R0L=H'04 R0L=H'04 R0L=H'04 R0L=H'04 R0L=H'04 R0L=H'04 R0H=H'xx R0H=H'04 R0H=H'05 R0H=H'0D R0H=H'0D R0H=H'0D (4) Reprogramming User ROM Area When it is necessary to reprogram the block containing the reprogramming-control program, use boot mode. This is because if the power supply voltage drops in EW0 mode while the block containing the reprogramming-control program is being reprogrammed, the reprogrammingcontrol program cannot be correctly reprogrammed, and this might disable further reprogramming of the flash memory. Only proceed with overwriting of the programming-control program after securing ample stabilization time for the power supply. (5) Program Do not program the already-programmed addresses. (6) LSI Mode Transition During software command execution, do not cause a transition to standby mode or sleep mode. (7) Reset during Execution of Software Command in Flash Memory Do not apply a pin reset, LVD reset, or watchdog timer reset during execution of the programming, lock-bit programming, blank-checking, and erasure commands. If applied, the currently executed command is forcibly terminated. In this case, execute the erasure command of the specified block again and confirm that erasure is completed successfully. Rev. 1.00 Oct. 03, 2008 Page 230 of 962 REJ09B0465-0100 Section 8 RAM Section 8 RAM The H8S/20103, H8S/20203, and H8S/20223 Group LSIs have an on-chip high-speed static RAM. The RAM is connected to the CPU via a 16-bit data bus, enabling the CPU to access both byte data and word data in one state. Product Classification Flash memory version 64 pins H8S/20103 H8S/20102 80 pins H8S/20223 H8S/20222 H8S/20203 H8S/20202 RAM Size 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes RAM Address H'FFDF80 to H'FFFF7F H'FFDF80 to H'FFFF7F H'FFDF80 to H'FFFF7F H'FFDF80 to H'FFFF7F H'FFDF80 to H'FFFF7F H'FFDF80 to H'FFFF7F Rev. 1.00 Oct. 03, 2008 Page 231 of 962 REJ09B0465-0100 Section 8 RAM Rev. 1.00 Oct. 03, 2008 Page 232 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller Section 9 Peripheral I/O Mapping Controller The peripheral function mapping controller (PMC) is composed of registers that are used to select the functions of multiplexed pins. The multiplexed pins are divided into two groups: group 1 and group 2. Group 1 consists of ports 1 to 3, 5, and 6, and group 2 consists of ports 8, 9*, and A. Tables 9.1 and 9.2 list the functions of the multiplexed pins in each group. Note: Port 9 is not available on the H8S/20103 group. Table 9.1 Group 1 Port 1 Port 2 Port 3 Port 5 Port 6 Pm5 Pm4 Pm3 Pm2 Pm1 Pm0 Initially mapped port Pm6 IRQ6 input IRQ5 input IRQ4 input IRQ3 input IRQ2 input IRQ1 input IRQ0 input Port 1 Multiplexed Pin Functions (Ports 1, 2, 3, 5, and 6) Pin Name Pm7 Function 1 IRQ7 input Function 2 Function 3 Function 4 Function 5 Function 6 TXD_2 output TXD_3 output SCL/SSI input/output RXD_2 input SCK3_2 input/output TRDOI_0 input RXD_3 input SCK3_3 input/output FTCI input* SDA/SCS input/output SSCK input/output SSO input/output FTIOD1 ADTRG2 input/output input FTIOC1 ADTRG1 input/output input FTIOB1 TRDOI_1 input/output input FTIOA1 TRAIO input/output input/output FTIOD0 TRAO output input/output FTIOC0 TRBO output input/output FTIOB0 TRGB input input/output FTIOA0 TREO output input/output Port 6 None TRCOI input* FTIOD TGIOB input/output* input/output TXD output RXD input SCK3 input/output Port 2 FTIOC TGIOA input/output* input/output FTIOB TCLKB input input/output* FTIOA TCLKA input input/output* Port 3 Port 5 [Legend] m = 1, 2, 3, 5 and 6 Note: The timer RC is not available on the H8S/20203 and H8S/20223 groups; therefore, the function cannot be selected for these groups. Rev. 1.00 Oct. 03, 2008 Page 233 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller Table 9.2 Group 2 Port 8 Port 9 Port A* 1 Multiplexed Pin Functions (Ports 8, 9, and A) Pin Name Pm7 Pm6 Pm5 Pm4 Pm3 Pm2 Pm1 Pm0 Function 1 Function 2 Function 3 Function 4 IRQ7 input IRQ6 input IRQ5 input IRQ4 input IRQ3 input IRQ2 input IRQ1 input IRQ0 input None None TXD output TREO output RXD input TRBO output Function 5*2 Function 6 FTIOD3 input/output FTIOC3 input/output FTIOB3 input/output FTIOA3 input/output TXD_3 output RXD_3 input SCK3_3 input/output None SCK3 TRAIO input/output input/output None TRGB input TRAO output FTIOD2 input/output Port 8 FTIOC2 input/output FTIOB2 input/output FTIOA2 input/output Port 9 Initially mapped port [Legend] Note: n = 8, 9, and A : Reserved 1. Port A is multiplexed with A/D converter analog input in the H8S/20223 group. Therefore, the multiplexed functions cannot be selected for the port. The PA3 to PA0 pins are multiplexed with A/D converter analog input in the H8S/20203 group. Therefore, the multiplexed functions cannot be selected for the port pins. 2. Function 5 cannot be selected for the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 234 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller 9.1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Register Descriptions Peripheral function mapping register write-protect register (PMCWPR) Port 1 peripheral function mapping register 1 (PMCR11) Port 1 peripheral function mapping register 2 (PMCR12) Port 1 peripheral function mapping register 3 (PMCR13) Port 1 peripheral function mapping register 4 (PMCR14) Port 2 peripheral function mapping register 1 (PMCR21) Port 2 peripheral function mapping register 2 (PMCR22) Port 2 peripheral function mapping register 3 (PMCR23) Port 2 peripheral function mapping register 4 (PMCR24) Port 3 peripheral function mapping register 1 (PMCR31) Port 3 peripheral function mapping register 2 (PMCR32) Port 3 peripheral function mapping register 3 (PMCR33) Port 3 peripheral function mapping register 4 (PMCR34) Port 5 peripheral function mapping register 1 (PMCR51) Port 5 peripheral function mapping register 2 (PMCR52) Port 5 peripheral function mapping register 3 (PMCR53) Port 5 peripheral function mapping register 4 (PMCR54) Port 6 peripheral function mapping register 1 (PMCR61) Port 6 peripheral function mapping register 2 (PMCR62) Port 6 peripheral function mapping register 3 (PMCR63) Port 6 peripheral function mapping register 4 (PMCR64) Port 8 peripheral function mapping register 3 (PMCR83) Port 8 peripheral function mapping register 4 (PMCR84) Port 9 peripheral function mapping register 1 (PMCR91)*1 Port 9 peripheral function mapping register 2 (PMCR92)*1 Port 9 peripheral function mapping register 3 (PMCR93)*1 Port 9 peripheral function mapping register 4 (PMCR94)*1 Port A peripheral function mapping register 3 (PMCRA3)*2 Port A peripheral function mapping register 4 (PMCRA4)*2 Notes: 1. PMCR91 to PMCR94 are not available on the H8S/20103 group. 2. PMCRA3 and PMCRA4 are not available on the H8S/20223 group. Rev. 1.00 Oct. 03, 2008 Page 235 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller 9.1.1 Peripheral Function Mapping Register Write-Protect Register (PMCWPR) Address: H'FF0065 Bit: b7 B0WI b6 PMCRWE 0 b5 b4 b3 b2 b1 b0 Value after reset: 1 0 0 0 0 0 0 Bit 7 Symbol B0WI Bit Name Bit 6 write protect Description 0: Writing to PMCRWE (bit 6 in this register) is enabled. 1: Writing to the PMCRWE bit is disabled. 0: Writing to PMCR is disabled. 1: Writing to PMCR is enabled. These bits are always read as 0. The write value should always be 0. R/W W 6 5 to 0 PMCRWE PMCR write enable Reserved R/W Note: A MOV instruction should be used to rewrite this register. * B0WI bit (Bit 6 write protect) Only when the write value to this bit is 0, PMCRWE (bit 6 in this register) can be modified. This bit is always read as 1. Rev. 1.00 Oct. 03, 2008 Page 236 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller 9.1.2 Port Group 1 Peripheral Function Mapping Registers 1 to 4 (PMCRn1 to PMCRn4 (n = 1, 2, 3, 5, and 6)) Port 1 Port 1 Peripheral Function Mapping Register 1 (PMCR11) Address: H'FF0040 Bit: b7 (1) (a) b6 b5 P11MD[2:0] b4 b3 b2 b1 P10MD[2:0] b0 Value after reset: 0 0 0 1 0 0 0 1 Bit 7 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ1 input (initial value) 010: RXD input (SCI3_1) 011: FTIOB input/output (timer RC)*2 100: TCLKB input (timer RG) 101: FTIOB0 input/output (timer RD_0) 110: TRGB input (timer RB) 111: Setting prohibited R/W R/W 6 to 4 P11MD[2:0] P11 function select 3 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ0 input (initial value) 010: SCK3 input/output (SCI3_1) 011: FTIOA input/output (timer RC)*2 100: TCLKA input (timer RG) 101: FTIOA0 input/output (timer RD_0) 110: TREO output (timer RE) 111: Setting prohibited R/W 2 to 0 P10MD[2:0] P10 function select*1 Notes: 1. For the H8S/20103 group, P10 is not provided and P10MD[2:0] are reserved. The initial value is B'001. The write value should be B'001. 2. This function cannot be selected for the H8S/20203 and H8S/20223 groups. Rev. 1.00 Oct. 03, 2008 Page 237 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (b) Port 1 Peripheral Function Mapping Register 2 (PMCR12) Address: H'FF0041 Bit: b7 b6 b5 P13MD[2:0] b4 b3 b2 b1 P12MD[2:0] b0 Value after reset: 0 0 0 1 0 0 0 1 Bit 7 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ3 input (initial value) 010: TRCOI input (timer RC)* 011: FTIOD input/output (timer RC)* 100: TGIOB input/output (timer RG) 101: FTIOD0 input/output (timer RD_0) 110: TRAO output (timer RA) 111: Setting prohibited R/W R/W 6 to 4 P13MD[2:0] P13 function select 3 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ2 input (initial value) 010: TXD output (SCI3_1) 011: FTIOC input/output (timer RC)* 100: TGIOA input/output (timer RG) 101: FTIOC0 input/output (timer RD_0) 110: TRBO output (timer RB) 111: Setting prohibited R/W 2 to 0 P12MD[2:0] P12 function select Note: * This function cannot be selected for the H8S/20203 and H8S/20223 groups. Rev. 1.00 Oct. 03, 2008 Page 238 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (c) Port 1 Peripheral Function Mapping Register 3 (PMCR13) Address: H'FF0042 Bit: b7 b6 b5 P15MD[2:0] b4 b3 b2 b1 P14MD[2:0] b0 Value after reset: 0 0 0 1 0 0 0 1 Bit 7 6 to 4 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. R/W R/W P15MD[2:0] P15 function 000: Setting prohibited select 001: IRQ5 input (initial value) 010: SCK3_2 input/output (SCI3_2) 011: SCK3_3 input/output (SCI3_3) 4 100: SSCK input/output* (SSU) 101: FTIOB1 input/output (timer RD_0) 110: TRDOI_1 input (timer RD_1)* 111: Setting prohibited 3 2 to 0 Reserved This bit is always read as 0. The write value should always be 0. R/W 2 P14MD[2:0] P14 function 000: Setting prohibited 1 select* 001: IRQ4 input (initial value) 010: TRDOI_0 input (timer RD_0) 011: FTCI input (timer RC)* 3 4 100: SSO input/output* (SSU) 101: FTIOA1 input/output (timer RD_0) 110: TRAIO input/output (timer RA) 111: Setting prohibited Notes: 1. For the H8S/20103 group, P14 is not provided and P14MD[2:0] are reserved. The initial value is B'001. The write value should be B'001. 2. This function cannot be selected for the H8S/20103 group. 3. This function cannot be selected for the H8S/20203 and H8S/20223 groups. 4. If the SSCK output pin or the SSO output pin is set, the NMOS open-drain output cannot be selected. Rev. 1.00 Oct. 03, 2008 Page 239 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (d) Port 1 Peripheral Function Mapping Register 4 (PMCR14) Address: H'FF0043 Bit: b7 b6 b5 P17MD[2:0] b4 b3 b2 b1 P16MD[2:0] b0 Value after reset: 0 0 0 1 0 0 0 1 Bit 7 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ7 input (initial value) 010: TXD_2 output (SCI3_2) 011: TXD_3 output (SCI3_3) 1 100: SSI/SCL input/output* (SSU/IIC2) R/W R/W 6 to 4 P17MD[2:0] P17 function select 101: FTIOD1 input/output (timer RD_0) 110: ADTRG2 input (AD_2) 111: Setting prohibited 3 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ6 input (initial value) 010: RXD_2 input (SCI3_2) 011: RXD_3 input (SCI3_3) 12 100: SCS/SDA input/output* * (SSU/IIC2) R/W 2 to 0 P16MD[2:0] P16 function select 101: FTIOC1 input/output (timer RD_0) 110: ADTRG1 input (AD_1) 111: Setting prohibited Note: 1. When the IICS/SSU is used as the IIC2 function, the SCL and SDA functions should be allocated to the P56 and P57 pins because SCL and SDA require buffers dedicated for 2 IIC input/output. When the ICSU is used for the SSU function except * , there is no restriction. 2. If the SCS output pin of the SSU is set, the NMOS open-drain output cannot be selected. Rev. 1.00 Oct. 03, 2008 Page 240 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (2) (a) Port 2 Port 2 Peripheral Function Mapping Register 1 (PMCR21) Address: H'FF0044 Bit: b7 b6 b5 P21MD[2:0] b4 b3 b2 b1 P20MD[2:0] b0 Value after reset: 0 0 1 0 0 0 1 0 Bit 7 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ1 input 010: RXD input (SCI3_1) (initial value) 011: FTIOB input/output (timer RC)* 100: TCLKB input (timer RG) 101: FTIOB0 input/output (timer RD_0) 110: TRGB input (timer RB) 111: Setting prohibited R/W R/W 6 to 4 P21MD[2:0] P21 function select 3 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ0 input 010: SCK3 input/output (SCI3_1) (initial value) 011: FTIOA input/output (timer RC)* 100: TCLKA input (timer RG) 101: FTIOA0 input/output (timer RD_0) 110: TREO output (timer RE) 111: Setting prohibited R/W 2 to 0 P20MD[2:0] P20 function select Note: * The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are reserved and the function cannot be selected for these groups. Rev. 1.00 Oct. 03, 2008 Page 241 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (b) Port 2 Peripheral Function Mapping Register 2 (PMCR22) Address: H'FF0043 Bit: b7 b6 b5 P23MD[2:0] b4 b3 b2 b1 P22MD[2:0] b0 Value after reset: 0 0 1 0 0 0 1 0 Bit 7 Bit Name Initial Value Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ3 input 010: TRCOI input (timer RC) (initial value) 011: FTIOD input/output (timer RC)* 100: TGIOB input/output (timer RG) 101: FTIOD0 input/output (timer RD_0) 110: TRAO output (timer RA) 111: Setting prohibited R/W R/W 6 to 4 P23MD[2:0] P23 function select 3 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ2 input 010: TXD output (SCI3_1) (initial value) 011: FTIOC input/output (timer RC)* 100: TGIOA input/output (timer RG) 101: FTIOC0 input/output (timer RD_0) 110: TRBO output (timer RB) 111: Setting prohibited R/W 2 to 0 P22MD[2:0] P22 function select Note: * The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are reserved and the function cannot be selected for these groups. Rev. 1.00 Oct. 03, 2008 Page 242 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (c) Port 2 Peripheral Function Mapping Register 3 (PMCR23) Address: H'FF0046 Bit: b7 b6 b5 P25MD[2:0] b4 b3 b2 b1 P24MD[2:0] b0 Value after reset: 0 0 1 0 0 0 1 0 Bit 7 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ5 input 010: SCK3_2 input/output (SCI3_2) (initial value) 011: SCK3_3 input/output (SCI3_3) 3 100: SSCK input/output* (SSU) R/W R/W 6 to 4 P25MD[2:0] P25 function select 101: FTIOB1 input/output (timer RD_0) 110: TRDOI_1 input (timer RD_1)* 111: Setting prohibited 3 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ4 input 010: TRDOI_0 input (timer RD_0) (initial value) 011: FTCI input (timer RC)* 2 3 100: SSO input/output* (SSU) 1 R/W 2 to 0 P24MD[2:0] P24 function select 101: FTIOA1 input/output (timer RD_0) 110: TRAIO input/output (timer RA) 111: Setting prohibited Notes: 1. This function cannot be selected for the H8S/20103 group. 2. This function cannot be selected for the H8S/20203 and H8S/20223 groups. 3. If the SSCK output pin or the SSO output pin is set, the NMOS open-drain output cannot be selected. Rev. 1.00 Oct. 03, 2008 Page 243 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (d) Port 2 Peripheral Function Mapping Register 4 (PMCR24) Address: H'FF0047 Bit: b7 b6 b5 P27MD[2:0] b4 b3 b2 b1 P26MD[2:0] b0 Value after reset: 0 0 1 0 0 0 1 0 Bit 7 6 to 4 Symbol P27MD[2:0] Bit Name Reserved P27 function select Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ7 input 010: TXD_2 output (SCI3_2) (initial value) 011: TXD_3 output (SCI3_3) 1 100: SSI/SCL input/output* (SSU/IIC2) R/W R/W 101: FTIOD1 input/output (timer RD_0) 110: ADTRG2 input (AD_2) 111: Setting prohibited 3 2 to 0 P26MD[2:0] Reserved P26 function select This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ6 input 010: RXD_2 input (SCI3_2) (initial value) 011: RXD_3 input (SCI3_3) 12 100: SCS/SDA input/output* * (SSU/IIC2) R/W 101: FTIOC1 input/output (timer RD_0) 110: ADTRG1 input (AD_1) 111: Setting prohibited Note: 1. When the IIC2/SSU is used as the IIC2 function, the SCL and SDA functions should be allocated to the P56 and P57 pins because SCL and SDA require buffers dedicated for 2 IIC input/output. When the ICSU is used for the SSU function except * , there is no restriction. 2. If the SCS output pin of the SSU is set, the NMOS open-drain output cannot be selected. Rev. 1.00 Oct. 03, 2008 Page 244 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (3) (a) Port 3 Port 3 Peripheral Function Mapping Register 1 (PMCR31) Address: H'FF0048 Bit: b7 b6 b5 P31MD[2:0] b4 b3 b2 b1 P32MD[2:0] b0 Value after reset: 0 0 1 1 0 0 1 1 Bit 7 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ1 input 010: RXD input (SCI3_1) 011: FTIOB input/output (timer RC)* (initial value) 100: TCLKB input (timer RG) 101: FTIOB0 input/output (timer RD_0) 110: TRGB input (timer RB) 111: Setting prohibited R/W R/W 6 to 4 P31MD[2:0] P31 function select 3 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ0 input 010: SCK3 input/output (SCI3_1) 011: FTIOA input/output (timer RC)* (initial value) 100: TCLKA input (timer RG) 101: FTIOA0 input/output (timer RD_0) 110: TREO output (timer RE) 111: Setting prohibited R/W 2 to 0 P30MD[2:0] P30 function select Note: * The timer RC is not available on the H8S/20203 and H8S/20223 groups. No function is selected in the initial state for these groups. Rev. 1.00 Oct. 03, 2008 Page 245 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (b) Port 3 Peripheral Function Mapping Register 2 (PMCR32) Address: H'FF0049 Bit: b7 b6 b5 P33MD[2:0] b4 b3 b2 b1 P32MD[2:0] b0 Value after reset: 0 0 1 1 0 0 1 1 Bit 7 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. R/W R/W 6 to 4 P33MD[2:0] P33 function 000: Setting prohibited select 001: IRQ3 input 010: TRCOI input (timer RC)* 011: FTIOD input/output (timer RC)* (initial value) 100: TGIOB input/output (timer RG) 101: FTIOD0 input/output (timer RD_0) 110: TRAO output (timer RA) 111: Setting prohibited 3 Reserved This bit is always read as 0. The write value should always be 0. R/W 2 to 0 P32MD[2:0] P32 function 000: Setting prohibited select 001: IRQ2 input 010: TXD output (SCI3_1) 011: FTIOC input/output (timer RC)* (initial value) 100: TGIOA input/output (timer RG) 101: FTIOC0 input/output (timer RD_0) 110: TRBO output (timer RB) 111: Setting prohibited Note: * The timer RC is not available on the H8S/20203 and H8S/20223 groups. No function is selected in the initial state for these groups. Rev. 1.00 Oct. 03, 2008 Page 246 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (c) Port 3 Peripheral Function Mapping Register 3 (PMCR33) Address: H'FF004A Bit: b7 b6 b5 P35MD[2:0] b4 b3 b2 b1 P34MD[2:0] b0 Value after reset: 0 0 1 1 0 0 1 1 Bit 7 6 to 4 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ5 input 010: SCK3_2 input/output (SCI3_2) 011: SCK3_3 input/output (SCI3_3) (initial value) 3 100: SSCK input/output* (SSU) R/W R/W P35MD[2:0] P35 function select 101: FTIOB1 input/output (timer RD_0) 110: TRDOI_1 input (timer RD_1)* 111: Setting prohibited 3 2 to 0 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ4 input 010: TRDOI_0 input (timer RD_0) 2 011: FTCI input (timer RC)* (initial value) 3 100: SSO input/output* (SSU) 1 R/W P34MD[2:0] P34 function select 101: FTIOA1 input/output (timer RD_0) 110: TRAIO input/output (timer RA) 111: Setting prohibited Notes: 1. This function cannot be selected for the H8S/20103 group. 2. The timer RC is not available on the H8S/20203 and H8S/20223 groups. No function is selected in the initial state for these groups. 3. If the SSCK output pin or the SSO output pin is set, the NMOS open-drain output cannot be selected. Rev. 1.00 Oct. 03, 2008 Page 247 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (d) Port 3 Peripheral Function Mapping Register 4 (PMCR34) Address: H'FF004B Bit: b7 b6 b5 P37MD[2:0] b4 b3 b2 b1 P36MD[2:0] b0 Value after reset: 0 0 1 1 0 0 1 1 Bit 7 6 to 4 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ7 input 010: TXD_2 output (SCI3_2) 011: TXD_3 output (SCI3_3) (initial value) 1 100: SSI/SCL input/output* (SSU/IIC2) R/W R/W P37MD[2:0] P37 function select 101: FTIOD1 input/output (timer RD_0) 110: ADTRG2 input (AD_2)* 111: Setting prohibited 3 2 to 0 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ6 input 010: RXD_2 input (SCI3_2) 011: RXD_3 input (SCI3_3) (initial value) 13 100: SCS/SDA input/output* * (SSU/IIC2) 2 R/W P36MD[2:0] P36 function select 101: FTIOC1 input/output (timer RD_0) 110: ADTRG1 input (AD_1) 111: Setting prohibited Notes: 1. When the IIC2/SSU is used as the IIC2 function, the SCL and SDA functions should be allocated to the P56 and P57 pins because SCL and SDA require buffers dedicated for 2 IIC input/output. When the ICSU is used for the SSU function except * , there is no restriction. 2. This function cannot be selected for the H8S/20103 and H8S/20203 groups. 3. If the SCS output pin of the SSU is set, the NMOS open-drain output cannot be selected. Rev. 1.00 Oct. 03, 2008 Page 248 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (4) (a) Port 5 Port 5 Peripheral Function Mapping Register 1 (PMCR51) Address: H'FF0050 Bit: b7 b6 b5 P51MD[2:0] b4 b3 b2 b1 P50MD[2:0] b0 Value after reset: 0 1 0 0 0 1 0 0 Bit 7 6 to 4 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ1 input 010: RXD input (SCI3_1) 011: FTIOB input/output (timer RC)* 100: TCLKB input (timer RG) (initial value) 101: FTIOB0 input/output (timer RD_0) 110: TRGB input (timer RB) 111: Setting prohibited R/W R/W P51MD[2:0] P51 function select 3 2 to 0 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ0 input 010: SCK3 input/output (SCI3_1) 011: FTIOA input/output (timer RC)* 100: TCLKA input (timer RG) (initial value) 101: FTIOA0 input/output (timer RD_0) 110: TREO output (timer RE) 111: Setting prohibited R/W P50MD[2:0] P50 function select Note: * The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are reserved and the function cannot be selected for these groups. Rev. 1.00 Oct. 03, 2008 Page 249 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (b) Port 5 Peripheral Function Mapping Register 2 (PMCR52) Address: H'FF0051 Bit: b7 b6 b5 P53MD[2:0] b4 b3 b2 b1 P52MD[2:0] b0 Value after reset: 0 1 0 0 0 1 0 0 Bit 7 Symbol Bit Name Reserved Description R/W This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ3 input 010: TRCOI input (timer RC)* 011: FTIOD input/output (timer RC)* 100: TGIOB input/output (timer RG) (initial value) 101: FTIOD0 input/output (timer RD_0) 110: TRAO output (timer RA) 111: Setting prohibited R/W 6 to 4 P53MD[2:0] P53 function select 3 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ2 input 010: TXD output (SCI3_1) 011: FTIOC input/output (timer RC)* 100: TGIOA input/output (timer RG) (initial value) 101: FTIOC0 input/output (timer RD_0) 110: TRBO output (timer RB) 111: Setting prohibited R/W 2 to 0 P52MD[2:0] P52 function select Note: * The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are reserved and the function cannot be selected for these groups. Rev. 1.00 Oct. 03, 2008 Page 250 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (c) Port 5 Peripheral Function Mapping Register 3 (PMCR53) Address: H'FF0052 Bit: b7 b6 b5 P55MD[2:0] b4 b3 b2 b1 P54MD[2:0] b0 Value after reset: 0 1 0 0 0 1 0 0 Bit 7 6 to 4 Symbol P55MD[2:0] Bit Name Reserved P55 function select Description R/W This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ5 input 010: SCK3_2 input/output (SCI3_2) 011: SCK3_3 input/output (SCI3_3) 3 100: SSCK input/output* (SSU) (initial value) R/W 101: FTIOB1 input/output (timer RD_0) 110: TRDOI_1 !Unexpected End of 1 Formulainput/output (timer RD_1)* 111: Setting prohibited 3 2 to 0 P54MD[2:0] Reserved P54 function select This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ4 input 010: TRDOI_0 input (timer RD_0) 011: FTCI input (timer RC)* 3 2 R/W 100: SSO input/output* (SSU) (initial value) 101: FTIOA1 input/output (timer RD_0) 110: TRAIO input/output (timer RA) 111: Setting prohibited Notes: 1. This function cannot be selected for the H8S/20103 group. 2. The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are reserved and the function cannot be selected for these groups. 3. If the NMOS open-drain output is selected for the SSCK output pin or the SSO output pin, use the PMC to allocate that pin from port 5 Rev. 1.00 Oct. 03, 2008 Page 251 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (d) Port 5 Peripheral Function Mapping Register 4 (PMCR54) Address: H'FF0053 Bit: b7 b6 b5 P57MD[2:0] b4 b3 b2 b1 P56MD[2:0] b0 Value after reset: 0 1 0 0 0 1 0 0 Bit 7 6 to 4 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ7 input 010: TXD_2 output (SCI3_2) 011: TXD_3 output (SCI3_3) 1 100: SSI/SCL input/output* (SSU/IIC2) (initial value) R/W R/W P57MD[2:0] P57 function select 101: FTIOD1 input/output (timer RD_0) 110: ADTRG2 input (AD_2) 111: Setting prohibited 3 2 to 0 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ6 input 010: RXD_2 input (SCI3_2) 011: RXD_3 input (SCI3_3) 12 100: SCS/SDA input/output* * (SSU/IIC2) (initial value) R/W P56MD[2:0] P56 function select 101: FTIOC1 input/output (timer RD_0) 110: ADTRG1 input (AD_1) 111: Setting prohibited Rev. 1.00 Oct. 03, 2008 Page 252 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller Note: 1. When the IIC2/SSU is used as the IIC2 function, the SCL and SDA functions should be allocated to the P56 and P57 pins because SCL and SDA require buffers dedicated for 2 IIC input/output. When the ICSU is used for the SSU function except * , there is no restriction. The P56 and P57 pins have different characteristics from other pins. When these pins are used as the SCL and SDA pins for the IIC2, they provide NMOS open drain output. When the P56 and P57 pins are used for other output functions, they provide NMOS push-pull output and characteristics of the high level output is different from that of the CMOS output. 2. If the NMOS open-drain output is selected for the SCS output pin, use the PMC to allocate that pin from port 5 Rev. 1.00 Oct. 03, 2008 Page 253 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (5) (a) Port 6 Port 6 Peripheral Function Mapping Register 1 (PMCR61) Address: H'FF0054 Bit: b7 b6 b5 P61MD[2:0] b4 b3 b2 b1 P60MD[2:0] b0 Value after reset: 0 1 0 1 0 1 0 1 Bit 7 6 to 4 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ1 input 010: RXD input (SCI3_1) 011: FTIOB input/output (timer RC)* 100: TCLKB input (timer RG) 101: FTIOB0 input/output (timer RD_0) (initial value) 110: TRGB input (timer RB) 111: Setting prohibited R/W R/W P61MD[2:0] P61 function select 3 2 to 0 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ0 input 010: SCK3 input/output (SCI3_1) 011: FTIOA input/output (timer RC)* 100: TCLKA input (timer RG) 101: FTIOA0 input/output (timer RD_0) (initial value) 110: TREO output (timer RE) 111: Setting prohibited R/W P60MD[2:0] P60 function select Note: * The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are reserved and the function cannot be selected for these groups. Rev. 1.00 Oct. 03, 2008 Page 254 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (b) Port 6 Peripheral Function Mapping Register 2 (PMCR62) Address: H'FF0055 Bit: b7 b6 b5 P63MD[2:0] b4 b3 b2 b1 P62MD[2:0] b0 Value after reset: 0 1 0 1 0 1 0 1 Bit 7 6 to 4 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ3 input 010: TRCOI input (timer RC)* 011: FTIOD input/output (timer RC)* 100: TGIOB input/output (timer RG) 101: FTIOD0 input/output (timer RD_0) (initial value) 110: TRAO output (timer RA) 111: Setting prohibited R/W R/W P63MD[2:0] P63 function select 3 2 to 0 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ2 input 010: TXD output (SCI3_1) 011: FTIOC input/output (timer RC)* 100: TGIOA input/output (timer RG) 101: FTIOC0 input/output (timer RD_0) (initial value) 110: TRBO output (timer RB) 111: Setting prohibited R/W P62MD[2:0] P62 function select Note: * The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are reserved and the function cannot be selected for these groups. Rev. 1.00 Oct. 03, 2008 Page 255 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (c) Port 6 Peripheral Function Mapping Register 3 (PMCR63) Address: H'FF0056 Bit: b7 b6 b5 P65MD[2:0] b4 b3 b2 b1 P64MD[2:0] b0 Value after reset: 0 1 0 1 0 1 0 1 Bit 7 6 to 4 Symbol P65MD[2:0] Bit Name Reserved P65 function select Description R/W This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ5 input 010: SCK3_2 input/output (SCI3_2) 011: SCK3_3 input/output (SCI3_3) 3 100: SSCK input/output* (SSU) R/W 101: FTIOB1 input/output (timer RD_0) (initial value) 110: TRDOI_1 input (timer RD_1)*1 111: Setting prohibited 3 2 to 0 P64MD[2:0] Reserved P64 function select This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ4 input 010: TRDOI_0 input (timer RD_0) 011: FTCI input (timer RC)* 3 2 R/W 100: SSO input/output* (SSU) 101: FTIOA1 input/output (timer RD_0) (initial value) 110: TRAIO input/output (timer RA) 111: Setting prohibited Notes: 1. This function cannot be selected for the H8S/20103 group. 2. The timer RC is not available on the H8S/20203 and H8S/20223 groups. These bits are reserved and the function cannot be selected for these groups. 3. If the SSCK output pin or the SSO output pin is set, the NMOS open-drain output cannot be selected. Rev. 1.00 Oct. 03, 2008 Page 256 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (d) Port 6 Peripheral Function Mapping Register 4 (PMCR64) Address: H'FF0057 Bit: b7 b6 b5 P67MD[2:0] b4 b3 b2 b1 P66MD[2:0] b0 Value after reset: 0 1 0 1 0 1 0 1 Bit 7 6 to 4 Symbol P67MD[2:0] Bit Name Reserved P67 function select Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ7 input 010: TXD_2 output (SCI3_2) 011: TXD_3 output (SCI3_3) 1 100: SSI/SCL input/output* (SSU/IIC2) R/W R/W 101: FTIOD1 input/output (timer RD_0) (initial value) 110: ADTRG2 input (AD_2) *2 111: Setting prohibited 3 2 to 0 P66MD[2:0] Reserved P66 function select This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ6 input 010: RXD_2 input (SCI3_2) 011: RXD_3 input (SCI3_3) 13 100: SCS/SDA input/output* * (SSU/IIC2) R/W 101: FTIOC1 input/output (timer RD_0) (initial value) 110: ADTRG1 input (AD_1) 111: Setting prohibited Notes: 1. When the IIC2/SSU is used as the IIC2 function, the SCL and SDA functions should be allocated to the P56 and P57 pins because SCL and SDA require buffers dedicated for 2 IIC input/output. When the ICSU is used for the SSU function except * , there is no restriction. 2. This function cannot be selected for the H8S/20103 and H8S/20203 groups. 3. If the SCS output pin of the SSU is set, the NMOS open-drain output cannot be selected. Rev. 1.00 Oct. 03, 2008 Page 257 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller 9.1.3 Port Group 2 Peripheral Function Mapping Registers 1 to 4 (PMCRn1 to PMCRn4 (n = 8, 9, and A) Port 8 Port 8 Peripheral Function Mapping Register 3 (PMCR83) Address: H'FF005E Bit: b7 (1) (a) b6 b5 P85MD[2:0] b4 b3 b2 b1 b0 Value after reset: 0 1 0 0 0 1 0 0 Bit 7 6 to 4 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. R/W R/W P85MD[2:0] P85 function 000: Setting prohibited select 001: IRQ5 input 010: Setting prohibited 011: SCK3 input/output (SCI3_1) 100: TRAIO input/output (timer RA) (initial value) 101: FTIOB3 input/output (timer RD_1)* 110: SCK3_3 input/output (SCI3_3) 111: Setting prohibited 3 2 to 0 Note: * Reserved Reserved This bit is always read as 0. The write value should always be 0. This bit is always read as B'100. The write value should always be B'100. This function cannot be selected for the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 258 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (b) Port 8 Peripheral Function Mapping Register 4 (PMCR84) Address: H'FF005F Bit: b7 b6 b5 P87MD[2:0] b4 b3 b2 b1 P86MD[2:0] b0 Value after reset: 0 1 0 0 0 1 0 0 Bit 7 6 to 4 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ7 input 010: Setting prohibited 011: TXD output (SCI3_1) 100: TREO output (timer RE) (initial value) 101: FTIOD3 input/output (timer RD_1)* 110: TXD_3 output (SCI3_3) 111: Setting prohibited R/W R/W P87MD[2:0] P87 function select 3 2 to 0 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ6 input 010: Setting prohibited 011: RXD input (SCI3_1) 100: TRBO output (timer RB) (initial value) 101: FTIOC3 input/output (timer RD_1)* 110: RXD_3 input (SCI3_3) 111: Setting prohibited R/W P86MD[2:0] P86 function select Note: * This function cannot be selected for the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 259 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (2) (a) Port 9 Port 9 Peripheral Function Mapping Register 1 (PMCR91) Address: H'FF0060 Bit: b7 b6 b5 P91MD[2:0] b4 b3 b2 b1 P90MD[2:0] b0 Value after reset: 0 1 0 1 0 1 0 1 Bit 7 6 to 4 Symbol P91MD[2:0] Bit Name Reserved P91 function select Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ1 input 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: FTIOB2 input/output (timer RD_1) (initial value) 110: Setting prohibited 111: Setting prohibited R/W R/W 3 2 to 0 P90MD[2:0] Reserved P90 function select This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ0 input 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: FTIOA2 input/output (timer RD_1) (initial value) 110: Setting prohibited 111: Setting prohibited R/W Note: PMCR91 is not available on the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 260 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (b) Port 9 Peripheral Function Mapping Register 2 (PMCR92) Address: H'FF0061 Bit: b7 b6 b5 P93MD[2:0] b4 b3 b2 b1 P92MD[2:0] b0 Value after reset: 0 1 0 1 0 1 0 1 Bit 7 6 to 4 Symbol Bit Name Reserved Description R/W This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ3 input 010: Setting prohibited 011: Setting prohibited 100: TRAO output (timer RA) 101: FTIOD2 input/output (timer RD_1) (initial value) 110: Setting prohibited 111: Setting prohibited R/W P93MD[2:0] P93 function select 3 2 to 0 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ2 input 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: FTIOC2 input/output (timer RD_1) (initial value) 110: Setting prohibited 111: Setting prohibited R/W P92MD[2:0] P92 function select Note: PMCR92 is not available on the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 261 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (c) Port 9 Peripheral Function Mapping Register 3 (PMCR93) Address: H'FF0062 Bit: b7 b6 b5 P95MD[2:0] b4 b3 b2 b1 P94MD[2:0] b0 Value after reset: 0 1 0 1 0 1 0 1 Bit 7 6 to 4 Symbol P95MD[2:0] Bit Name Reserved P95 function select Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ5 input 010: Setting prohibited 011: SCK3 input/output (SCI3_1) 100: TRAIO input/output (timer RA) 101: FTIOB3 input/output (timer RD_1) (initial value) 110: SCK3_3 input/output (SCI3_3) 111: Setting prohibited R/W R/W 3 2 to 0 P94MD[2:0] Reserved P94 function select This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ4 input 010: Setting prohibited 011: Setting prohibited 100: TRGB input (timer RB) 101: FTIOA3 input/output (timer RD_1) (initial value) 110: Setting prohibited 111: Setting prohibited R/W Note: PMCR93 is not available on the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 262 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (d) Port 9 Peripheral Function Mapping Register 4 (PMCR94) Address: H'FF0063 Bit: b7 b6 b5 P97MD[2:0] b4 b3 b2 b1 P96MD[2:0] b0 Value after reset: 0 1 0 1 0 1 0 1 Bit 7 6 to 4 Symbol Bit Name Reserved Description This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ7 input 010: Setting prohibited 011: TXD output (SCI3_1) 100: TREO output (timer RE) 101: FTIOD3 input/output (timer RD_1) (initial value) 110: TXD_3 output (SCI3_3) 111: Setting prohibited R/W R/W P97MD[2:0] P97 function select 3 2 to 0 Reserved This bit is always read as 0. The write value should always be 0. 000: Setting prohibited 001: IRQ6 input 010: Setting prohibited 011: RXD input (SCI3_1) 100: TRBO output (timer RB) 101: FTIOC3 input/output (timer RD_1) (initial value) 110: RXD_3 input (SCI3_3) 111: Setting prohibited R/W P96MD[2:0] P96 function select Note: PMCR94 is not available on the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 263 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (3) (a) Port A Port A Peripheral Function Mapping Register 3 (PMCRA3) Address: H'FF0066 Bit: b7 b6 b5 PA5MD[2:0] b4 b3 b2 b1 PA4MD[2:0] b0 Value after reset: 0 0 0 0 0 0 0 0 Bit 7 6 to 4 Symbol PA5MD[2:0] Bit Name Reserved PA5 function select Description This bit is always read as 0. The write value should always be 0. 000: No function selected (initial value) 001: IRQ5 input 010: Setting prohibited 011: SCK3 input/output (SCI3_1) 100: TRAIO input/output (timer RA) 101: FTIOB3 input/output (timer RD_1)* 110: SCK3_3 input/output (SCI3_3) 111: Setting prohibited R/W R/W 3 2 to 0 PA4MD[2:0] Reserved PA4 function select This bit is always read as 0. The write value should always be 0. 000: No function selected (initial value) 001: IRQ4 input 010: Setting prohibited 011: Setting prohibited 100: TRGB input (timer RB) 101: FTIOA3 input/output (timer RD_1)* 110: Setting prohibited 111: Setting prohibited R/W Note: PMCRA3 is not available on the H8S/20223 group. * This function cannot be selected for the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 264 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller (b) Port A Peripheral Function Mapping Register 4 (PMCRA4) Address: H'FF0067 Bit: b7 b6 b5 PA7MD[2:0] b4 b3 b2 b1 PA6MD[2:0] b0 Value after reset: 0 0 0 0 0 0 0 0 Bit 7 6 to 4 Symbol PA7MD[2:0] Bit Name Reserved PA7 function select Description This bit is always read as 0. The write value should always be 0. 000: No function selected (initial value) 001: IRQ7 input 010: Setting prohibited 011: TXD output (SCI3_1) 100: TREO output (timer RE) 101: FTIOD3 input/output (timer RD_1)* 110: TXD_3 output (SCI3_3) 111: Setting prohibited R/W R/W 3 2 to 0 PA6MD[2:0] Reserved PA6 function select This bit is always read as 0. The write value should always be 0. 000: No function selected (initial value) 001: IRQ6 input 010: Setting prohibited 011: RXD input (SCI3_1) 100: TRBO output (timer RB) 101: FTIOC3 input/output (timer RD_1)* 110: RXD_3 input (SCI3_3) 111: Setting prohibited R/W Note: PMCRA4 is not available on the H8S/20223 group. * This function cannot be selected for the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 265 of 962 REJ09B0465-0100 Section 9 Peripheral I/O Mapping Controller 9.2 9.2.1 Usage Notes Procedures for Setting Multiplexed Port Functions Use the following procedures to set a function for a multiplexed port. 1. 2. 3. 4. 5. Clear the relevant port mode register (PMR) bit to 0 to select the general input function. Set PMCWPR to enable writing to the relevant peripheral function mapping register (PMCR). Select a function using the peripheral function mapping register (PMCR). Set the PMCRWE bit in PMCWPR to 0 to disable writing to PMCR. Set the PMR bit to 1 as necessary to activate the selected multiplexed function. Notes on Setting PMC Registers 9.2.2 1. A function of a multiplexed port should be set when the relevant PMR bit is 0. If a function is set when PMR is 1, an unintended edge may be input for the input function or unintended pulses may be output for the output function. 2. Only the functions that can be selected by PMCR should be set. If the other functions are set, operation cannot be guaranteed. 3. The same function must not be assigned to multiple pins by the PMC. 4. Port A also has an analog input function for the A/D converter. When port A is used as analog input, the relevant bit in PMRA should be set to 0 to select general I/O. Rev. 1.00 Oct. 03, 2008 Page 266 of 962 REJ09B0465-0100 Section 10 I/O Ports Section 10 I/O Ports The H8S/20103 group has fifty-five general I/O ports, and the H8S/20223 and H8S/20203 groups each have sixty-nine general I/O ports. The general I/O ports are divided into three groups: the digital I/O ports that can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, the ports that can also be used as analog input ports, and the ports that can also be used as external oscillation pins. Although all the ports are set as general input ports immediately after a reset, the pin functions can be selected by setting the appropriate register. Pin functions of the digital I/O ports are selected by the peripheral function mapping controller (PMC). For details, see section 9, Peripheral I/O Mapping Controller. All pins of general I/O ports can be set as high-power ports. For the permissible total output current, see section 28, Electrical Characteristics. 10.1 Port 1 Figure 10.1 shows the pin configuration of port 1. H8S/20203 group H8S/20223 group H8S/20103 group P17/IRQ7 P16/IRQ6 P15/IRQ5 P14/IRQ4 P13/IRQ3 P12/IRQ2 P11/IRQ1 P10/IRQ0 Port 1 Port 1 P17/IRQ7 P16/IRQ6 P15/IRQ5 P13/IRQ3 P12/IRQ2 P11/IRQ1 Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.1 Port 1 Pin Configuration Rev. 1.00 Oct. 03, 2008 Page 267 of 962 REJ09B0465-0100 Section 10 I/O Ports Port 1 has the following registers. * * * * * Port mode register 1 (PMR1) Port control register 1 (PCR1) Port data register 1 (PDR1) Port pull-up control register 1 (PUCR1) Port drive control register 1 (PDVR1) Port Mode Register 1 (PMR1) 10.1.1 Address: H'FF0000 Bit: b7 PMR17 Value after reset: 0 b6 PMR16 0 b5 PMR15 0 b4 PMR14 0 b3 PMR13 0 b2 PMR12 0 b1 PMR11 0 b0 PMR10 0 Bit 7 6 5 4 3 2 1 0 Symbol PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 Bit Name Port 17 mode Port 16 mode Port 15 mode Port 14 mode Port 13 mode Port 12 mode Port 11 mode Port 10 mode Description 0: General I/O port 1: The function selected by the peripheral I/O mapping controller (PMC). R/W R/W R/W R/W PMR1 is a register that selects the function of the R/W multiplexed pins: general I/O function or the function R/W selected by the PMC. R/W In the H8S/20103 group, bits PMR14 and PMR10 are reserved. Only 0 should be written to these bits. R/W R/W Rev. 1.00 Oct. 03, 2008 Page 268 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.1.2 Port Control Register 1 (PCR1) Address: H'FFFFF0 Bit: b7 PCR17 b6 PCR16 0 b5 PCR15 0 b4 PCR14 0 b3 PCR13 0 b2 PCR12 0 b1 PCR11 0 b0 PCR10 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PCR17 PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 Bit Name Port 17 control Port 16 control Port 15 control Port 14 control Port 13 control Port 12 control Port 11 control Port 10 control Description 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port. 1: When the corresponding pin is designated as a general I/O port, the pin functions as an output port. R/W R/W R/W R/W R/W R/W When the corresponding pin is designated in PMR1 R/W as a general I/O pin, setting a PCR bit to 1 makes the corresponding pin an output port, while clearing R/W the bit to 0 makes the pin an input port. R/W In the H8S/20103 group, bits PCR14 and PCR10 are reserved. Only 0 should be written to these bits. Rev. 1.00 Oct. 03, 2008 Page 269 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.1.3 Port Data Register 1 (PDR1) Address: H'FFFFE0 Bit: b7 PDR17 b6 PDR16 0 b5 PDR15 0 b4 PDR14 0 b3 PDR13 0 b2 PDR12 0 b1 PDR11 0 b0 PDR10 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PDR17 PDR16 PDR15 PDR14 PDR13 PDR12 PDR11 PDR10 Bit Name Port 17 data Port 16 data Port 15 data Port 14 data Port 13 data Port 12 data Port 11 data Port 10 data Description 0: Low level 1: High level R/W R/W R/W PDR1 is a register that stores output data for port 1 R/W pins. When PCR1 bits are set to 1, the values R/W stored in PDR1 are output. R/W When PDR1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read. If PDR1 is read R/W while PCR1 bits are cleared to 0, the pin states are R/W read regardless of the value stored in PDR1. R/W Rev. 1.00 Oct. 03, 2008 Page 270 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.1.4 Port Pull-Up Control Register 1 (PUCR1) Address: H'FF0010 Bit: b7 PUCR17 b6 PUCR16 0 b5 PUCR15 0 b4 PUCR14 0 b3 PUCR13 0 b2 PUCR12 0 b1 PUCR11 0 b0 PUCR10 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 Bit Name Port 17 pull-up control Port 16 pull-up control Port 15 pull-up control Port 14 pull-up control Port 13 pull-up control Port 12 pull-up control Port 11 pull-up control Port 10 pull-up control Description 0: The pull-up MOS of corresponding pin is disabled. 1: The pull-up MOS of corresponding pin is enabled. R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 271 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.1.5 Port Drive Control Register 1 (PDVR1) Address: H'FF0030 Bit: b7 PDVR17 b6 PDVR16 0 b5 PDVR15 0 b4 PDVR14 0 b3 PDVR13 0 b2 PDVR12 0 b1 PDVR11 0 b0 PDVR10 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PDVR17 PDVR16 PDVR15 PDVR14 PDVR13 PDVR12 PDVR11 PDVR10 Bit Name Port 17 drive control Port 16 drive control Port 15 drive control Port 14 drive control Port 13 drive control Port 12 drive control Port 11 drive control Port 10 drive control Description 0: Normal output 1: High-current drive output R/W R/W PDVR1 is a register that controls drive capability of R/W the output pins in a bit unit. In the H8S/20103 group, bits PVDR14 and PVDR10 R/W are reserved. Only 0 should be written to these bits. R/W R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 272 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.2 Port 2 Figure 10.2 shows the pin configuration of port 2. H8S/20203 group H8S/20223 group H8S/20103 group P27/TXD_2 P26/RXD_2 P25/SCK3_2 P24/TRDOI P23 P22/TXD P21/RXD P20/SCK3 P27/TXD_2 P26/RXD_2 P25/SCK3_2 P24/TRDOI P23/TRCOI P22/TXD P21/RXD P20/SCK3 Port 2 Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.2 Port 2 Pin Configuration Port 2 has the following registers. * * * * * Port mode register 2 (PMR2) Port control register 2 (PCR2) Port data register 2 (PDR2) Port pull-up control register 2 (PUCR2) Port drive control register 2 (PDVR2) Port 2 Rev. 1.00 Oct. 03, 2008 Page 273 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.2.1 Port Mode Register 2 (PMR2) Address: H'FF0001 Bit: b7 PMR27 Value after reset: 0 b6 PMR26 0 b5 PMR25 0 b4 PMR24 0 b3 PMR23 0 b2 PMR22 0 b1 PMR21 0 b0 PMR20 0 Bit 7 6 5 4 3 2 1 0 Symbol PMR27 PMR26 PMR25 PMR24 PMR23 PMR22 PMR21 PMR20 Bit Name Port 27 mode Port 26 mode Port 25 mode Port 24 mode Port 23 mode Port 22 mode Port 21 mode Port 20 mode Description 0: General I/O port 1: The function selected by the peripheral function mapping controller (PMC). R/W R/W R/W R/W PMR2 is a register that selects the function of the R/W multiplexed pins: general I/O function or the function R/W selected by the PMC. R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 274 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.2.2 Port Control Register 2 (PCR2) Address: H'FFFFF1 Bit: b7 PCR27 Value after reset: 0 b6 PCR26 0 b5 PCR25 0 b4 PCR24 0 b3 PCR23 0 b2 PCR22 0 b1 PCR21 0 b0 PCR20 0 Bit 7 6 5 4 3 2 1 0 Symbol PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 Bit Name Port 27 control Port 26 control Port 25 control Port 24 control Port 23 control Port 22 control Port 21 control Port 20 control Description 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port. 1: When the corresponding pin is designated as a general I/O port, the pin functions as an output port. R/W R/W R/W R/W R/W R/W PCR2 is a register that selects inputs/outputs in bit R/W units for pins to be used as general I/O ports of port R/W 2. R/W * PCR27 bit to PCR20 bit (port 27 to 20 control) When the corresponding pin is designated in PMR2 as a general I/O pin, setting a PCR2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 1.00 Oct. 03, 2008 Page 275 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.2.3 Port Data Register 2 (PDR2) Address: H'FFFFE1 Bit: b7 PDR27 b6 PDR26 0 b5 PDR25 0 b4 PDR24 0 b3 PDR23 0 b2 PDR22 0 b1 PDR21 0 b0 PDR20 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PDR27 PDR26 PDR25 PDR24 PDR23 PDR22 PDR21 PDR20 Bit Name Port 27 data Port 26 data Port 25 data Port 24 data Port 23 data Port 22 data Port 21 data Port 20 data Description 0: Low level 1: High level R/W R/W R/W PDR2 is a register that stores output data for port 2 R/W pins. When PCR2 bits are set to 1, the values R/W stored in PDR2 are output. R/W When PDR2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read. If PDR2 is read R/W while PCR2 bits are cleared to 0, the pin states are R/W read regardless of the value stored in PDR2. R/W Rev. 1.00 Oct. 03, 2008 Page 276 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.2.4 Port Pull-Up Control Register 2 (PUCR2) Address: H'FF0011 Bit: b7 PUCR27 Value after reset: 0 b6 PUCR26 0 b5 PUCR25 0 b4 PUCR24 0 b3 PUCR23 0 b2 PUCR22 0 b1 PUCR21 0 b0 PUCR20 0 Bit 7 6 5 4 3 2 1 0 Symbol PUCR27 PUCR26 PUCR25 PUCR24 PUCR23 PUCR22 PUCR21 PUCR20 Bit Name Port 27 pull-up control Port 26 pull-up control Port 25 pull-up control Port 24 pull-up control Port 23 pull-up control Port 22 pull-up control Port 21 pull-up control Port 20 pull-up control Description 0: The pull-up MOS of corresponding pin is disabled. 1: The pull-up MOS of corresponding pin is enabled. PUCR2 is a register that controls the pull-up MOS in bit units of the pins set as the input ports. R/W R/W R/W R/W R/W R/W R/W R/W R/W * PUCR27 bit to PUCR20 bit (port 27 to 20 pull-up control) This function is valid only for the pin set as general input, and for the input pin with a function selected by the PMC. Rev. 1.00 Oct. 03, 2008 Page 277 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.2.5 Port Drive Control Register 2 (PDVR2) Address: H'FF0031 Bit: b7 PDVR27 Value after reset: 0 b6 PDVR26 0 b5 PDVR25 0 b4 PDVR24 0 b3 PDVR23 0 b2 PDVR22 0 b1 PDVR21 0 b0 PDVR20 0 Bit 7 6 5 4 3 2 1 0 Symbol PDVR27 PDVR26 PDVR25 PDVR24 PDVR23 PDVR22 PDVR21 PDVR20 Bit Name Port 27 drive control Port 26 drive control Port 25 drive control Port 24 drive control Port 23 drive control Port 22 drive control Port 21 drive control Port 20 drive control Description 0: Normal output 1: High-current drive output R/W R/W PDVR2 is a register that controls drive capability of R/W the output pins in a bit unit. R/W R/W R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 278 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.3 Port 3 Figure 10.3 shows the pin configuration of port 3. H8S/20203 group H8S/20223 group H8S/20103 group P37/TXD_3 P36/RXD_3 P35/SCK3_3 P34 P33 P32 P31 P30 P37/TXD_3 P36/RXD_3 P35/SCK3_3 P34/FTCI P33/FTIOD P32/FTIOC P31/FTIOB P30/FTIOA Port 3 Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.3 Port 3 Pin Configuration Port 3 has the following registers. * * * * * Port mode register 3 (PMR3) Port control register 3 (PCR3) Port data register 3 (PDR3) Port pull-up control register 3 (PUCR3) Port drive control register 3 (PDVR3) Port 3 Rev. 1.00 Oct. 03, 2008 Page 279 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.3.1 Port Mode Register 3 (PMR3) Address: H'FF0002 Bit: b7 PMR37 Value after reset: 0 b6 PMR36 0 b5 PMR35 0 b4 PMR34 0 b3 PMR33 0 b2 PMR32 0 b1 PMR31 0 b0 PMR30 0 Bit 7 6 5 4 3 2 1 0 Symbol PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR31 PMR30 Bit Name Port 37 mode Port 36 mode Port 35 mode Port 34 mode Port 33 mode Port 32 mode Port 31 mode Port 30 mode Description 0: General I/O port 1: The function selected by the peripheral function mapping controller (PMC). R/W R/W R/W R/W PMR3 is a register that selects the function of the R/W multiplexed pins: general I/O function or the function R/W selected by the PMC. R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 280 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.3.2 Port Control Register 3 (PCR3) Address: H'FFFFF2 Bit: b7 PCR37 b6 PCR36 0 b5 PCR35 0 b4 PCR34 0 b3 PCR33 0 b2 PCR32 0 b1 PCR31 0 b0 PCR30 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30 Bit Name Port 37 control Port 36 control Port 35 control Port 34 control Port 33 control Port 32 control Port 31 control Port 30 control Description 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port. 1: When the corresponding pin is designated as a general I/O port, the pin functions as an output port. R/W R/W R/W R/W R/W R/W PCR3 is a register that selects inputs/outputs in bit R/W units for pins to be used as general I/O ports of port R/W 3. R/W * PCR37 bit to PCR30 bit (port 37 to 30 control) When the corresponding pin is designated in PMR3 as a general I/O pin, setting a PCR3 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 1.00 Oct. 03, 2008 Page 281 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.3.3 Port Data Register 3 (PDR3) Address: H'FFFFE2 Bit: b7 PDR37 Value after reset: 0 b6 PDR36 0 b5 PDR35 0 b4 PDR34 0 b3 PDR33 0 b2 PDR32 0 b1 PDR31 0 b0 PDR30 0 Bit 7 6 5 4 3 2 1 0 Symbol PDR37 PDR36 PDR35 PDR34 PDR33 PDR32 PDR31 PDR30 Bit Name Port 37 data Port 36 data Port 35 data Port 34 data Port 33 data Port 32 data Port 31 data Port 30 data Description 0: Low level 1: High level R/W R/W R/W PDR3 is a register that stores output data for port 3 R/W pins. When PCR3 bits are set to 1, the values R/W stored in PDR3 are output. R/W When PDR3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read. If PDR3 is read R/W while PCR3 bits are cleared to 0, the pin states are R/W read regardless of the value stored in PDR3. R/W Rev. 1.00 Oct. 03, 2008 Page 282 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.3.4 Port Pull-Up Control Register 3 (PUCR3) Address: H'FF0012 Bit: b7 PUCR37 Value after reset: 0 b6 PUCR36 0 b5 PUCR35 0 b4 PUCR34 0 b3 PUCR33 0 b2 PUCR32 0 b1 PUCR31 0 b0 PUCR30 0 Bit 7 6 5 4 3 2 1 0 Symbol PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30 Bit Name Port 37 pull-up control Port 36 pull-up control Port 35 pull-up control Port 34 pull-up control Port 33 pull-up control Port 32 pull-up control Port 31 pull-up control Port 30 pull-up control Description 0: The pull-up MOS of corresponding pin is disabled. 1: The pull-up MOS of corresponding pin is enabled. PUCR3 is a register that controls the pull-up MOS in bit units of the pins set as the input ports. R/W R/W R/W R/W R/W R/W R/W R/W R/W * PUCR37 bit to PUCR30 bit (port 37 to 30 pull-up control) This function is valid only for the pin set as general input, and for the input pin with a function selected by the PMC. Rev. 1.00 Oct. 03, 2008 Page 283 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.3.5 Port Drive Control Register 3 (PDVR3) Address: H'FF0032 Bit: b7 PDVR37 b6 PDVR36 0 b5 PDVR35 0 b4 PDVR34 0 b3 PDVR33 0 b2 PDVR32 0 b1 PDVR31 0 b0 PDVR30 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PDVR37 PDVR36 PDVR35 PDVR34 PDVR33 PDVR32 PDVR31 PDVR30 Bit Name Port 37 drive control Port 36 drive control Port 35 drive control Port 34 drive control Port 33 drive control Port 32 drive control Port 31 drive control Port 30 drive control Description 0: Normal output 1: High-current drive output R/W R/W PDVR3 is a register that controls drive capability of R/W the output pins in a bit unit. R/W R/W R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 284 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.4 Port 5 Figure 10.4 shows the pin configuration of port 5. P57/SCL/SSI P56/SDA/SCS P55/SSCK P54/SSO P53/TGIOB P52/TGIOA P51/TCLKB P50/TCLKA Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.4 Port 5 Pin Configuration Port 5 has the following registers. * * * * * Port mode register 5 (PMR5) Port control register 5 (PCR5) Port data register 5 (PDR5) Port pull-up control register 5 (PUCR5) Port drive control register 5 (PDVR5) Port 5 Rev. 1.00 Oct. 03, 2008 Page 285 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.4.1 Port Mode Register 5 (PMR5) Address: H'FF0004 Bit: b7 PMR57 b6 PMR56 0 b5 PMR55 0 b4 PMR54 0 b3 PMR53 0 b2 PMR52 0 b1 PMR51 0 b0 PMR50 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PMR57 PMR56 PMR55 PMR54 PMR53 PMR52 PMR51 PMR50 Bit Name Port 57 mode Port 56 mode Port 55 mode Port 54 mode Port 53 mode Port 52 mode Port 51 mode Port 50 mode Description 0: General I/O port 1: The function selected by the peripheral function mapping controller (PMC). R/W R/W R/W R/W PMR5 is a register that selects the function of the R/W multiplexed pins: general I/O function or the function R/W selected by the PMC. R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 286 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.4.2 Port Control Register 5 (PCR5) Address: H'FFFFF4 Bit: b7 PCR57 b6 PCR56 0 b5 PCR55 0 b4 PCR54 0 b3 PCR53 0 b2 PCR52 0 b1 PCR51 0 b0 PCR50 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 Bit Name Port 57 control Port 56 control Port 55 control Port 54 control Port 53 control Port 52 control Port 51 control Port 50 control Description 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port. 1: When the corresponding pin is designated as a general I/O port, the pin functions as an output port. R/W R/W R/W R/W R/W R/W PCR5 is a register that selects inputs/outputs in bit R/W units for pins to be used as general I/O ports of port R/W 5. R/W * PCR57 bit to PCR50 bit (port 57 to 50 control) When the corresponding pin is designated in PMR5 as a general I/O pin, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 1.00 Oct. 03, 2008 Page 287 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.4.3 Port Data Register 5 (PDR5) Address: H'FFFFE4 Bit: b7 PDR57 b6 PDR56 0 b5 PDR55 0 b4 PDR54 0 b3 PDR53 0 b2 PDR52 0 b1 PDR51 0 b0 PDR50 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PDR57 PDR56 PDR55 PDR54 PDR53 PDR52 PDR51 PDR50 Bit Name Port 57 data Port 56 data Port 55 data Port 54 data Port 53 data Port 52 data Port 51 data Port 50 data Description 0: Low level 1: High level R/W R/W R/W PDR5 is a register that stores output data for port 5 R/W pins. When PCR5 bits are set to 1, the values R/W stored in PDR5 are output. R/W When PDR5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read. If PDR5 is read R/W while PCR5 bits are cleared to 0, the pin states are R/W read regardless of the value stored in PDR5. R/W Rev. 1.00 Oct. 03, 2008 Page 288 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.4.4 Port Pull-Up Control Register 5 (PUCR5) Address: H'FF0014 Bit: b7 -- Value after reset: 0 b6 -- 0 b5 PUCR55 0 b4 PUCR54 0 b3 PUCR53 0 b2 PUCR52 0 b1 PUCR51 0 b0 PUCR50 0 Bit 7 6 5 4 3 2 1 0 Symbol PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Bit Name Reserved Reserved Port 55 pull-up control Port 54 pull-up control Port 53 pull-up control Port 52 pull-up control Port 51 pull-up control Port 50 pull-up control Description R/W These bits are read as 0. The write value should be 0. 0: The pull-up MOS of corresponding pin is disabled. 1: The pull-up MOS of corresponding pin is enabled. PUCR5 is a register that controls the pull-up MOS in bit units of the pins set as the input ports. R/W R/W R/W R/W R/W R/W * PUCR55 bit to PUCR50 bit (port 55 to 50 pull-up control) This function is valid only for the pin set as general input, and for the input pin with a function selected by the PMC. Rev. 1.00 Oct. 03, 2008 Page 289 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.4.5 Port Drive Control Register 5 (PDVR5) Address: H'FF0034 Bit: b7 b6 b5 PDVR55 0 b4 PDVR54 0 b3 PDVR53 0 b2 PDVR52 0 b1 PDVR51 0 b0 PDVR50 0 Value after reset: 0 0 Bit 7 6 5 4 3 2 1 0 Symbol PDVR55 PDVR54 PDVR53 PDVR52 PDVR51 PDVR50 Bit Name Reserved Reserved Port 55 drive control Port 54 drive control Port 53 drive control Port 52 drive control Port 51 drive control Port 50 drive control Description This bit is read as 0. The write value should be 0. R/W R/W 0: Normal output 1: High-current drive output PDVR5 is a register that controls drive capability of R/W the output pins in a bit unit. When pins P56 and P57 are set as general output, R/W they function as NMOS push-pull output and thus drive capability cannot be selected for them. R/W R/W R/W Note: When pins P56 and P57 are set as general output, they function as NMOS push-pull output, and have characteristics different from those of other CMOS outputs. When set as SDA and SCL of IIC2, they function as NMOS open-drain output. For details, see section 28, Electrical Characteristics. Rev. 1.00 Oct. 03, 2008 Page 290 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.5 Port 6 Figure 10.5 shows the pin configuration of port 6. P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.5 Port 6 Pin Configuration Port 6 has the following registers. * * * * * Port mode register 6 (PMR6) Port control register 6 (PCR6) Port data register 6 (PDR6) Port pull-up control register 6 (PUCR6) Port drive control register 6 (PDVR6) Port 6 Rev. 1.00 Oct. 03, 2008 Page 291 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.5.1 Port Mode Register 6 (PMR6) Address: H'FF0005 Bit: b7 PMR67 b6 PMR66 0 b5 PMR65 0 b4 PMR64 0 b3 PMR63 0 b2 PMR62 0 b1 PMR61 0 b0 PMR60 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PMR67 PMR66 PMR65 PMR64 PMR63 PMR62 PMR61 PMR60 Bit Name Port 67 mode Port 66 mode Port 65 mode Port 64 mode Port 63 mode Port 62 mode Port 61 mode Port 60 mode Description 0: General I/O port 1: The function selected by the peripheral function mapping controller (PMC). R/W R/W R/W R/W PMR6 is a register that selects the function of the R/W multiplexed pins: general I/O function or the function R/W selected by the PMC. R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 292 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.5.2 Port Control Register 6 (PCR6) Address: H'FFFFF5 Bit: b7 PCR67 b6 PCR66 0 b5 PCR65 0 b4 PCR64 0 b3 PCR63 0 b2 PCR62 0 b1 PCR61 0 b0 PCR60 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 Bit Name Port 67 control Port 66 control Port 65 control Port 64 control Port 63 control Port 62 control Port 61 control Port 60 control Description 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port. 1: When the corresponding pin is designated as a general I/O port, the pin functions as an output port. R/W R/W R/W R/W R/W R/W PCR6 is a register that selects inputs/outputs in bit R/W units for pins to be used as general I/O ports of port R/W 6. R/W * PCR67 bit to PCR60 bit (port 67 to 60 control) When the corresponding pin is designated in PMR6 as a general I/O pin, setting a PCR6 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 1.00 Oct. 03, 2008 Page 293 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.5.3 Port Data Register 6 (PDR6) Address: H'FFFFE5 Bit: b7 PDR67 b6 PDR66 0 b5 PDR65 0 b4 PDR64 0 b3 PDR63 0 b2 PDR62 0 b1 PDR61 0 b0 PDR60 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PDR67 PDR66 PDR65 PDR64 PDR63 PDR62 PDR61 PDR60 Bit Name Port 67 data Port 66 data Port 65 data Port 64 data Port 63 data Port 62 data Port 61 data Port 60 data Description 0: Low level 1: High level R/W R/W R/W PDR6 is a register that stores output data for port 6 R/W pins. When PCR6 bits are set to 1, the values R/W stored in PDR6 are output. R/W When PDR6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read. If PDR6 is read R/W while PCR6 bits are cleared to 0, the pin states are R/W read regardless of the value stored in PDR6. R/W Rev. 1.00 Oct. 03, 2008 Page 294 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.5.4 Port Pull-Up Control Register 6 (PUCR6) Address: H'FF0015 Bit: b7 PUCR67 b6 PUCR66 0 b5 PUCR65 0 b4 PUCR64 0 b3 PUCR63 0 b2 PUCR62 0 b1 PUCR61 0 b0 PUCR60 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 Bit Name Port 67 pull-up control Port 66 pull-up control Port 65 pull-up control Port 64 pull-up control Port 63 pull-up control Port 62 pull-up control Port 61 pull-up control Port 60 pull-up control Description 0: The pull-up MOS of corresponding pin is disabled. 1: The pull-up MOS of corresponding pin is enabled. PUCR6 is a register that controls the pull-up MOS in bit units of the pins set as the input ports. R/W R/W R/W R/W R/W R/W R/W R/W R/W * PUCR67 bit to PUCR60 bit (port 67 to 60 pull-up control) This function is valid only for the pin set as general input, and for the input pin with a function selected by the PMC. Rev. 1.00 Oct. 03, 2008 Page 295 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.5.5 Port Drive Control Register 6 (PDVR6) Address: H'FF0035 Bit: b7 PDVR67 b6 PDVR66 0 b5 PDVR65 0 b4 PDVR64 0 b3 PDVR63 0 b2 PDVR62 0 b1 PDVR61 0 b0 PDVR60 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PDVR67 PDVR66 PDVR65 PDVR64 PDVR63 PDVR62 PDVR61 PDVR60 Bit Name Port 67 drive control Port 66 drive control Port 65 drive control Port 64 drive control Port 63 drive control Port 62 drive control Port 61 drive control Port 60 drive control Description 0: Normal output 1: High-current drive output R/W R/W PDVR6 is a register that controls drive capability of R/W the output pins in a bit unit. R/W R/W R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 296 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.6 Port 8 Figure 10.6 shows the pin configuration of port 8. P87/TREO P86/TRBO P85/TRAIO Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.6 Port 8 Pin Configuration Port 8 has the following registers. * * * * * Port mode register 8 (PMR8) Port control register 8 (PCR8) Port data register 8 (PDR8) Port pull-up control register 8 (PUCR8) Port drive control register 8 (PDVR8) Port 8 Rev. 1.00 Oct. 03, 2008 Page 297 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.6.1 Port Mode Register 8 (PMR8) Address: H'FF0005 Bit: b7 PMR67 b6 PMR66 0 b5 PMR65 0 b4 PMR64 0 b3 PMR63 0 b2 PMR62 0 b1 PMR61 0 b0 PMR60 0 Value after reset: 0 Bit 7 6 5 Symbol PMR87 PMR86 PMR85 Bit Name Port 87 mode Port 86 mode Port 85 mode Description 0: General I/O port 1: The function selected by the peripheral function mapping controller (PMC). PMR8 is a register that selects the function of the multiplexed pins: general I/O function or the function selected by the PMC. R/W R/W R/W R/W 4 to 0 Reserved These bits are read as 0. The write value should be 0. Rev. 1.00 Oct. 03, 2008 Page 298 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.6.2 Port Control Register 8 (PCR8) Address: H'FFFFF7 Bit: b7 PCR87 Value after reset: 0 b6 PCR86 0 b5 PCR85 0 b4 b3 b2 b1 b0 0 0 0 0 0 Bit 7 6 5 Symbol PCR87 PCR86 PCR85 Bit Name Port 87 control Port 86 control Port 85 control Description R/W 0: When the corresponding pin is designated as a R/W general I/O port, the pin functions as an input R/W port. R/W 1: When the corresponding pin is designated as a general I/O port, the pin functions as an output port. PCR8 is a register that selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. 4 to 0 Reserved These bits are read as 0. The write value should be 0. * PCR87 bit to PCR85 bit (port 87 to 85 control) When the corresponding pin is designated in PMR8 as a general I/O pin, setting a PCR8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 1.00 Oct. 03, 2008 Page 299 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.6.3 Port Data Register 8 (PDR8) Address: H'FFFFE7 Bit: b7 PDR87 b6 PDR86 0 b5 PDR85 0 b4 0 b3 0 b2 0 b1 0 b0 0 Value after reset: 0 Bit 7 6 5 Symbol PDR87 PDR86 PDR85 Bit Name Port 87 data Port 86 data Port 85 data Description 0: Low level 1: High level R/W R/W R/W PDR8 is a register that stores output data for port R/W 8 pins. When PCR8 bits are set to 1, the values stored in PDR8 are output. When PDR8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read. If PDR8 is read while PCR8 bits are cleared to 0, the pin states are read regardless of the value stored in PDR8. 4 to 0 Reserved These bits are read as 0. The write value should be 0. Rev. 1.00 Oct. 03, 2008 Page 300 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.6.4 Port Pull-Up Control Register 8 (PUCR8) Address: H'FF0017 Bit: b7 PUCR87 b6 PUCR86 0 b5 PUCR85 0 b4 b3 b2 b1 b0 Value after reset: 0 0 0 0 0 0 Bit 7 6 5 Symbol PUCR87 PUCR86 PUCR85 Bit Name Port 87 pull-up control Port 86 pull-up control Port 85 pull-up control Reserved Description 0: The pull-up MOS of corresponding pin is disabled. 1: The pull-up MOS of corresponding pin is enabled. R/W R/W R/W PUCR8 is a register that controls the pull-up MOS R/W in bit units of the pins set as the input ports. These bits are read as 0. The write value should be 0. 4 to 0 * PUCR87 bit to PUCR85 bit (port 87 to 85 pull-up control) This function is valid only for the pin set as general input, and for the input pin with a function selected by the PMC. Rev. 1.00 Oct. 03, 2008 Page 301 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.6.5 Port Drive Control Register 8 (PDVR8) Address: H'FF0037 Bit: b7 PDVR87 b6 PDVR86 0 b5 PDVR85 0 b4 0 b3 0 b2 0 b1 0 b0 0 Value after reset: 0 Bit 7 6 5 Symbol PDVR87 PDVR86 PDVR85 Bit Name Port 87 drive control Port 86 drive control Port 85 drive control Reserved Description 0: Normal output 1: High-current drive output R/W R/W PDVR8 is a register that controls drive capability of R/W the output pins in a bit unit. R/W These bits are read as 0. The write value should be 0. 4 to 0 10.6.6 Notes on Using Port 8 When using on-chip debugger function, set port 8 as general I/O port using PMR8. Rev. 1.00 Oct. 03, 2008 Page 302 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.7 Port 9 Figure 10.7 shows the pin configuration of port 9. Port 9 is not available on the H8S/20103 group. P97/FTIOD3 P96/FTIOC3 P95/FTIOB3 P94/FTIOA3 P93/FTIOD2 P92/FTIOC2 P91/FTIOB2 P90/FTIOA2 Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.7 Port 9 Pin Configuration Port 9 has the following registers. * * * * * Port mode register 9 (PMR9) Port control register 9 (PCR9) Port data register 9 (PDR9) Port pull-up control register 9 (PUCR9) Port drive control register 9 (PDVR9) Port 9 Rev. 1.00 Oct. 03, 2008 Page 303 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.7.1 Port Mode Register 9 (PMR9) Address: H'FF0008 Bit: b7 PMR97 b6 PMR96 0 b5 PMR95 0 b4 PMR94 0 b3 PMR93 0 b2 PMR92 0 b1 PMR91 0 b0 PMR90 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PMR97 PMR96 PMR95 PMR94 PMR93 PMR92 PMR91 PMR90 Bit Name Port 97 mode Port 96 mode Port 95 mode Port 94 mode Port 93 mode Port 92 mode Port 91 mode Port 90 mode Description 0: General I/O port 1: The function selected by the peripheral function mapping controller (PMC). R/W R/W R/W R/W PMR9 is a register that selects the function of the R/W multiplexed pins: general I/O function or the function R/W selected by the PMC. R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 304 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.7.2 Port Control Register 9 (PCR9) Address: H'FFFFF8 Bit: b7 PCR97 b6 PCR96 0 b5 PCR95 0 b4 PCR94 0 b3 PCR93 0 b2 PCR92 0 b1 PCR91 0 b0 PCR90 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PCR97 PCR96 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90 Bit Name Port 97 control Port 96 control Port 95 control Port 94 control Port 93 control Port 92 control Port 91 control Port 90 control Description 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port. 1: When the corresponding pin is designated as a general I/O port, the pin functions as an output port. R/W R/W R/W R/W R/W R/W PCR9 is a register that selects inputs/outputs in bit R/W units for pins to be used as general I/O ports of port R/W 9. R/W * PCR97 bit to PCR90 bit (port 97 to 90 control) When the corresponding pin is designated in PMR9 as a general I/O pin, setting a PCR9 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 1.00 Oct. 03, 2008 Page 305 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.7.3 Port Data Register 9 (PDR9) Address: H'FFFFE8 Bit: b7 PDR97 Value after reset: 0 b6 PDR96 0 b5 PDR95 0 b4 PDR94 0 b3 PDR93 0 b2 PDR92 0 b1 PDR91 0 b0 PDR90 0 Bit 7 6 5 4 3 2 1 0 Symbol PDR97 PDR96 PDR95 PDR94 PDR93 PDR92 PDR91 PDR90 Bit Name Port 97 data Port 96 data Port 95 data Port 94 data Port 93 data Port 92 data Port 91 data Port 90 data Description 0: Low level 1: High level R/W R/W R/W PDR9 is a register that stores output data for port 9 R/W pins. When PCR9 bits are set to 1, the values R/W stored in PDR9 are output. R/W When PDR9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read. If PDR9 is read R/W while PCR9 bits are cleared to 0, the pin states are R/W read regardless of the value stored in PDR9. R/W Rev. 1.00 Oct. 03, 2008 Page 306 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.7.4 Port Pull-Up Control Register 9 (PUCR9) Address: H'FF0018 Bit: b7 PUCR97 Value after reset: 0 b6 PUCR96 0 b5 PUCR95 0 b4 PUCR94 0 b3 PUCR93 0 b2 PUCR92 0 b1 PUCR91 0 b0 PUCR90 0 Bit 7 6 5 4 3 2 1 0 Symbol PUCR97 PUCR96 PUCR95 PUCR94 PUCR93 PUCR92 PUCR91 PUCR90 Bit Name Port 97 pull-up control Port 96 pull-up control Port 95 pull-up control Port 94 pull-up control Port 93 pull-up control Port 92 pull-up control Port 91 pull-up control Port 90 pull-up control Description 0: The pull-up MOS of corresponding pin is disabled. 1: The pull-up MOS of corresponding pin is enabled. PUCR9 is a register that controls the pull-up MOS in bit units of the pins set as the input ports. R/W R/W R/W R/W R/W R/W R/W R/W R/W * PUCR97 bit to PUCR90 bit (port 97 to 90 pull-up control) This function is valid only for the pin set as general input, and for the input pin with a function selected by the PMC. Rev. 1.00 Oct. 03, 2008 Page 307 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.7.5 Port Drive Control Register 9 (PDVR9) Address: H'FF0038 Bit: b7 PDVR97 Value after reset: 0 b6 PDVR96 0 b5 PDVR95 0 b4 PDVR94 0 b3 PDVR93 0 b2 PDVR92 0 b1 PDVR91 0 b0 PDVR90 0 Bit 7 6 5 4 3 2 1 0 Symbol PDVR97 PDVR96 PDVR95 PDVR94 PDVR93 PDVR92 PDVR91 PDVR90 Bit Name Port 97 drive control Port 96 drive control Port 95 drive control Port 94 drive control Port 93 drive control Port 92 drive control Port 91 drive control Port 90 drive control Description 0: Normal output 1: High-current drive output R/W R/W PDVR9 is a register that controls drive capability of R/W the output pins in a bit unit. R/W R/W R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 308 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.8 Port A Port A consists of general I/O pins that are also used as analog input pins for A/D converter unit 1 and unit 2 (only in the H8S/20223 group). The functions of PA4 to PA7 can be selected with the peripheral function mapping register of the PMC (except for the H8S/20223 group). For selection of functions by the peripheral function mapping controller, see section 9, Peripheral I/O Mapping Controller. Figure 10.8 shows the pin configuration of port A. H8S/20223 group H8S/20203 group H8S/20103 group PA7/AN3_2 PA6/AN2_2 PA5/AN1_2 PA4/AN0_2 PA3/AN11 PA2/AN10 PA1/AN9 PA0/AN8 PA7 PA6 PA5 PA4 PA3/AN11 PA2/AN10 PA1/AN9 PA0/AN8 PA7 PA6 PA5 PA4 Port A Port A Figure 10.8 Port A Pin Configuration Port A has the following registers. * * * * Port mode register A (PMRA) Port control register A (PCRA) Port data register A (PDRA) Port pull-up control register A (PUCRA) Rev. 1.00 Oct. 03, 2008 Page 309 of 962 REJ09B0465-0100 Port A Section 10 I/O Ports * H8S/20103 group 10.8.1 Port Mode Register A (PMRA) Address: H'FF0009 Bit: b7 PMRA7 Value after reset: 0 b6 PMRA6 0 b5 PMRA5 0 b4 PMRA4 0 b3 b2 PMRA2 0 b1 b0 0 0 0 Bit 7 6 5 4 Symbol PMRA7 PMRA6 PMRA5 PMRA4 Bit Name Port A7 mode Port A6 mode Port A5 mode Port A4 mode Description 0: General I/O port 1: The function selected by the peripheral function mapping controller (PMC). R/W R/W R/W R/W PMRA is a register that selects the function of the R/W port A multiplexed pins: general I/O function or the function selected by the PMC. PMRA also provides the bit to select the function of the PB0 pin. This bit is read as 0. The write value should be 0. 0: General I/O port 1: AN0 input pin These bits read as 0. The write value should be 0. R/W 3 2 1, 0 PMRA2 Reserved Port A2 mode Reserved * PMRA7 bit to PMRA4 bit (port A7 to A4 mode) These bits select the function of the multiplexed pins PA7 to PA4: general I/O function or the function selected by the PMC. * PMRA2 bit (port A2 mode) This bit selects general I/O function or the analog input function for PB0. Rev. 1.00 Oct. 03, 2008 Page 310 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.8.2 Port Control Register A (PCRA) Address: H'FFFFF9 Bit: b7 PCRA7 Value after reset: 0 b6 PCRA6 0 b5 PCRA5 0 b4 PCRA4 0 b3 0 b2 0 b1 0 b0 0 Bit 7 6 5 4 Symbol PCRA7 PCRA6 PCRA5 PCRA4 Bit Name Description R/W R/W R/W R/W R/W Port A7 control 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input Port A6 control port. Port A5 control 1: When the corresponding pin is designated as a Port A4 control general I/O port, the pin functions as an output port. PCRA is a register that selects inputs/outputs in bit units for pins to be used as general I/O ports of port A. 3 to 0 Reserved These bits are read as 0. The write value should be 0. * PCRA7 bit to PCRA4 bit (port A7 to A4 control) When the corresponding pin is designated in PMRA as a general I/O pin, setting a PCRA bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 1.00 Oct. 03, 2008 Page 311 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.8.3 Port Data Register A (PDRA) Address: H'FFFFE9 Bit: b7 PDRA7 Value after reset: 0 b6 PDRA6 0 b5 PDRA5 0 b4 PDRA4 0 b3 b2 b1 b0 0 0 0 0 Bit 7 6 5 4 Symbol PDRA7 PDRA6 PDRA5 PDRA4 Bit Name Port A7 data Port A6 data Port A5 data Port A4 data Description 0: Low level 1: High level R/W R/W R/W PDRA is a register that stores output data for port A R/W pins. When PCRA bits are set to 1, the values R/W stored in PDRA are output. When PDRA is read while PCRA bits are set to 1, the values stored in PDRA are read. If PDRA is read while PCRA bits are cleared to 0, the pin states are read regardless of the value stored in PDRA. 3 to 0 Reserved These bits are read as 0. The write value should be 0. Rev. 1.00 Oct. 03, 2008 Page 312 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.8.4 Port Pull-Up Control Register A (PUCRA) Address: H'FF0019 Bit: b7 PUCRA7 b6 PUCRA6 0 b5 PUCRA5 0 b4 PUCRA4 0 b3 0 b2 0 b1 0 b0 0 Value after reset: 0 Bit 7 6 5 4 Symbol PUCRA7* PUCRA6* PUCRA5* PUCRA4* Bit Name Description R/W R/W R/W R/W R/W Port A7 pull-up 0: The pull-up MOS of corresponding pin is disabled. control Port A6 pull-up 1: The pull-up MOS of corresponding pin is not enabled. control Port A5 pull-up PUCRA is a register that controls the pull-up MOS in bit units of the pins set as the input ports. control Port A4 pull-up control Reserved 3 to 0 Note: * These bits are read as 0. The write value should be 0. When PA7 to PA4 are set as the analog input pin, clear the corresponding bits to 0. * PUCRA7 bit to PUCRA4 bit (port A7 to A4 pull-up control) This function is valid only for the pin set as general input, and for the input pin with a function selected by the PMC. Rev. 1.00 Oct. 03, 2008 Page 313 of 962 REJ09B0465-0100 Section 10 I/O Ports * H8S/20203 group 10.8.5 Port Mode Register A (PMRA) Address: H'FF0009 Bit: b7 PMRA7 Value after reset: 0 b6 PMRA6 0 b5 PMRA5 0 b4 PMRA4 0 b3 b2 PMRA2 0 b1 b0 0 0 0 Bit 7 6 5 4 Symbol PMRA7 PMRA6 PMRA5 PMRA4 PMRA2 Bit Name Port A7 mode Port A6 mode Port A5 mode Port A4 mode Description 0: General I/O port 1: The function selected by the peripheral function mapping controller (PMC). PMRA is a register that selects the function of the port A multiplexed pins: general I/O function or the function selected by the PMC. This bit is read as 0. The write value should be 0. 0: General I/O port 1: AN0 input pin R/W R/W R/W R/W R/W R/W 3 2 1, 0 Reserved Port A2 mode Reserved These bits are read as 0. The write value should be 0. * PMRA7 bit to PMRA4 bit (port A7 to A4 mode) These bits select the function of the multiplexed pins PA7 to PA4: general I/O function or the function selected by the PMC. * PMRA2 bit (port A2 mode) This bit selects general I/O function or the analog input function for PB0. Rev. 1.00 Oct. 03, 2008 Page 314 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.8.6 Port Control Register A (PCRA) Address: H'FFFFF9 Bit: b7 PCRA7 b6 PCRA6 0 b5 PCRA5 0 b4 PCRA4 0 b3 PCRA3 0 b2 PCRA2 0 b1 PCRA1 0 b0 PCRA0 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PCRA7 PCRA6 PCRA5 PCRA4 PCRA3 PCRA2 PCRA1 PCRA0 Bit Name Description R/W R/W R/W R/W R/W R/W PCRA is a register that selects inputs/outputs in bit R/W Port A2 control units for pins to be used as general I/O ports of port Port A1 control A. R/W Port A0 control R/W Port A7 control 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input Port A6 control port. Port A5 control 1: When the corresponding pin is designated as a Port A4 control general I/O port, the pin functions as an output port. Port A3 control * PCRA7 bit to PCRA0 bit (port A7 to A0 control) When the corresponding pin is designated in PMRA as a general I/O pin, setting a PCRA bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 1.00 Oct. 03, 2008 Page 315 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.8.7 Port Data Register A (PDRA) Address: H'FFFFE9 Bit: b7 PDRA7 b6 PDRA6 0 b5 PDRA5 0 b4 PDRA4 0 b3 PDRA3 0 b2 PDRA2 0 b1 PDRA1 0 b0 PDRA0 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PDRA7 PDRA6 PDRA5 PDRA4 PDRA3 PDRA2 PDRA1 PDRA0 Bit Name Port A7 data Port A6 data Port A5 data Port A4 data Port A3 data Port A2 data Port A1 data Port A0 data Description 0: Low level 1: High level R/W R/W R/W PDRA is a register that stores output data for port A R/W pins. When PCRA bits are set to 1, the values R/W stored in PDRA are output. R/W When PDRA is read while PCRA bits are set to 1, R/W the values stored in PDRA are read. If PDRA is read while PCRA bits are cleared to 0, the pin R/W states are read regardless of the value stored in R/W PDRA. When pins PA3 to PA0 are set as analog input channels by ADCSR and ADCR of the A/D converter, however, the corresponding PCRA bits are always read as 1 even if they are cleared to 0. Rev. 1.00 Oct. 03, 2008 Page 316 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.8.8 Port Pull-Up Control Register A (PUCRA) Address: H'FF0019 Bit: b7 PUCRA7 b6 PUCRA6 0 b5 PUCRA5 0 b4 PUCRA4 0 b3 PUCRA3 0 b2 PUCRA2 0 b1 PUCRA1 0 b0 PUCRA0 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Note: Symbol PUCRA7* PUCRA6* PUCRA5* PUCRA4* PUCRA3* PUCRA2* PUCRA1* PUCRA0* * Bit Name Description R/W R/W R/W R/W R/W R/W R/W R/W R/W Port A7 pull-up 0: The pull-up MOS of corresponding pin is disabled. control Port A6 pull-up 1: The pull-up MOS of corresponding pin is enabled. control Port A5 pull-up PUCRA is a register that controls the pull-up MOS in bit units of the pins set as the input ports. control Port A4 pull-up control Port A3 pull-up control Port A2 pull-up control Port A1 pull-up control Port A0 pull-up control When PA7 to PA4 are set as the analog input pin, clear the corresponding bits to 0. * PUCRA7 bit to PUCRA0 bit (port A7 to A0 pull-up control) This function is valid only for the pin set as general input, and for the input pin with a function selected by the PMC. However, this setting is invalid for the analog input pin. Rev. 1.00 Oct. 03, 2008 Page 317 of 962 REJ09B0465-0100 Section 10 I/O Ports * H8S/20223 group 10.8.9 Port Mode Register A (PMRA) Address: H'FF0009 Bit: b7 b6 b5 b4 b3 PMRA3 0 b2 PMRA2 0 b1 b0 Value after reset: 0 0 0 0 0 0 Bit Symbol Bit Name Reserved Port A3 mode Port A2 mode Reserved Description These bits are read as 0. The write value should be 0. 0: General I/O port 1: AN0_2 input pin 0: General I/O port 1: AN0 input pin These bits are read as 0. The write value should be 0. R/W R/W R/W 7 to 4 3 2 1, 0 PMRA3 PMRA2 PMRA is a register that selects the function of the port A multiplexed pins: general I/O function or the function selected by the PMC. PMRA also provides the bit to select the function of the PB0 pin. * PMRA3 bit (port A3 mode) This bit selects general I/O function or the function selected by the PMC. * PMRA2 bit (port A2 mode) This bit selects general I/O function or the analog input function for PB0. Rev. 1.00 Oct. 03, 2008 Page 318 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.8.10 Port Control Register A (PCRA) Address: H'FFFFF9 Bit: b7 PCRA7 Value after reset: 0 b6 PCRA6 0 b5 PCRA5 0 b4 PCRA4 0 b3 PCRA3 0 b2 PCRA2 0 b1 PCRA1 0 b0 PCRA0 0 Bit 7 6 5 4 3 2 1 0 Symbol PCRA7 PCRA6 PCRA5 PCRA4 PCRA3 PCRA2 PCRA1 PCRA0 Bit Name Description R/W R/W R/W R/W R/W R/W PCRA is a register that selects inputs/outputs in bit R/W Port A2 control units for pins to be used as general I/O ports of port Port A1 control A. R/W Port A0 control R/W Port A7 control 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input Port A6 control port. Port A5 control 1: When the corresponding pin is designated as a Port A4 control general I/O port, the pin functions as an output port. Port A3 control * PCRA7 bit to PCRA0 bit (port A7 to A0 control) When the corresponding pin is designated in PMRA as a general I/O pin, setting a PCRA bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 1.00 Oct. 03, 2008 Page 319 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.8.11 Port Data Register A (PDRA) Address: H'FFFFE9 Bit: b7 PDRA7 Value after reset: 0 b6 PDRA6 0 b5 PDRA5 0 b4 PDRA4 0 b3 PDRA3 0 b2 PDRA2 0 b1 PDRA1 0 b0 PDRA0 0 Bit 7 6 5 4 3 2 1 0 Symbol PDRA7 PDRA6 PDRA5 PDRA4 PDRA3 PDRA2 PDRA1 PDRA0 Bit Name Port A7 data Port A6 data Port A5 data Port A4 data Port A3 data Port A2 data Port A1 data Port A0 data Description 0: Low level 1: High level R/W R/W R/W PDRA is a register that stores output data for port A R/W pins. When PCRA bits are set to 1, the values R/W stored in PDRA are output. R/W When PDRA is read while PCRA bits are set to 1, R/W the values stored in PDRA are read. If PDRA is read while PCRA bits are cleared to 0, the pin R/W states are read regardless of the value stored in R/W PDRA. Rev. 1.00 Oct. 03, 2008 Page 320 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.8.12 Port Pull-Up Control Register A (PUCRA) Address: H'FF0019 Bit: b7 PUCRA7 Value after reset: 0 b6 PUCRA6 0 b5 PUCRA5 0 b4 PUCRA4 0 b3 PUCRA3 0 b2 PUCRA2 0 b1 PUCRA1 0 b0 PUCRA0 0 Bit 7 6 5 4 3 2 1 0 Note: Symbol PUCRA7* PUCRA6* PUCRA5* PUCRA4* PUCRA3* PUCRA2* PUCRA1* PUCRA0* * Bit Name Description R/W R/W R/W R/W R/W R/W R/W R/W R/W Port A7 pull-up 0: The pull-up MOS of corresponding pin is disabled. control Port A6 pull-up 1: The pull-up MOS of corresponding pin is enabled. control Port A5 pull-up PUCRA is a register that controls the pull-up MOS in bit units of the pins set as the input ports. control Port A4 pull-up control Port A3 pull-up control Port A2 pull-up control Port A1 pull-up control Port A0 pull-up control When PA7 to PA0 are set as the analog input pin, clear the corresponding bits to 0. * PUCRA7 bit to PUCRA0 bit (port A7 to A0 pull-up control) This function is valid only for the pin set as general input, and for the input pin with a function selected by the PMC. However, this setting is invalid for the analog input pin. 10.8.13 Notes on Using Port A 1. The PA4 pin is initially set as general I/O pin. If using this pin as the AN0_2 analog input pin for the A/D converter unit 2 in the H8S/20223 group, set the PMRA3 bit in PMRA to 1. 2. In the H8S/20223 group, pins PA7 to PA4 can be used as the general I/O pins or analog input pins. If using these pins as the general I/O pins, do not set bits CH3 to CH0 in ADCSR_2 of the A/D converter unit 2 to set these pins as the analog input pins. Rev. 1.00 Oct. 03, 2008 Page 321 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.9 Port B Port B consists of general I/O pins that are also used as analog input pins for the A/D converter unit 1, or as analog output pins for the D/A converter. Figure 10.9 shows the pin configuration of port B. PB7/AN7/DA1 PB6/AN6/DA0 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 10.9 Port B Pin Configuration Port B has the following registers. * Port control register B (PCRB) * Port data register B (PDRB) * Port pull-up control register B (PUCRB) Rev. 1.00 Oct. 03, 2008 Page 322 of 962 REJ09B0465-0100 Port B Section 10 I/O Ports 10.9.1 Port Control Register B (PCRB) Address: H'FFFFFA Bit: b7 PCRB7 b6 PCRB6 0 b5 PCRB5 0 b4 PCRB4 0 b3 PCRB3 0 b2 PCRB2 0 b1 PCRB1 0 b0 PCRB0 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PCRB7 PCRB6 PCRB5 PCRB4 PCRB3 PCRB2 PCRB1 PCRB0 Bit Name Description R/W R/W R/W R/W R/W R/W PCRB is a register that selects inputs/outputs in bit R/W Port B2 control units for pins to be used as general I/O ports of port Port B1 control B. R/W Port B0 control R/W Port B7 control 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input Port B6 control port. Port B5 control 1: When the corresponding pin is designated as a Port B4 control general I/O port, the pin functions as an output port. Port B3 control * PCRB7 bit to PCRB0 bit (port B7 to B0 control) When the corresponding pin is designated in PMRB as a general I/O pin, setting a PCRB bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 1.00 Oct. 03, 2008 Page 323 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.9.2 Port Data Register B (PDRB) Address: H'FFFFEA Bit: b7 PDRB7 Value after reset: 0 b6 PDRB6 0 b5 PDRB5 0 b4 PDRB4 0 b3 PDRB3 0 b2 PDRB2 0 b1 PDRB1 0 b0 PDRB0 0 Bit 7 6 5 4 3 2 1 0 Symbol PDRB7 PDRB6 PDRB5 PDRB4 PDRB3 PDRB2 PDRB1 PDRB0 Bit Name Port B7 data Port B6 data Port B5 data Port B4 data Port B3 data Port B2 data Port B1 data Port B0 data Description 0: Low level 1: High level When the pins are set as analog input channels by ADCSR and ADCR of the A/D converter, however, the corresponding PCRB bits are always read as 1 even if they are cleared to 0. R/W R/W R/W R/W R/W R/W Similarly, when pins PB6 and PB7 are set as analog R/W output for the D/A converter by bit DAOE1 in DACR R/W of the D/A converter, the corresponding PCRB bits are always read as 1 even if they are cleared to 0. R/W PDRB is a register that stores output data for port B pins. Rev. 1.00 Oct. 03, 2008 Page 324 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.9.3 Port Pull-Up Control Register B (PUCRB) Address: H'FF001A Bit: b7 PUCRB7 b6 PUCRB6 0 b5 PUCRB5 0 b4 PUCRB4 0 b3 PUCRB3 0 b2 PUCRB2 0 b1 PUCRB1 0 b0 PUCRB0 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PUCRB7 PUCRB6 PUCRB5 PUCRB4 PUCRB3 PUCRB2 PUCRB1 PUCRB0 Bit Name Description R/W R/W R/W R/W R/W R/W R/W R/W R/W Port B7 pull-up 0: The pull-up MOS of corresponding pin is disabled. control Port B6 pull-up 1: The pull-up MOS of corresponding pin is enabled. control Port B5 pull-up PUCRB is a register that controls the pull-up MOS in bit units of the pins set as the input ports. control Port B4 pull-up control Port B3 pull-up control Port B2 pull-up control Port B1 pull-up control Port B0 pull-up control * PUCRB7 bit to PUCRB0 bit (port B7 to B0 pull-up control) This function is valid only for the pin set as general input, and for the input pin with a function selected by the PMC. However, this setting is invalid for the analog input pin. 10.9.4 Notes on Using Port B 1. The PB0 pin is initially set as general I/O pin. If using this pin as the analog input pin for the A/D converter, set the PMRA2 bit in PMRA to 1. 2. Pins PB7 and PB6 can be used as analog input pins for the A/D converter or analog output pins for the D/A converter. Do not set these pins as analog input pins and analog output pins at the same time. Rev. 1.00 Oct. 03, 2008 Page 325 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.10 Port J Port J consists of pins PJ1 and PJ0. These pins can also be used as external oscillation pins and clock output pin. Figure 10.10 shows the pin configuration of port J. In selection of the function of these multiplexed pins, the PMRJ register setting is given priority. Port J PJ1/OSC2/CLKOUT PJ0/OSC1 Figure 10.10 Port J Pin Configuration Port J has the following registers. * * * * Port mode register J (PMRJ) Port control register J (PCRJ) Port data register J (PDRJ) Port pull-up control register J (PUCRJ) Rev. 1.00 Oct. 03, 2008 Page 326 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.10.1 Port Mode Register J (PMRJ) Address: H'FF000C Bit: b7 b6 b5 b4 b3 b2 b1 PMRJ[1:0] 0 b0 Value after reset: 0 0 0 0 0 0 0 Bit Symbol Bit Name Reserved Description R/W 7 to 2 1, 0 These bits are read as 0. The write value should be 0. R/W PJ0 Pin PJ0 I/O OSC1 input* (external clock input) PJ0 I/O OSC1 PMRJ1 0 0 PMRJ0 0 1 PJ1 Pin PJ1 I/O PJ1 I/O PMRJ[1:0] Port J[1:0] mode Selects PJ1 and PJ0 pin functions. 1 1 Note: * 0 1 CLKOUT OSC2 Set the PMRJ1 and PMRJ0 bits to 01 to input the external clock on the OSC1 pin. Do not apply the external clock to the OSC1 pin while the PMRJ1 and PMRJ0 bits are set to 11. Rev. 1.00 Oct. 03, 2008 Page 327 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.10.2 Port Control Register J (PCRJ) Address: H'FFFFFC Bit: b7 b6 0 b5 0 b4 0 b3 0 b2 0 b1 PCRJ1 0 b0 PCRJ0 0 Value after reset: 0 Bit Symbol Bit Name Reserved Port J1 control Port J0 control Description These bits are read as 0. The write value should be 0. 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port. 1: When the corresponding pin is designated as a general I/O port, the pin functions as an output port. PCRJ is a register that selects inputs/outputs in bit units for pins to be used as general I/O ports of port J. R/W R/W R/W 7 to 2 1 0 PCRJ1 PCRJ0 * PCRJ1 bit and PCRJ0 bit (port J1 and J0 control) When the general I/O port function is selected by PMRJ, setting a PCRJ bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Rev. 1.00 Oct. 03, 2008 Page 328 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.10.3 Port Data Register J (PDRJ) Address: H'FFFFEC Bit: b7 Value after reset: 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 PDRJ1 0 b0 PDRJ0 0 Bit Symbol Bit Name Reserved Port J1 data Port J0 data Description R/W 7 to 2 1 0 PDRJ1 PDRJ0 These bits are read as 0. The write value should be 0. 0: Low level 1: High level PDRJ is a register that stores output data for port J pins. When PCRJ bits are set to 1, the values stored in PDRJ are output. When PDRJ is read while PCRJ bits are set to 1, the values stored in PDRJ are read. If PDRJ is read while PCRJ bits are cleared to 0, the pin states are read regardless of the value stored in PDRJ. R/W R/W Rev. 1.00 Oct. 03, 2008 Page 329 of 962 REJ09B0465-0100 Section 10 I/O Ports 10.10.4 Port Pull-Up Control Register J (PUCRJ) Address: H'FF001C Bit: b7 b6 0 b5 0 b4 0 b3 0 b2 0 b1 PUCRJ1 0 b0 PUCRJ0 0 Value after reset: 0 Bit Symbol Bit Name Reserved Port J1 pull-up control Port J0 pull-up control Description These bits are read as 0. The write value should be 0. 0: The pull-up MOS of corresponding pin is disabled. 1: The pull-up MOS of corresponding pin is enabled. PUCRJ is a register that controls the pull-up MOS in bit units of the pins set as the input ports. R/W R/W R/W 7 to 2 1 0 PUCRJ1 PUCRJ0 * PUCRJ1 bit and PUCRJ0 bit (port J1 and J0 pull-up control) This function is valid only for the pin set as general input, and for the input pin with a function selected by the PMC. Rev. 1.00 Oct. 03, 2008 Page 330 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Section 11 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software to transfer data. Figure 11.1 shows a block diagram of the DTC. 11.1 Features * Transfer possible over any number of channels * Three transfer modes Normal mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2. From 1 to 65,536 transfers can be specified. Repeat mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2. Once the specified number of transfers (1 to 256) has ended, the initial state is restored, and transfer is repeated. Block transfer mode One operation transfers specified one block of data. The block size is 1 to 256 bytes or words. From 1 to 65,536 transfers can be specified. Either the transfer source or the transfer destination is designated as a block area. * One activation source can trigger a number of data transfers (chain transfer) * Direct specification of 16-Mbyte address space possible * Activation by software is possible. * Transfer can be set in byte or word units. * A CPU interrupt can be requested for the interrupt that activated the DTC. * Module standby mode can be set. Rev. 1.00 Oct. 03, 2008 Page 331 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) The DTC's register information is stored in the on-chip RAM. A 32-bit bus connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC register information. Internal address bus Interrupt controller DTC On-chip RAM CPU interrupt request DTC activation request Figure 11.1 Block Diagram of DTC Rev. 1.00 Oct. 03, 2008 Page 332 of 962 REJ09B0465-0100 MRA MRB CRA CRB DAR SAR Interrupt request Internal data bus Register information Control logic DTCERA to DTCERH DTVECR Section 11 Data Transfer Controller (DTC) 11.2 Register Descriptions DTC has the following registers. * * * * * * DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB) The above six registers cannot be directly accessed from the CPU. When the DTC activation source is generated, the DTC reads from a set of register information that is stored in an on-chip RAM to the corresponding DTC register information and transfers data. After the data transfer, it writes a set of updated register information back to the RAM. * * * * * * * * * DTC enable register A (DTCERA) DTC enable register B (DTCERB) DTC enable register C (DTCERC) DTC enable register D (DTCERD) DTC enable register E (DTCERE) DTC enable register F (DTCERF) DTC enable register G (DTCERG) DTC enable register H (DTCERH) DTC vector register (DTVECR) Rev. 1.00 Oct. 03, 2008 Page 333 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.2.1 DTC Mode Register A (MRA) Address: Bit: b7 SM[1:0] b6 b5 DM[1:0] b4 b3 MD[1:0] b2 b1 DTC b0 Sz Value after reset: Bit 7 6 Symbol SM[1:0] Bit Name Description R/W Source 0x: SAR is fixed address mode 10: SAR is incremented after a transfer 1 and 0 (by +1 when Sz = 0; by +2 when Sz = 1) 11: SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 5 4 DM[1:0] Destination 0x: DAR is fixed address mode 10: DAR is incremented after a transfer 1 and 0 (by +1 when Sz = 0; by +2 when Sz = 1) 11: DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 3 2 MD[1:0] DTC mode 1 and 0 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 0 DTC Sz DTC transfer mode select DTC data transfer size 0: Destination side is repeat area or block area. 1: Source side is repeat area or block area. 0: Byte-size transfer 1: Word-size transfer Legend: x: Don't care Rev. 1.00 Oct. 03, 2008 Page 334 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) MRA selects the DTC operating mode. * SM[1:0] bits (source address mode 1 and 0) These bits specify an SAR operation after data transfer. * DM[1:0] bits (destination address mode 1 and 0) These bits specify a DAR operation after data transfer. * MD[1:0] bits (DTC mode 1 and 0) These bits specify the DTC transfer mode. * DTS bit (DTC transfer mode select) This bit specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. * Sz bit (DTC data transfer size) This bit specifies the size of data to be transferred. Rev. 1.00 Oct. 03, 2008 Page 335 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.2.2 DTC Mode Register B (MRB) b7 CHNE b6 DISEL b5 CHNS b4 b3 b2 b1 b0 Address: Bit: Value after reset: Bit 7 Symbol CHNE Bit Name DTC chain transfer enable DTC interrupt select Description 0: Disables chain transfer. 1: Enables chain transfer. 0: Generates an interrupt request to the CPU only when the specified data transfer has been completed. 1: Generates an interrupt request to the CPU every time after the DTC transfer has been completed. R/W 6 DISEL 5 CHNS Chain transfer 0: Performs chain transfer consecutively. select 1: Performs chain transfer only when transfer counter =0 Reserved These bits have no effect on DTC operation. The write value should be 0. 4 to 0 MRB selects the DTC operating mode. * CHNE bit (DTC chain transfer enable) When this bit is set to 1, a chain transfer will be performed. For details, see section 11.5.4, Chain Transfer. In the data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the activation source flag, and clearing of DTCER are not performed. * DISEL bit (DTC interrupt select) When this bit is set to 1, a CPU interrupt request is generated every time the DTC transfer is performed (the interrupt source flags as the activation source are not cleared to 0 by the DTC). When this bit is cleared to 0, a CPU interrupt request is generated at the time when the specified number of data transfers ends (the interrupt source flags as the activation source is cleared to 0 by the DTC). Rev. 1.00 Oct. 03, 2008 Page 336 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.2.3 DTC Source Address Register (SAR) Address: Bit: b23 bit23 Value after reset: Bit: b15 bit15 Value after reset: Bit: b7 bit7 Value after reset: b22 bit22 b14 bit14 b6 bit6 b21 bit21 b13 bit13 b5 bit5 b20 bit20 b12 bit12 b4 bit4 b19 bit19 b11 bit11 b3 bit3 b18 bit18 b10 bit10 b2 bit2 b17 bit17 b9 bit9 b1 bit1 b16 bit16 b8 bit8 b0 bit0 SAR designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 11.2.4 DTC Destination Address Register (DAR) b23 bit23 Value after reset: Bit: b15 bit15 Value after reset: Bit: b7 bit7 Value after reset: b22 bit22 b14 bit14 b6 bit6 b21 bit21 b13 bit13 b5 bit5 b20 bit20 b12 bit12 b4 bit4 b19 bit19 b11 bit11 b3 bit3 b18 bit18 b10 bit10 b2 bit2 b17 bit17 b9 bit9 b1 bit1 b16 bit16 b8 bit8 b0 bit0 Address: Bit: DAR designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. Rev. 1.00 Oct. 03, 2008 Page 337 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.2.5 DTC Transfer Count Register A (CRA) Address: Bit: b15 bit15 Value after reset: Bit: b7 bit7 Value after reset: b14 bit14 b6 bit6 b13 bit13 b5 bit5 b12 bit12 b4 bit4 b11 bit11 b3 bit3 b10 bit10 b2 bit2 b9 bit9 b1 bit1 b8 bit8 b0 bit0 CRA designates the number of times that data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). In repeat mode, CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). In block transfer mode, CRAH holds the size of blocks while CRAL functions as a block-size counter. CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count value reaches H'00. 11.2.6 DTC Transfer Count Register B (CRB) Address: Bit: b15 bit15 Value after reset: Bit: b7 bit7 Value after reset: b14 bit14 b6 bit6 b13 bit13 b5 bit5 b12 bit12 b4 bit4 b11 bit11 b3 bit3 b10 bit10 b2 bit2 b9 bit9 b1 bit1 b8 bit8 b0 bit0 CRB is a 16-bit register that designates the number of times block data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. The CRB is not available in normal and repeat modes. Rev. 1.00 Oct. 03, 2008 Page 338 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) Address: H'FF0534 to H'FF053B Bit: b7 DTCEn7 Value after reset: b6 DTCEn6 b5 DTCEn5 b4 DTCEn4 b3 DTCEn3 b2 DTCEn2 b1 DTCEn1 b0 DTCEn0 Bit 7 6 5 4 3 2 1 0 Symbol DTCEn7 DTCEn6 DTCEn5 DTCEn4 DTCEn3 DTCEn2 DTCEn1 DTCEn0 Bit Name Description R/W R/W R/W R/W R/W R/W R/W R/W R/W DTC activation 0: A relevant interrupt source is not selected as a enable DTC activation source. 1: A relevant interrupt source is selected as a DTC activation source. [Setting condition] * Setting this bit to 1 specifies a relevant interrupt source to a DTC activation source. When the DISEL bit in MRB is set to 1 and the data transfer has ended. When the specified number of data transfers has ended. [Clearing conditions] * * These bits are not automatically cleared when the DISEL bit is 0 and the specified number of data transfers has not ended. * When 0 is written to DTCE after reading DTCE = 1. Notes: n = A to H DTCE bits with no corresponding interrupt are reserved. The write value should always be 0. DTCER, which is comprised of DTCERA to DTCERH, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 11.1. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Rev. 1.00 Oct. 03, 2008 Page 339 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Table 11.1 Correspondence between Interrupt Sources and DTCER Bit Register 7 6 IRQ1 5 IRQ2 4 IRQ3 3 IRQ4 2 IRQ5 ELC2FP 2 1 IRQ6 0 IRQ7 DTCERA IRQ0 DTCERB IADEND_1 IADCMP_1 IADEND_2 IADCMP_2 ELC1FP 1 1 * * DTCERC SCI3_2_RXI SCI3_2_TXI SCI3_3_RXI SCI3_3_TXI DTCERD IIC2/SSU_ IIC2/SSU_ RXI TXI ITCMA* SCI3_1_RXI SCI3_1_TXI 2 2 ITCMB* ITCMC* ITCMD* 2 DTCERE ITDMA0_0 ITDMB0_0 ITDMC0_0 ITDMD0_0 ITDMA0_1 ITDMB0_1 ITDMC0_1 ITDMD0_1 DTCERF ITDMA1_2 ITDMB1_2 ITDMC1_2 ITDMD1_2 ITDMA1_3 ITDMB1_3 ITDMC1_3 ITDMD1_3 3 3 3 3 3 3 3 3 * * * * * * * * DTCERG DTCERH ITESC ITEMI ITGMA ITEHR ITGMB ITEDY ITEWK Notes: : 1. 2. 3. Reserved bit Supported only in the H8S/20223 group. Supported only in the H8S/20103 group. Not supported in the H8S/20103 group. Rev. 1.00 Oct. 03, 2008 Page 340 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.2.8 DTC Vector Register (DTVECR) H'FF053D b7 SWDTE b6 DTVEC6 0 b5 DTVEC5 0 b4 DTVEC4 0 b3 DTVEC3 0 b2 DTVEC2 0 b1 DTVEC1 0 b0 DTVEC0 0 Address: Bit: Value after reset: 0 Bit 7 Symbol SWDTE Bit Name Description R/W R/W DTC software 0: Disables the DTC activation by software. activation 1: Enables the DTC activation by software. enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit. [Clearing conditions] * * When the DISEL bit is 0 and the specified number of data transfers has not ended. When 0 is written to the DISEL bit after a software-activated data transfer end interrupt (SWDTEND) request has been sent to the CPU. When the DISEL bit is 1 and data transfer has ended or when the specified number of data transfers has ended, this bit will not be cleared. 6 5 4 3 2 1 0 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 R/W DTC software These bits specify a vector number for DTC activation activation by software. R/W vector 6 to 0 These bits specify a vector number for DTC software R/W activation. R/W The vector address is expressed as H'0400 + (vector R/W number x 2). For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. R/W When the bit SWDTE is 0, these bits can be written. R/W DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Rev. 1.00 Oct. 03, 2008 Page 341 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.3 Activation Sources The DTC operates when activated by an interrupt request or by a write to DTVECR by software. An interrupt request can be designated by the DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding bit to DTCER is cleared. For example, the activation source flag, in the case of SCI3_1_RXI, is the RDRF flag of SCI3_1. When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities for the interrupt sources. Table 11.2 shows a relationship between activation sources and DTCER clear conditions. Figure 11.2 shows a block diagram of DTC activation source control. For details, see section 4, Interrupt Controller. Table 11.2 Relationship between Activation Sources and DTCER Clearing DISEL = 0 and Specified Number of Transfers Has Not Ended SWDTE bit is cleared to 0 * * DISEL = 1 or Specified Number of Transfers Has Ended * * Activation by an interrupt Corresponding DTCER bit remains set to 1. Activation source flag is cleared to 0. * * * SWDTE bit remains set to 1 Interrupt request to CPU Corresponding DTCER bit is cleared to 0. Activation source flag remains set to 1. Interrupt that became the activation source is requested to the CPU. Activation Source Activation by software Rev. 1.00 Oct. 03, 2008 Page 342 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Source flag cleared Clear controller Clear DTCER Select Clear request IRQ interrupt Interrupt request Selection circuit On-chip peripheral module DTC DTVECR Interrupt controller Interrupt mask CPU Figure 11.2 Block Diagram of DTC Activation Source Control Rev. 1.00 Oct. 03, 2008 Page 343 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM. Register information should be located at the address that is multiple of four. Locating the register information in address space is shown in figure 11.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas as shown in figure 11.3 and the register information start address should be located at the corresponding vector address to the activation source. Figure 11.4 shows correspondences between the DTC vector address and register information. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] x 2). For example, if VOFR and DTVECR are H'0000 and H'18 respectively, the vector address is H'0430. The configuration of the vector address is a 2-byte unit. These two bytes specify the lower bits of the start address. Variable vector addresses can be used by setting VOFR. For details on VOFR settings, see section 4, Interrupt Controller. Rev. 1.00 Oct. 03, 2008 Page 344 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Lower addresses 0 Start address of register information MRA MRB CRA Chain transfer MRA MRB CRA Four bytes SAR DAR CRB Register information for second transfer in case of chain transfer 1 2 SAR DAR CRB Register information 3 Figure 11.3 Locating DTC Register Information in Address Space DTC vector address Start address of register information Register information Chain transfer Figure 11.4 Correspondence between DTC Vector Address and Register Information Rev. 1.00 Oct. 03, 2008 Page 345 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Table 11.3 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Activation Source Software External pin Vector Number Activation Source Write to DTVECR IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Vector Address* 1 DTCE* 5 Priority High DTVECR H'0400 + (DTVECR[6:0] x 2) 22 23 24 25 26 27 28 29 30 H'42C to H'42D H'42E to H'42F H'430 to H'431 H'432 to H'433 H'434 to H'435 H'436 to H'437 H'438 to H'439 H'43A to H'43B H'43C to H'43D H'43E to H'43F H'442 to H'443 H'444 to H'445 H'446 to H'447 H'448 to H'449 H'44C to H'44D H'44E to H'44F H'454 to H'455 H'456 to H'457 H'45C to H'45D H'45E to H'45F H'478 to H'479 H'47A to H'47B DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCED7 DTCED6 A/D converter unit 1 IADEND_1 (conversion completion) IADCMP_1 31 (compare condition match) A/D converter unit 2*2 IADEND_2 (conversion completion) 32 IADCMP_2 33 (compare condition match) ELC ELC1FP 35 (ELSR12 event occurrence) ELC2FP 36 (ELSR30 event occurrence) SCI3 channel 1 SCI3_1 RXI SCI3_1 TXI SCI3 channel 2 SCI3_2 RXI SCI3_2 TXI SCI3 channel 3 SCI3_3 RXI SCI3_3 TXI IIC2/SSU IIC2/SSU_RXI IIC3/SSU_TXI 38 39 42 43 46 47 60 61 Low Rev. 1.00 Oct. 03, 2008 Page 346 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Origin of Activation Source Timer RC* 3 Activation Source ITCMA Input capture A/ compare match A ITCMB Input capture B/ compare match B ITCMC Input capture C/ compare match C ITCMD Input capture D/ compare match D Vector Vector 1 Number Address* 71 H'48E to H'48F DTCE* 5 Priority High DTCED3 72 H'490 to H'491 DTCED2 73 H'492 to H'493 DTCED1 74 H'494 to H'495 DTCED0 Timer RD unit 0 channel 0 ITDMA0_0 Input capture A/ compare match A ITDMB0_0 Input capture B/ compare match B ITDMC0_0 Input capture C/ compare match C ITDMD0_0 Input capture D/ compare match D 76 H'498 to H'499 DTCEE7 77 H'49A to H'49B DTCEE6 78 H'49C to H'49D DTCEE5 79 H'49E to H'49F DTCEE4 Timer RD unit 0 channel 1*4 ITDMA0_1 Input capture A/ compare match A ITDMB0_1 Input capture B/ compare match B ITDMC0_1 Input capture C/ compare match C ITDMD0_1 Input capture D/ compare match D 82 H'4A4 to H'4A5 DTCEE3 83 H'4A6 to H'4A7 DTCEE2 84 H'4A8 to H'4A9 DTCEE1 85 H'4AA to H'4AB DTCEE0 Low Rev. 1.00 Oct. 03, 2008 Page 347 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Origin of Activation Source Timer RD unit 1 channel 2*4 Activation Source ITDMA1_2 Input capture A/ compare match A ITDMB1_2 Input capture B/ compare match B ITDMC1_2 Input capture C/ compare match C ITDMD1_2 Input capture D/ compare match D Vector Vector 1 Number Address* 87 H'4AE to H'4AF DTCE* 5 Priority High DTCEF7 88 H'4B0 to H'4B1 DTCEF6 89 H'4B2 to H'4B3 DTCEF5 90 H'4B4 to H'4B5 DTCEF4 Timer RD unit 1 channel 3*4 ITDMA1_3 Input capture A/ compare match A ITDMB1_3 Input capture B/ compare match B ITDMC1_3 Input capture C/ compare match C ITDMD1_3 Input capture D/ compare match D 93 H'4BA to H'4BB DTCEF3 94 H'4BC to H'4BD DTCEF2 95 H'4BE to H'4BF DTCEF1 96 H'4C0 to H'4C1 DTCEF0 Timer RE ITESC ITEMI ITEHR ITEDY ITEWK 100 101 102 103 104 109 H'4C8 to H'4C9 DTCEG4 H'4CA to H'4CB DTCEG3 H'4CC to H'4CD DTCEG2 H'4CE to H'4CF DTCEG1 H'4D0 to H'4D1 DTCEG0 Timer RG ITGMA Input capture A/ compare match A ITGMB Input capture B/ compare match B H'4DA to H'4DB DTCEH3 110 H'4DC to H'4DD DTCEH2 Low Rev. 1.00 Oct. 03, 2008 Page 348 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Notes: 1. 2. 3. 4. 5. Vector address indicates the lower 11 bits of vector address when VOFR = H'0000. Supported only in the H8S/20223 group and reserved in other products. Supported only in the H8S/20103 group and reserved in other products. Not supported in the H8S/20103 group and reserved in the H8S/20103 group. DTCE bits with no corresponding interrupt are reserved. The write value should always be 0. 11.5 Operation The DTC stores register information in the on-chip RAM. When activated, the DTC reads register information in the on-chip RAM and transfers data. After the data transfer, it writes updated register information back to the on-chip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer data over any required number of channels. There are three transfer modes: normal mode, repeat mode, and block transfer mode. Setting the CHNE bit to 1 allows a number of transfers with a single activation (chain transfer). Setting the CHNS bit to 1 enables chain transfer only when the transfer counter value is 0. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed according to the register information. Figure 11.5 shows a flowchart of DTC operation, and table 11.4 summarizes the chain transfer conditions (for performing the first and second transfers). Rev. 1.00 Oct. 03, 2008 Page 349 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1 No Yes CHNS = 0 Yes Transfer counter = 0 or DISEL = 1 No No Yes Transfer counter = 0 No DISEL = 1 Yes No Yes Clear activation source flag Clear DTCER End Interrupt exception handling Figure 11.5 Flowchart of DTC Operation Rev. 1.00 Oct. 03, 2008 Page 350 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Table 11.4 Chain Transfer Conditions 1st Transfer CHNE CHNS DISEL CR 0 0 0 1 0 0 0 1 Except 0 0 0 0 0 1 1 1 1 0 Except 0 0 0 0 0 1 1 1 Except 0 2nd Transfer CHNE CHNS DISEL CR 0 0 1 0 0 1 0 0 DTC Transfer Ends at 1st transfer Ends at 1st transfer Interrupt request to CPU Except 0 Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU Ends at 1st transfer Except 0 Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU Ends at 1st transfer Interrupt request to CPU 11.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. Table 11.5 lists the register function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt can be requested. Table 11.5 Register Function in Normal Mode Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Abbreviation SAR DAR CRA CRB Function Designates transfer source address Designates transfer destination address Designates transfer count Not used Rev. 1.00 Oct. 03, 2008 Page 351 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) SAR Transfer DAR Figure 11.6 Memory Mapping in Normal Mode 11.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 11.6 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode, the transfer counter value does not reach H'00, therefore CPU interrupts cannot be requested when DISEL = 0. Table 11.6 Register Function in Repeat Mode Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Abbreviation SAR DAR CRAH CRAL CRB Function Designates transfer source address Designates transfer destination address Holds number of transfers Designates transfer count Not used Rev. 1.00 Oct. 03, 2008 Page 352 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) SAR or DAR Repeat area Transfer DAR or SAR Figure 11.7 Memory Mapping in Repeat Mode 11.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 11.7 lists the register function in block transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed according to the register information. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt is requested. Table 11.7 Register Function in Block Transfer Mode Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds block size Designates block size count Designates transfer count Rev. 1.00 Oct. 03, 2008 Page 353 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) First block SAR or DAR Block area Transfer DAR or SAR Nth block Figure 11.8 Memory Mapping in Block Transfer Mode 11.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB can be set independently. Figure 11.9 shows the operation of chain transfer. When activated, the DTC reads the register information start address stored at the vector address, and then reads the first register information at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is 1, the next register information, which is located consecutively, is read and transfer is performed. This operation is repeated until the end of data transfer of register information with CHNE = 0. Setting both the CHNE bit and CHNS bit to 1 enables execution of chain transfer only when the transfer counter value is 0. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. Rev. 1.00 Oct. 03, 2008 Page 354 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Source Destination Register information CHNE=1 DTC vector address Start address of register information Register information CHNE=0 Source Destination Figure 11.9 Operation of Chain Transfer 11.5.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC ends the specified number of data transfers, or when the DTC ends a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended or the specified number of transfers has ended, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated after data transfer ends. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. Rev. 1.00 Oct. 03, 2008 Page 355 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.5.6 Operation Timing DTC activation request DTC request Data transfer Read Write Vector read Address Transfer information read Transfer information write Figure 11.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) DTC activation request DTC request Vector read Address Data transfer Read Write Read Write Transfer information read Transfer information write Figure 11.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) Rev. 1.00 Oct. 03, 2008 Page 356 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) DTC activation request DTC request Vector read Address Read Write Read Write Data transfer Data transfer Transfer information read Transfer information write Transfer information read Transfer information write Figure 11.12 DTC Operation Timing (Example of Chain Transfer) 11.5.7 Number of DTC Execution States Table 11.8 lists execution state for a single DTC data transfer, and table 11.9 shows the number of states required for each execution status. Table 11.8 DTC Execution State Register Information Read/Write J 6 6 6 Internal Operations M 3 3 3 Mode Normal Repeat Block transfer Vector Read I 1 1 1 Data Read K 1 1 N Data Write L 1 1 N Legend: N: Block size (initial setting value of CRAH and CRAL) Rev. 1.00 Oct. 03, 2008 Page 357 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Table 11.9 Number of States Required for Each Execution Status OnChip RAM 32 1 1 1 1 1 1 1 OnChip ROM Internal I/O Register 16 1 1 1 1 1 1 2 2 2 4 2 4 8 3 3 3 6 3 6 1 4 4 4 8 4 8 2 2 2 2 2 2 16 3 3 3 3 3 3 4 4 4 4 4 4 Object to be Accessed Bus width Access states Execution state Vector read SI Register information read/write SJ Byte data read SK Word data read SK Byte data write SL Word data write SL Internal operation SM The number of execution states is calculated from the formula below. Note that means the sum of all transfers activated by one activation source (the number in which the CHNE bit is set to 1 + 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL) + M * SM For example, when the DTC vector address table is located in on-chip ROM and data is transferred from the on-chip ROM to an internal I/O register (two-state access) in normal mode, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. Rev. 1.00 Oct. 03, 2008 Page 358 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.6 11.6.1 Procedures for Using DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. 2. 3. 4. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Set the corresponding bit in DTCER to 1. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software 11.6.2 The procedure for using the DTC with software activation is as follows: 1. 2. 3. 4. 5. 6. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Check that the SWDTE bit is 0. Write 1 to the SWDTE bit and the vector number to DTVECR. Check the vector number written to DTVECR. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers has ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. Clear the SWDTE bit to 0 by an interrupt processing routine. Rev. 1.00 Oct. 03, 2008 Page 359 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.7 11.7.1 Examples of Use of the DTC Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI3. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the RDR address in SCI3 of SAR, the start address of the RAM area where the data is stored in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI3 to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI3, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform termination processing. Rev. 1.00 Oct. 03, 2008 Page 360 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.7.2 Chain Transfer when Transfer Counter = 0 By executing the second data transfer, and performing re-setting of the first data transfer, only when the counter value is 0, 256 or more repeat transfers can be performed. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 11.13 shows overview of the chain transfer when the counter value is 0. 1. For the first transfer, set the normal mode for input data. Set fixed transfer source address (G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20. 3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer is H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, an interrupt request is not sent to the CPU. Rev. 1.00 Oct. 03, 2008 Page 361 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data transfer register information Upper 8 bits of DAR Figure 11.13 Chain Transfer when Counter = 0 Rev. 1.00 Oct. 03, 2008 Page 362 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.7.3 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the transfer destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that H'60 is set to the vector number. If it is not, this indicates that the write has failed. This is because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. Rev. 1.00 Oct. 03, 2008 Page 363 of 962 REJ09B0465-0100 Section 11 Data Transfer Controller (DTC) 11.8 11.8.1 Usage Notes Module Standby Mode Setting DTC operation can be disabled or enabled using the module standby control register. The initial value is for DTC operation to be disabled. When the DTC is used, cancel module standby mode. Register access is disabled in module standby mode. Module standby mode cannot be set while the DTC is activated. For details, see section 6, Power-Down Modes. 11.8.2 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. 11.8.3 DTC Activation by SCI3, IIC2/SSU and A/D Converter Interrupt Sources Interrupts and activation sources of the SCI3, IIC2/SSU, and A/D converter are cleared when the DTC reads or writes the prescribed register. Therefore, when the DTC is activated by an interrupt or activation source, the interrupt or activation source will be retained if a read/write of the relevant register is not included in the last chained data transfer. The above operation is performed regardless of the DISEL bit setting. Rev. 1.00 Oct. 03, 2008 Page 364 of 962 REJ09B0465-0100 Section 12 Event Link Controller Section 12 Event Link Controller The event link controller (ELC) connects the events generated by the various peripheral modules to different modules. This function allows direct cooperation between the modules without CPU intervention. A block diagram of the ELC is shown in figure 12.1. 12.1 Overview * Fifty-nine event signals can be directly connected to modules. * The operation of timer modules can be selected when an event is input to the timer module. * Events can be connected to ports 3 and 6. Single port-pin: An event link can be set for a single specific pin of a port. Port group: An event link can be set for a specific group of bits within an 8-bit port. In addition, in the specified single pin or group within a port, an event is generated by a change in the value of the linked signals. * Four channels of events can be generated in arbitrary setting interval using the eventgeneration timer. Rev. 1.00 Oct. 03, 2008 Page 365 of 962 REJ09B0465-0100 Section 12 Event Link Controller ELCR ELSR0 to ELSR31 Event control Peripheral modules ELOPA ELOPB ELOPC Timer event input control Peripheral timer modules PGR1, PGR2 PGC1, PGC2 PDBF1, PDBF2 PEL0 to PEL3 ELTMCR ELTMSA ELTMSB ELTMDR Port event input/output control Port 3 or port 6 Event-generation timer Event signal 1 Event signal 2 Event signal 3 Event signal 4 ELTMCNT Figure 12.1 Block Diagram of Event Link Controller Rev. 1.00 Oct. 03, 2008 Page 366 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2 Register Descriptions The ELC has the following registers. * * * * * * * * * * * * * * Event link control register (ELCR) Event link setting registers 0 to 32 (ELSR0 to ELSR32) Event link option setting register A (ELOPA) Event link option setting register B (ELOPB) Event link option setting register C (ELOPC) Port-group setting registers 1 and 2 (PGR1, PGR2) Port-group control registers 1 and 2 (PGC1, PGC2) Port buffer registers 1 and 2 (PDBF1 and PDBF2) Event link port setting registers 0 to 3 (PEL0 to PEL3) Event-generation timer control register (ELTMCR) Event-generation timer interval setting register A (ELTMSA) Event-generation timer interval setting register B (ELTMSB) Event-generation timer delay selection register (ELTMDR) ELC timer counter (ELTMCNT) Event Link Control Register (ELCR) 12.2.1 Address: H'FF06BC Bit: b7 ELCON Value after reset: 0 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 1 1 Bit 7 Symbol ELCON Bit Name All event link enable Reserved Description 0: Linkage of all the events are disabled. 1: Linkage of all the events are enabled. These bits are read as 1. The write value should be 1. R/W R/W 6 to 0 ELCR controls the operation of the event link controller (ELC) collectively. Rev. 1.00 Oct. 03, 2008 Page 367 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.2 Event Link Setting Registers 0 to 32 (ELSR0 to ELSR32) H'FF0680 to H'FF0684, H'FF0688, H'FF068A to H'FF068C, H'FF068E, H'FF068F, H'FF0692, H'FF0693, H'FF0695 to H'FF0698, H'FF069D to H'FF06A0 b7 ELSn7 b6 ELSn6 0 b5 ELSn5 0 b4 ELSn4 0 b3 ELSn3 0 b2 ELSn2 0 b1 ELSn1 0 b0 ELSn0 0 Address: Bit: Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol ELSn7 ELSn6 ELSn5 ELSn4 ELSn3 ELSn2 ELSn1 ELSn0 Bit Name Event link select n7 Event link select n6 Event link select n5 Event link select n4 Event link select n3 Event link select n2 Event link select n1 Event link select n0 Description 00000000: Linkage of the event is disabled. R/W R/W 0000001 to 01100001: Set the number specific to the event signal to be linked. R/W Other than the above: Setting prohibited. R/W R/W R/W R/W R/W R/W [Legend] n: 0 to 32 (except 5 to 7, 9, 13, 16, 17, 20, and 25 to 28) Each of ELSR0 to ELSR32 specifies an event signal to be linked for the peripheral module. Table 12.1 shows the correspondence between ELSR0 to ELSR31 and the peripheral modules. Table 12.2 shows the correspondence between the event signal names and the numbers specific to the signals. Rev. 1.00 Oct. 03, 2008 Page 368 of 962 REJ09B0465-0100 Section 12 Event Link Controller Table 12.1 Correspondence between ELSR and Peripheral Modules Register Name ELSR0 ELSR1 ELSR2* ELSR3 ELSR4 ELSR8 ELSR10 ELSR11* ELSR12 ELSR14 ELSR15 ELSR18 ELSR19 ELSR21 ELSR22 ELSR23 ELSR24 ELSR29 ELSR30 ELSR31 ELSR32 Note: 2 1 Peripheral Module (Functions) Timer RA Timer RB Timer RC Timer RD_0 channel 0 Timer RD_0 channel 1 Timer RG AD converter unit 1 AD converter unit 2 Interrupts 1 Output port-group 2 Output port-group 3 Input port-group 2 Input port-group 3 Single-port 1 Single-port 2 Single-port 3 Single-port 4 Clock oscillator Interrupts 2 DA converter channel 0 DA converter channel 1 1. Supported only in the H8S/20103 group. 2. Supported only in the H8S/20223 group. Rev. 1.00 Oct. 03, 2008 Page 369 of 962 REJ09B0465-0100 Section 12 Event Link Controller Table 12.2 Correspondence between Event Signal Names and ELSn Bit Values ELSn7 to ELSn0 Bit Value (Signal Number) 00000001 (H'01) 00000010 (H'02) 00000011 (H'03)* 1 Name of Event Signal to Set ELSR Timer RA underflow Timer RB underflow Timer RC overflow Timer RC compare-match A Timer RC compare-match B Timer RC compare-match C Timer RC compare-match D Timer RD_0 channel 0 overflow Timer RD_0 channel 0 compare-match A Timer RD_0 channel 0 compare-match B Timer RD_0 channel 0 compare-match C Timer RD_0 channel 0 compare-match D Timer RD_0 channel 1 overflow Timer RD_0 channel 1 underflow Timer RD_0 channel 1 compare-match A Timer RD_0 channel 1 compare-match B Timer RD_0 channel 1 compare-match C Timer RD_0 channel 1 compare-match D Timer RG overflow Timer RG underflow Timer RG compare-match A Timer RG compare-match B AD conversion end in AD converter unit 1 00000100 (H'04)*1 00000101 (H'05)* 00000110 (H'06)* 00000111 (H'07)* 00001000 (H'08) 00001001 (H'09) 00001010 (H'0A) 00001011 (H'0B) 00001100 (H'0C) 00001101 (H'0D) 00001110 (H'0E) 00001111 (H'0F) 00010000 (H'10) 00010001 (H'11) 00010010 (H'12) 00100001 (H'21) 00100010 (H'22) 00100011 (H'23) 00100100 (H'24) 00101001 (H'29) 00101010 (H'2A)* 00101100 (H'2C) 00101101 (H'2D) 00101111 (H'2F) 00110000 (H'30) 00110001 (H'31) 00110010 (H'32) 00110111 (H'37) 2 1 1 1 AD conversion end in AD converter unit 2 Input edge detection on input port-group 1 Input edge detection on input port-group 2 Input edge detection on single input port 1 Input edge detection on single input port 2 Input edge detection on single input port 3 Input edge detection on single input port 4 Voltage-drop detection in LVD Rev. 1.00 Oct. 03, 2008 Page 370 of 962 REJ09B0465-0100 Section 12 Event Link Controller ELSn7 to ELSn0 Bit Value (Signal Number) 00111000 (H'38) 00111001 (H'39) 00111010 (H'3A) 00111011 (H'3B) 00111100 (H'3C) 00111101 (H'3D) 00111110 (H'3E) 00111111 (H'3F) 01000000 (H'40) 01000001 (H'41) 01000010 (H'42) 01000011 (H'43) 01001010 (H'4A) 01001011 (H'4B) 01001100 (H'4C) 01001101 (H'4D) 01001110 (H'4E) 01001111 (H'4F) 01010000 (H'50) 01010001 (H'51) 01010010 (H'52) 01010011 (H'53) 01010100 (H'54) 01010101 (H'55) 01011110 (H'5E) 01011111 (H'5F) 01100000 (H'60) 01100001 (H'61) Note: Name of Event Signal to Set ELSR Voltage-drop reset detection in LVD CPG backup start WDT increment WDT reset Timer RE interval (week, day, hour, minute, or second) DTC transfer end Transmit-buffer empty in IIC2/SSU Transmit end in IIC2/SSU Receive-buffer full in IIC2/SSU Stop-condition detection in IIC2/SSU Arbitration loss/overrun error in IIC2/SSU NACK detection/conflict error in IIC2/SSU SCI3_1 transmit-buffer empty SCI3_1 transmit end SCI3_1 receive-buffer full SCI3_1 transfer error SCI3_2 transmit-buffer empty SCI3_2 transmit end SCI3_2 receive-buffer full SCI3_2 transfer error SCI3_3 transmit-buffer empty SCI3_3 transmit end SCI3_3 receive-buffer full SCI3_3 transfer error Timer ELC event 0 Timer ELC event 1 Timer ELC event 2 Timer ELC event 3 Other than the above: Setting prohibited 1. Selected for the H8S/20103 group. 2. Selected for the H8S/20223 group. Rev. 1.00 Oct. 03, 2008 Page 371 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.3 Event Link Option Setting Register A (ELOPA) Address: H'FF06B5 Bit: b7 b6 b5 b4 b3 b2 b1 b0 TMRAM[2:1] Value after reset: 1 1 1 TMRBM[2:1] 1 1 TMRCM[2:1] 1 TMRD1M[2:1] 1 1 Bit 7 6 Symbol TMRAM [2:1] Bit Name Timer RA operation select Description 00: Timer starts counting. 01: Timer counts events. 10: Setting prohibited. 11: Events disabled. 00: Timer starts counting. 01: Timer counts events. 10: Setting prohibited. 11: Events disabled. 00: Timer starts counting. 01: Timer counts events. 10: Timer performs input-capture operation.* 11: Events disabled. 00: Timer starts counting. 01: Timer counts events. 10: Timer performs input-capture operation.* 11: Events disabled. 3 2 R/W R/W 5 4 TMRBM [2:1] Timer RB operation select R/W 3 2 TMRCM [2:1]*1 Timer RC operation select R/W 1 0 TMRD1M [2:1] Timer RD_0 channel 0 operation select R/W Note: 1. Selected only for the H8S/20103 group and reserved in other products. When writing, b'11 should be written. 2. The TRCCNT value is captured by GRD. 3. The TRDCNT_0 value is captured by GRD_0. ELOPA determines the operation of timer RA, timer RB, timer RC, and timer RD_0 when an event is input to the timer. Rev. 1.00 Oct. 03, 2008 Page 372 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.4 Event Link Option Setting Register B (ELOPB) Address: H'FF06B6 Bit: b7 b6 b5 b4 b3 b2 b1 b0 TMRD2M[2:1] Value after reset: 1 1 1 1 1 1 1 1 Bit 7, 6 Symbol Bit Name Description 00: Timer starts counting. 01: Timer counts events. 10: Timer performs input-capture operation.* 11: Events disabled. R/W R/W TMRD2M Timer RD_0 [2:1] channel 1 operation select 5 to 0 Note: * Reserved These bits are read as 1. The write value should be 1. The TRDCNT_1 value is captured by GRD_1. ELOPB determines the operation of timer RD_0 when an event is input to the timer. 12.2.5 Event Link Option Setting Register C (ELOPC) Address: H'FF06B7 Bit: b7 b6 b5 1 1 b4 1 b3 1 b2 1 b1 1 b0 1 TMRGM[2:1] Value after reset: 1 Bit 7, 6 Symbol TMRGM [2:1] Bit Name Description R/W R/W Timer RG 00: Timer starts counting. operation select 01: Timer counts events. 10: Timer performs input-capture operation.* 11: Events disabled. 5 to 0 Note: * Reserved These bits are read as 1. The write value should be 1. The TRGCNT value is captured by GRB. ELOPC determines the operation of timer RG when an event is input to the timer. Rev. 1.00 Oct. 03, 2008 Page 373 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.6 Port-Group Setting Registers 1 and 2 (PGR1 and PGR2) H'FF06A2, H'FF06A3 b7 PGRn7 b6 PGRn6 0 b5 PGRn5 0 b4 PGRn4 0 b3 PGRn3 0 b2 PGRn2 0 b1 PGRn1 0 b0 PGRn0 0 Address: Bit: Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PGRn7 PGRn6 PGRn5 PGRn4 PGRn3 PGRn2 PGRn1 PGRn0 Bit Name Port-group setting n7 Port-group setting n6 Port-group setting n5 Port-group setting n4 Port-group setting n3 Port-group setting n2 Port-group setting n1 Port-group setting n0 Description 0: The port bit is not specified as the member of the same group. 1: The port bit is specified as the member of the same group. R/W R/W R/W R/W R/W R/W R/W R/W R/W [Legend] n: 1 or 2 PGR specifies each port bit in the same 8-bit I/O port as the member of a group. One to eight port bits can be specified as the members of the same group as required. The correspondence between PGR and ports is shown in table 12.3. Rev. 1.00 Oct. 03, 2008 Page 374 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.7 Port-Group Control Registers 1 and 2 (PGC1 and PGC2) H'FF06A6, H'FF06A7 b7 Address: Bit: b6 b5 PGCOn[2:0] b4 b3 b2 PGCOVEn 0 b1 PGCIn[1:0] 0 b0 Value after reset: 1 0 0 0 1 0 Bit 7 Symbol Bit Name Reserved Description This bit is read as 1. The write value should be 1. 000: 0 is output when the event is input. 001: 1 is output when the event is input. 010: The toggled (inverted) value is output when the event is input. 011: The buffer value is output when the event is input. 1XX: The bit value is sifted out in the group (from MSB to LSB) when the event is input. R/W R/W 6 to 4 PGCOn[2:0] Port group operation select 3 2 1, 0 PGCOVEn PGCIn[1:0] Reserved PDBF overwrite Event output edge select This bit is read as 1. The write value should be 1. 0: Overwriting PDBF is disabled. 1: Overwriting PDBF is enabled. 00: Event is generated upon detection of the rising edge of the external input signal. 01: Event is generated upon detection of the falling edge of the external input signal. 1X: Event is generated upon detection of both the rising and falling edge of the external input signal. R/W R/W [Legend] n: 1 or 2 X: Don't care. For the output port-group, PGC specifies the form of outputting the signal externally via the port when the event signal is input. For the input port-group, PGC enables/disables overwriting of PDBF and specifies the conditions of event generation (edge of the externally input signal). The correspondence between PGR and ports is shown in table 12.3. Rev. 1.00 Oct. 03, 2008 Page 375 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.8 Port Buffer Registers 1 and 2 (PDBF1 and PDBF2) H'FF06AA, H'FF06AB b7 PDBFn7 b6 PDBFn6 0 b5 PDBFn5 0 b4 PDBFn4 0 b3 PDBFn3 0 b2 PDBFn2 0 b1 PDBFn1 0 b0 PDBFn0 0 Address: Bit: Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol PDBFn7 PDBFn6 PDBFn5 PDBFn4 PDBFn3 PDBFn2 PDBFn1 PDBFn0 Bit Name Description R/W R/W R/W R/W R/W R/W R/W R/W R/W Port buffer n7 Data is transferred between PDR and PDBF when Port buffer n6 an event is input. Write access to the bit specified as a member of the input port-group by the CPU is Port buffer n5 invalid. For details, see section 12.3, Operation. Port buffer n4 Port buffer n3 Port buffer n2 Port buffer n1 Port buffer n0 [Legend] n: 1, 2 PDBF is an 8-bit readable/writable register used in combination with PGR. For PDBF operations, see section 12.3, Operation. The correspondence of PPBF and PDR is shown in table 12.3. Table 12.3 Registers Related to Port-Groups and Corresponding Port Numbers Port Group Setting Register (PGR) PGR1 PGR2 Port Group Control Register (PGC) PGC1 PGC2 Port Buffer Register (PDBF) PDBF1 PDBF2 Port Number Port 3 Port 6 Rev. 1.00 Oct. 03, 2008 Page 376 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.9 Event Link Port Setting Registers 0 to 3 (PEL0 to PEL3) Address: H'FF06AD to H'FF06B0 Bit: b7 Value after reset: 1 0 b6 b5 PSMn[1:0] 0 0 b4 b3 PSPn[4:3] 0 0 b2 b1 PSPn[2:0] 0 0 b0 Bit 7 6 5 Symbol PSMn[1:0] Bit Name Reserved Event link specification Description This bit is read as 1. The write value should be 1. * For the output port, data to be output from the port is specified. 00: 0 is output when the event is input. 01: 1 is output when the event is input. 1X: The toggled (inverted) value is output when the event is input. * For the input port, the edge on which the event is to be output is specified. 00: Event is output upon detection of the rising edge. 01: Event is output upon detection of the falling edge. 1X: Event is output upon detection of both the rising and falling edge. R/W R/W 4 3 PSPn[4:3] Port number specification 00: Do not set this value. 01: Port 3 (corresponding to PGR1) 10: Port 6 (corresponding to PGR2) 11: Do not set this value. R/W 2 1 0 PSPn2 PSPn1 PSPn0 Bit number specification A bit number in an 8-bit port is specified. R/W R/W R/W [Legend] n: 0 to 3 X: Don't care. PEL specifies the 1-bit port (hereinafter referred to as a single-port) to which an event is to be linked, the port operation upon the event signal input, and the conditions of event generation. With this LSI, a total of four bits in either port 3 or port 6 (8-bit ports) can be specified as single-ports. Rev. 1.00 Oct. 03, 2008 Page 377 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.10 Event-Generation Timer Control Register (ELTMCR) Address: H'FF06B8 Bit: b7 TMRSTR Value after reset: 0 b6 1 b5 1 b4 1 0 0 b3 b2 b1 b0 CLSRS[3:0] 0 0 Bit 7 Symbol TMRSTR Bit Name Timer count start Reserved Description 0: Counter is stopped. 1: Counter is incremented. R/W R/W 6 to 4 These bits are read as 1. The write value should be 1. R/W 3 to 0 CLSRS[3:0] Clock source (ELC) 0000: select 0001: /2 0010: /4 0011: /8 0100: /16 0101: /32 0110: /64 0111: /128 1000: /256 1001: /512 1010: /1024 1011: /2048 1100: /4096 1101: /8192 1110: Reserved (Counter is stopped.) 1111: Reserved (Counter is stopped.) Note: Be sure to stop the counter before changing the clock source. ELTMCR controls the ELTMCNT operation and selects the clock source. Rev. 1.00 Oct. 03, 2008 Page 378 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.11 Event-Generation Timer Interval Setting Register A (ELTMSA) Address: H'FF06B9 Bit: b7 b6 b5 C1CLS[3:0] Value after reset: 1 0 0 0 1 b4 b3 b2 C0CLS[3:0] 0 0 0 b1 b0 Bit Symbol Bit Name Description R/W R/W 7 to 4 C1CLS[3:0] Channel 1 0000: Clock source ELC/1 event0001: Clock source ELC/2 generation interval select 0010: Clock source ELC/4 0011: Clock source ELC/8 0100: Clock source ELC/16 0101: Clock source ELC/32 0110: Clock source ELC/64 0111: Clock source ELC/128 1000: Clock source ELC/256 (initial value) 1001: Clock source ELC/512 1010: Clock source ELC/1024 1011: Clock source ELC/2048 1100: Clock source ELC/4096 1101: Clock source ELC/8192 1110: Clock source ELC/16384 1111: Clock source ELC/32768 Rev. 1.00 Oct. 03, 2008 Page 379 of 962 REJ09B0465-0100 Section 12 Event Link Controller Bit Symbol Bit Name Description 0000: Clock source ELC/1 0001: Clock source ELC/2 0010: Clock source ELC/4 0011: Clock source ELC/8 0100: Clock source ELC/16 0101: Clock source ELC/32 0110: Clock source ELC/64 0111: Clock source ELC/128 1000: Clock source ELC/256 (initial value) 1001: Clock source ELC/512 1010: Clock source ELC/1024 1011: Clock source ELC/2048 1100: Clock source ELC/4096 1101: Clock source ELC/8192 1110: Clock source ELC/16384 1111: Clock source ELC/32768 R/W R/W 3 to 0 C0CLS[3:0] Channel 0 eventgeneration interval select Note: Do not set B'0000 when the clock source is set to s. ELTMSA determines the event-generation interval for channels 0 and 1, and sets the division ratio for the clock source specified by ELTMCR. Rev. 1.00 Oct. 03, 2008 Page 380 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.12 Event-Generation Timer Interval Setting Register B (ELTMSB) Address: H'FF06BA Bit: b7 b6 b5 C3CLS[3:0] Value after reset: 1 0 0 0 1 b4 b3 b2 C2CLS[3:0] 0 0 0 b1 b0 Bit Symbol Bit Name Description 0000: Clock source ELC/1 0001: Clock source ELC/2 0010: Clock source ELC/4 0011: Clock source ELC/8 0100: Clock source ELC/16 0101: Clock source ELC/32 0110: Clock source ELC/64 0111: Clock source ELC/128 1000: Clock source ELC/256 (initial value) 1001: Clock source ELC/512 1010: Clock source ELC/1024 1011: Clock source ELC/2048 1100: Clock source ELC/4096 1101: Clock source ELC/8192 1110: Clock source ELC/16384 1111: Clock source ELC/32768 R/W R/W 7 to 4 C3CLS[3:0] Channel 3 eventgeneration interval select Rev. 1.00 Oct. 03, 2008 Page 381 of 962 REJ09B0465-0100 Section 12 Event Link Controller Bit Symbol Bit Name Description 0000: Clock source ELC/1 0001: Clock source ELC/2 0010: Clock source ELC/4 0011: Clock source ELC/8 0100: Clock source ELC/16 0101: Clock source ELC/32 0110: Clock source ELC/64 0111: Clock source ELC/128 1000: Clock source ELC/256 (initial value) 1001: Clock source ELC/512 1010: Clock source ELC/1024 1011: Clock source ELC/2048 1100: Clock source ELC/4096 1101: Clock source ELC/8192 1110: Clock source ELC/16384 1111: Clock source ELC/32768 R/W R/W 3 to 0 C2CLS[3:0] Channel 2 eventgeneration interval select Note: Do not set B'0000 when the clock source is set to s. ELTMSB determines the event-generation interval for channels 2 and 3, and sets the division ratio for the clock source specified by ELTMCR. Rev. 1.00 Oct. 03, 2008 Page 382 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.13 Event-Generation Timer Delay Selection Register (ELTMDR) Address: H'FF06BB Bit: b7 b6 C3DLY[1:0] Value after reset: 0 0 0 b5 b4 C2DLY[1:0] 0 0 b3 b2 C1DLY[1:0] 0 0 b1 b0 C0DLY[1:0] 0 Bit 7, 6 Symbol Bit Name Description 00: No delay 01: 1 clock cycle 10: 2 clock cycles 11: 3 clock cycles R/W R/W C3DLY[1:0] Channel 3 delay select 5, 4 C2DLY[1:0] Channel 2 delay select 00: No delay 01: 1 clock cycle 10: 2 clock cycles 11: 3 clock cycles R/W 3, 2 C1DLY[1:0] Channel 1 delay select 00: No delay 01: 1 clock cycle 10: 2 clock cycles 11: 3 clock cycles R/W 1, 0 C0DLY[1:0] Channel 0 delay select 00: No delay 01: 1 clock cycle 10: 2 clock cycles 11: 3 clock cycles R/W Note: There is no delay when the event-generation interval is set to clock source /1. ELTMDR determines the necessary delay time, which is the time from the specified eventgeneration timing (= interval) to the actual generation timing of the event in terms of the cycles of the selected clock source. Rev. 1.00 Oct. 03, 2008 Page 383 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.2.14 ELC Timer Counter (ELTMCNT) Address: H'FF06C0 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELTMCNT is a 16-bit readable/writable up-counter. To select the input clock signal to be supplied to the counter, use the CLSRS[3:0] bits in ELTMCR. ELTMCNT cannot be accessed in 8-bit units; it must always be accessed in 16-bit units. The initial value of ELTMCNT is H'0000. To set the event-generation interval to the time from starting of the timer to generation of the first event, set the counter to 0. Rev. 1.00 Oct. 03, 2008 Page 384 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.3 12.3.1 Operation Relation between Interrupt Processing and Event Linking The modules incorporated in this LSI are provided with the interrupt request status flags and the bits to enable/disable these interrupt requests. When an interrupt request is generated in a module, the corresponding interrupt request status flag is set. If the corresponding interrupt request is enabled then, the interrupt requested is issued to the CPU. In contrast, the ELC uses interrupt requests (hereinafter referred to as events) generated in modules as event signals that directly activate other modules. This means that the event signal can be used whether or not the interrupt signal is enabled. Figure 12.2 shows the relation between the interrupt processing and ELC. Module External pin Interrupt request (event) ELC Port Module 1 Module n Status flag Interrupt enable control Interrupt control circuit CPU Figure 12.2 Relation between Interrupt Processing and ELC 12.3.2 Event Linkage When an event has been set as a trigger in the event-link setting registers (ELSR0 to ELSR32) and then occurs, that event is linked with the corresponding module (activate the module). Only one type of event can be connected with one module. When a module is to be activated by the eventlink controller, the operation of the module must be set up in advance. Table 12.4 lists the operations of modules when an event is input. Rev. 1.00 Oct. 03, 2008 Page 385 of 962 REJ09B0465-0100 Section 12 Event Link Controller Table 12.4 Operations of Modules when Event is Input Module Timer RA Timer RB Timer RC Timer RD Timer RG A/D converter D/A converter Output ports Operations when Event is Input Each timer operates differently depending on the setting of the relevant event link option setting register as below. * * * Starts counting when an event signal is input. Counts the input events. Performs input-capture operation when an event is input. (except timer RA and timer RB) Starts A/D conversion when an event signal is input. Starts D/A conversion when an event signal is input. The value of PDR (port data register) changes when an event signal is input. (The value of the signal to be output from the relevant external pin changes.) Port-groups The port-group operates differently depending on the settings as below. * * * Single-ports Changes the PDR value to the specified value. Transfers the PDBF values to the PDR. Shifts out the bit value. Changes the PDR value to the specified value. Input ports When the signal value of the input pin changes. When an event is input Port-groups Single-ports Port-groups Single-ports Generates an event. Transfers the signal value of the external pin to PDBF. Event connection is impossible. Clock oscillator Interrupt controller Switches the clock source to the low-speed on-chip oscillator operation. Issues an interrupt request to the CPU, and the DTC starts to transfer data. Rev. 1.00 Oct. 03, 2008 Page 386 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.3.3 Operation of Peripheral Timer Modules When Event is Input Three different operations are performed depending on the ELOP settings when an event is input. * Counting-Start Operation When an event is input, the timer starts counting, which sets the count start bit* in each timer control register to 1. An event that is input while the count start bit is 1 is invalid. * Event-Counter Operation Event-input is selected as the timer clock source and the timer counts events. * Input-Capture Operation When an event is input, the timer performs input-capture operation. Note: * See the descriptions on the bit in the relevant timer section. 12.3.4 Operation of A/D and D/A Converters When Event is Input The A/D and D/A converter start A/D and D/A conversion, respectively, which sets the start bits* in the A/D control register and the output enable bits* in the D/A control register to 1. Note: * See the descriptions on the bit in the A/D and D/A converter sections. Rev. 1.00 Oct. 03, 2008 Page 387 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.3.5 Port Operation upon Event Input and Event Generation The port operation to be performed upon event input to the port can be set and the operation causing the port to generate an event can be set. (1) Single-Ports and Port-Groups There are two event link modes: event link to single-ports and event link to port-groups. In the former mode, events can be connected to single-ports in an 8-bit port. In the latter mode, events can be connected to port-groups consisting of any two or more bits in the same 8-bit port. A single-port can be set by specifying any one bit in the port* to which an event can be connected using the PEL register. A port-group can be set by specifying any two or more bits in the port* to which an event can be connected using the PGR register. One input port-group and one output port-group can be set in the same port. If the port bit is specified as both a single-port and a member of a port-group, both functions are effective when the relevant port is input, whereas only the group-port function is effective when the relevant port is output. The input or output direction of ports can be selected using the PCR register. PCR should be set so that all the bits in the same port-group should have the same direction. Note: Port 3 and port 6 (2) Event Generation by Input Single-Ports An input single-port generates an event when the signal value of the external pin connected to the relevant port changes. The event-generation condition is specified using the PEL0 to PEL3 registers. An example of operation is shown in figure 12.3. (3) Output Single-Port Operation upon Event Input When an event is input to an output single-port, the PDR value of the relevant port changes. The specific change of the PDR value is specified using the PEL0 to PEL3 registers. Thus, the change of the PDR value changes the signal value of the external pin connected to the relevant port. An example of operation is shown in figure 12.3. Rev. 1.00 Oct. 03, 2008 Page 388 of 962 REJ09B0465-0100 Section 12 Event Link Controller (4) Input Port-Group Operation upon Event Input and Event Generation An input port-group generates an event when the signal value of any one of the external pins connected to the relevant port-group changes. The event-generation condition is specified using the PGC1 and PGC2 registers. When an event is input to an input port-group, the signal value of the external pin upon event input is transferred to PDBF. In this case, only the values of the bits specified as members of the input port-group are transferred. An example of operation is shown in figure 12.4. (5) Output Port-Group Operation upon Event Input When an event is input to an output port-group, the PDR values change to the values according to the PGC1 or PGC2 settings. An example of operation is shown in figure 12.5. Rev. 1.00 Oct. 03, 2008 Page 389 of 962 REJ09B0465-0100 Section 12 Event Link Controller Example of Operation for Single-Port Input Port 3 Port 37 On-chip module Event link Port 36 External pin Port 35 Port 34 Example of Operation for Single-Port Output Port 33 Event link Port 32 On-chip module Port 31 Port 30 Port to which event is connected Figure 12.3 Event Linkage related to Single-Ports Rev. 1.00 Oct. 03, 2008 Page 390 of 962 REJ09B0465-0100 Section 12 Event Link Controller PDBF 0 PDBF 0 P37 External signal 0 0 P36 0 0 P35 0 0 P34 0 1 P33 0 0 P32 0 1 P31 0 0 P30 P30 to P33 are specified as an input port-group. Event signal Figure 12.4 Event Linkage related to Input Port-Groups Rev. 1.00 Oct. 03, 2008 Page 391 of 962 REJ09B0465-0100 Section 12 Event Link Controller (6) (a) Operation of Port Buffer Registers Input Port-Groups When an event is input to an input port-group, the signal value of the external pin of the bit specified as the members of the input port-group is transferred to PDBF. If another event is input to the input port-group in this state, the current PDR value is transferred or not depending on the PGCOVE bit setting in PGC as described below. * PGCOVE = 0 (overwriting PDBF is disabled) If the PDBF value that has been transferred upon the latest event input has already been read by the CPU (or transferred by the DTC), the signal value of the external pin is transferred to PDBF. If not read, the signal value of the external pin is not transferred and the input event is invalid. * PGCOVE = 1 (overwriting PDBF is enabled) When another event is input to an input port-group, the signal value of the external pin is transferred to PDBF. (b) Output Port-Groups If an output port-group is specified so that it should output the PDBF value, the PDBF value is transferred to PDR when an event is input to the output port-group. In this case, only the values of the bits specified as the members of the output port-group are transferred If an output port-group is specified so that it should shift out the bit values in the group (PGCO bits = 1xx in PGC), the PDBF data is transferred to PDR, and then the PDR value is shifted bit by bit from MSB to LSB. The initial value to be output to the port-group should be provided in PDBF. Examples of operation are shown in figures 12.5 and 12.6. (7) Restrictions on Writing to PDR or PDBF by CPU When the ELCON bit in ELCR is set to 1, write access to the following registers is invalid. * If bits are specified as members of the input port-group and the event-linkage is set for the port-group, write access to the relevant bits in PDBF by the CPU is invalid. * If port bits are specified as members of the output port-group, write access to the relevant bits in PDR by the CPU is invalid. * If a port bit is specified as an output single-port and the event-linkage is set (by ELSR) for the port, write access to the relevant bit in PDR by the CPU is invalid. Rev. 1.00 Oct. 03, 2008 Page 392 of 962 REJ09B0465-0100 Section 12 Event Link Controller External signal PDBF P33 P32 P31 P30 1 0 1 0 PDR 0 0 0 0 PDBF 1 0 1 0 PDR 1 0 1 0 Port P33 P32 P31 P30 Event signal Note: P30 to P33 are specified as an output port-group. Figure 12.5 Event Linkage related to Output Port-Groups PDBF P33 P32 P31 1 0 0 0 PDR 0 0 0 0 PDR 1 0 0 0 PDR 0 1 0 0 PDR 0 0 1 0 PDR 0 0 0 1 P30 P33 P32 P31 P30 Event signal Note: P30 to P33 are specified as an output port-group. Figure 12.6 Bit-Shifting Operation of Output Port-Groups Rev. 1.00 Oct. 03, 2008 Page 393 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.3.6 Event-Generation Timer The event-generation timer can generate an event at specified interval. The generated event can be connected to another module. The features of the timer are given below. * The interval can be generated using the 16-bit free-running counter. * The delay time (of 0 to 3 counter clock cycles) can be set, which is the time from the set eventgeneration timing (= interval) to actual generation of the event. * Four-channel event output is available (figure 12.8). ELTMCR ELTMSB ELTMDR Internal clock (/8192 to ) ELC ELTMCNT 32768 cycles One cycle Channel 0 Output delay circuit 0 Internal data bus ELC timer event 0 Output delay circuit 1 ELC timer event 1 Output delay circuit 2 ELC timer event 2 Output delay circuit 3 ELC timer event 3 ELTMSA Channel 1 Channel 2 Channel 3 Figure 12.7 Block Diagram of Event-Generation Timer Rev. 1.00 Oct. 03, 2008 Page 394 of 962 REJ09B0465-0100 Section 12 Event Link Controller ELC ELTMDR ELC/one cycle C D Q D C Q D C Q Latch ELC/32768 cycles Latch Latch ELC timer event n (n = 0 to 3) Channel x selectable frequency (16 counter cycles) Event output x Delay time can be specified using ELTMDR. Figure 12.8 Operation of Event-Generation Timer Rev. 1.00 Oct. 03, 2008 Page 395 of 962 REJ09B0465-0100 Section 12 Event Link Controller 12.3.7 Procedure for Linking Events The following describes the procedure for linking events. 1. Set the operation of the module to which an event is to be linked. 2. To the ELSRn register corresponding to the module to which an event signal is to be linked, set the number of the event signal. 3. If events are to be linked to timers, set the ELOPA to ELOPC registers corresponding to the timers as required. 4. Set the ELCON bit in ELCR to 1, which enables linkage of all the events. 5. Set the operation of the module from which an event is output, and start the module. This allows the event output from the module to start the module to which an event is linked as specified. 6. To stop event linkage of some independent modules, set B'00000000 to the ELSn7 to ELSn0 bits in the ELSRn corresponding to the modules. To stop linkage of all the events, clear the ELCON bit in ELCR to 0. If events are linked to ports, set the registers corresponding to the ports as below. PDR: Set the initial values of the output ports. PCR: Set the I/O direction of the ports. PGR: If ports are used as a port-group, set the ports (in bit units) to be grouped. PGC: Set the operation of the port-group. PEL: If ports are used as single-ports, set the ports, the operation of the ports when an event is input, and the condition when an event is generated. Rev. 1.00 Oct. 03, 2008 Page 396 of 962 REJ09B0465-0100 Section 13 Timer RA Section 13 Timer RA The timer RA is an 8-bit reload timer with a prescaler. The prescaler and the timer are comprised of a reload register and a counter, respectively. 13.1 Overview * Operating mode: 5 modes Timer mode: Counts internal count sources. Pulse output mode: Counts internal count sources and produces a toggle output in timer underflow. Event counter mode: Counts external events. Pulse width measurement mode: Measures the pulse width of external pulses. Pulse cycle measurement mode: Measures the pulse cycle of external pulses. * Selection of nine count sources , /2, /8, /32, /64, /128, 40, sub, or an external event input to the TRAIO pin. * An interrupt generated on an underflow of the counter Data bus TCK[2:0] /8 40 /2 sub /32 /64 /128 Pulse width measurement mode TRAPRE Pulse cycle measurement mode Reload Timer mode TCKCUT register Pulse output mode TSTART Counter Event count mode Pulse width measurement mode Pulse cycle measurement mode TRAIO pin Digital filter TIPF[1:0] Polarity switching Count control circuit Measurement-complete signal Pulse output mode TOPCR TEGSEL Q Q TRATR Reload register Underflow signal Counter Timer RA interrupt Toggle flipflop CK CLR TOENA TRAO pin Write to TRAMR register Write 1 to TSTOP bit Figure 13.1 Block Diagram of Timer RA Rev. 1.00 Oct. 03, 2008 Page 397 of 962 REJ09B0465-0100 Section 13 Timer RA Table 13.1 shows the timer RA input/output pins. Table 13.1 Pin Configuration Name Timer RA input/output Timer RA output Abbreviation TRAIO TRAO I/O I/O Output Function External event input and pulse input/output Inverted pulse output of TRAIO output 13.2 Register Descriptions The timer RA has the following registers: * * * * * * Timer RA control register (TRACR) Timer RA I/O control register (TRAIOC) Timer RA mode register (TRAMR) Timer RA prescaler register (TRAPRE) Timer RA timer register (TRATR) Timer RA interrupt request status register (TRAIR) Rev. 1.00 Oct. 03, 2008 Page 398 of 962 REJ09B0465-0100 Section 13 Timer RA 13.2.1 Timer RA Control Register (TRACR) Address: H'FF06F0 Bit: b7 Value after reset: 0 b6 0 b5 TUNDF 0 b4 TEDGF 0 b3 0 b2 TSTOP 0 b1 TCSTF 0 b0 TSTART 0 Bit 7, 6 5 Symbol TUNDF Bit Name Reserved Description R/W These bits are read as 0. The write valued should be 0. R/W [Setting condition] Timer RA underflow flag * When timer RA underflows from H'00 to H'FF. [Clearing condition] * When 0 is written to this bit* 4 TEDGF [Setting condition] Valid edge R/W detection flag * When the pulse width measurement is completed with TSTART in TRACR = 1, in pulse width measurement mode. * When the timer RA prescaler underflows at the second time after a valid edge of the measurement pulse is input, in pulse cycle measurement mode. [Clearing condition] * When 0 is written to this bit* R/W Reserved Timer RA count forced stop This bit is read as 0. The write value should be 0. 0: Timer RA counting is continued. 1: Timer RA counting is forcedly stopped. 3 2 TSTOP Rev. 1.00 Oct. 03, 2008 Page 399 of 962 REJ09B0465-0100 Section 13 Timer RA Bit 1 Symbol TCSTF Bit Name Timer RA count status flag Description 0: Timer RA counting has been stopped. 1: Timer RA counting is in progress. [Setting condition] * When 1 is written to TSTART and counting is started. * The start of counting after ELOPA of the event link controller is selected counting by timer RA, the specified event is occurred, and the TSTART bit is set to 1. [Clearing condition] * * When 0 is written to TSTART and counting is stopped. When 1 is written to TSTOP and counting is stopped. R/W R 0 Note: TSTART Timer RA count start 0: Timer RA counting is stopped. 1: Timer RA counting is started. R/W 1. A MOV instruction should be used to write 0 to this register. 2. The timer RA registers should not be accessed until the TCSIF bit changes after the TSTART bit is set, apart from TRACR which can be read at any time during timer operation. TRACR controls the timer RA counter and indicates the timer RA state. * TSTOP bit (timer RA count forced stop) Setting this bit to 1 initializes the counter of the timer and the prescaler, bits TSTART and TCSTF, and timer outputs. This bit is always read as 0. Rev. 1.00 Oct. 03, 2008 Page 400 of 962 REJ09B0465-0100 Section 13 Timer RA 13.2.2 Timer RA I/O Control Register (TRAIOC) Address: H'FF06F1 Bit: b7 TIOGT[1:0] Value after reset: 0 0 0 b6 b5 TIPF[1:0] 0 b4 b3 TIOSEL 0 b2 TOENA 0 b1 TOPCR 0 b0 TEDGSEL 0 Bit 7, 6 Symbol Bit Name Description R/W TIOGT[1:0] TRAIO event input control 00: Input control is not performed. (Events are always R/W enabled.) 01: Input control is performed. (Events are enabled when IRQ2 input is high.) 10: Setting prohibited 11: Setting prohibited 5, 4 TIPF[1:0] TRAIO input filter select 00: No filter operation 01: Filtered (Sampled at ) 10: Filtered (Sampled at /8) 11: Filtered (Sampled at /32) These bits should be set to B'00 in timer mode and pulse output mode. R/W 3 2 TIOSEL TOENA TRAIO input select TRAO output enable 0: Input from the TRAIO pin 1: Input from the LIN 0: TRAO outputs are disabled. 1: TRAO outputs are enabled. This bit should be set to 0 except in event counter mode and pulse output mode. R/W R/W 1 TOPCR TRAIO output control 0: TRAIO outputs are enabled. 1: TRAIO outputs are disabled. This bit should be set to 0 except in pulse output mode. R/W Rev. 1.00 Oct. 03, 2008 Page 401 of 962 REJ09B0465-0100 Section 13 Timer RA Bit 0 Symbol TEDGSEL Bit Name Description Timer mode This bit should be set to 0. Pulse output mode 0: The initial value of TRAIO output is set at a high level. 1: The initial value of TRAIO output is set at a low level. * Event count mode 0: Counter incremented at the TRAIO input rising edge. The initial value of TRAIO output is set at a low level. 1: Counter incremented at the TRAIO input falling edge. The initial value of TRAIO output is set at a high level. * Pulse width measurement mode 0: Measures the low-level width of TRAIO input. 1: Measures the high-level width of TRAIO input. * Pulse cycle measurement mode 0: Measures from the rising edge of the measurement pulse to the next rising edge. 1: Measures from the falling edge of the measurement pulse to the next falling edge. R/W R/W Input/output * polarity switch * Note: When TCSTF = 1, do not rewrite this register. * TIOGT1 bit and TIOGT0 bit (TRAIO event input control 1 and 0) These bits control input events in event counter mode. * TIPF1 bit and TIPF0 bit (TRAIO input filter select 1 and 0) If filtered operation is selected, the input is determined when the same value is sampled three times in succession from the TRAIO pin. Rev. 1.00 Oct. 03, 2008 Page 402 of 962 REJ09B0465-0100 Section 13 Timer RA 13.2.3 Timer RA Mode Register (TRAMR) Address: H'FF06F2 Bit: b7 TCKCUT Value after reset: 0 0 b6 b5 TCK[2:0] 0 0 b4 b3 b2 b1 TMOD[2:0] b0 0 0 0 0 Bit 7 6 to 4 Symbol TCKCUT TCK[2:0]*2 Bit Name Description R/W R/W R/W Timer RA count 0: Count source is supplied. source cutoff 1: Count source is cut off. Timer RA count 000: source select 001: /8 010: /40 011: /2 100: sub 101: /32 110: /64 111: /128 Reserved This bit is read as 0. The write value should be 0. 000: Timer mode Timer RA operating mode 001: Pulse output mode select 010: Event count mode 011: Pulse width measurement mode 100: Pulse cycle measurement mode 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited 3 2 to 0 TMOD[2:0] R/W Note: 1. The counting should be stopped (when both the TSTART and TCSTF bits in TRACR are 0) when this register is modified. 2. If the internal /40 clock is selected, the high-speed on-chip oscillator must be operating. As long as the internal 40 clock is selected, do not stop the high-speed onchip oscillator. * TCK2 bit and TCK0 bit (timer RA count source select) A count source is selected if the mode is not the event count mode. * TMOD2 bit to TMOD0 bit (timer RA operating mode select) Writing to TRAMR initializes the output level. Rev. 1.00 Oct. 03, 2008 Page 403 of 962 REJ09B0465-0100 Section 13 Timer RA 13.2.4 Timer RA Interrupt Enable Status Register (TRAIR) Address: H'FF06F5 Bit: b7 TRAIE Value after reset: 0 b6 TRAIF 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 0 Bit 7 Symbol TRAIE Bit Name Description R/W R/W Timer RA 0: Timer RA interrupt requests are disabled. interrupt 1: Timer RA interrupt requests are enabled. request enable Timer RA interrupt request flag [Setting condition] * * * When the timer RA underflows. When the input pulse measurement is completed in pulse width measurement mode. When the timer RA prescaler underflows at the second time after a valid edge of measurement pulse is input, in pulse cycle measurement mode. When 1 is read from the bit and then 0 is written to. When the DTC is activated by a TRAIF interrupt, and the DISEL bit in MRB of the DTC is 0. 6 TRAIF R/W [Clearing condition] * * 5 to 0 Reserved This bit is read as 0. The write value should be 0. Rev. 1.00 Oct. 03, 2008 Page 404 of 962 REJ09B0465-0100 Section 13 Timer RA 13.2.5 Timer RA Prescaler Register (TRAPRE) Address: H'FF06F3 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 TRAPRE consists of a reload register and an 8-bit counter, each with an initial value of H'FF. If a down-count is performed using the count source selected with TRAMR and an underflow occurs, the value of the reload register is loaded to the counter. The underflow becomes a count source for TRATR. The reload register and the counter are assigned to the same address. On write, a value is written to the reload register, and on read, a counter value is read. During a write to TRAPRE the load timing from the reload register to the counter differs between counting in progress and counting stopped. Writing to TRAPRE when counting is stopped causes the data to be written to both the reload register and the counter. Writing to TRAPRE during counting causes the new value to be written to the reload register after four cycles of count source, and to be loaded to the counter in synchronization with the next count source. Rev. 1.00 Oct. 03, 2008 Page 405 of 962 REJ09B0465-0100 Section 13 Timer RA 13.2.6 Timer RA Timer Register (TRATR) Address: H'FF06F4 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 TRATR consists of a reload register and an 8-bit counter, each with an initial value of H'FF. TRATR performs a down-count of the prescaler underflows. When an underflow occurs in TRATR, the value of the reload register is loaded to the counter and a timer RA interrupt request is generated at the same time. The reload register and the counter are assigned to the same address. On write, a value is written to the reload register, and on read, a counter value is read. However, on read in pulse cycle measurement mode, a value in the read buffer is read. During a write to TRATR the load timing from the reload register to the counter differs between counting in progress and counting stopped. Writing to TRATR when counting is stopped causes the data to be written to both the reload register and the counter. Writing to TRATR during counting causes the new value to be written to the reload register in synchronization with an underflow of the prescaler first after four counts of the count source, and to be loaded to the counter in synchronization with the next underflow of the prescaler. TRAPRE and TRATR should not be set to H'00 at the same time. Rev. 1.00 Oct. 03, 2008 Page 406 of 962 REJ09B0465-0100 Section 13 Timer RA 13.3 13.3.1 (1) Operation Operations Common to Various Modes Starting and Stopping Operation Writing the value 1 to the TSTART bit in TRACR starts counting in a set operating mode; writing the value 0 to the TSTART bit stops the counting. The prescaler counts down in the counter clock cycle to be input into the prescaler. The timer counts down using the underflow of the prescaler as a count source. (2) Forced Termination of Operation Writing 1 to the TSTOP bit in TRACR stops the counting forcibly. When the counting is stopped, the timer counter, the prescaler counter, and any associated flags are initialized while the reload registers of the prescaler and the timer counter are retained. (3) Interrupt Request An interrupt request is generated on the underflow of the timer RA counter. (4) Reading and Writing Count Value Reading registers TRAPRE and TRATR reads count values from each register. If a write is performed to TRAPRE or TRATR when the counting is stopped, a specified value is written to both the reload register and the counter. If a write is performed to the TRAPRE register during counting, first a set value is written to the reload register in synchronization with the count source after four cycles of count source, and the set value is then transferred to the prescaler counter in synchronization with the next count source. If a write is performed to the TRATR register, a set value is written to the reload register in synchronization with the underflow of the prescaler, and the set value is transferred to the timer counter in synchronization the next underflow of the prescaler. For this reason, if a write is performed to TRAPRE or TRATR during counting, the value of the counter is not updated immediately after the execution of the write command. Figure 13.2 shows an example operation where a count value is rewritten when the timer RA is counting. Rev. 1.00 Oct. 03, 2008 Page 407 of 962 REJ09B0465-0100 Section 13 Timer RA Write H'01 to TRAPRE and H'25 to TRATR by a program Count source After a write, reload register is written to after four counts of count source. Reload register for timer RA prescaler Previous value New value (H'01) Reloaded at the second count source Reloaded on underflow Counter for H'06 timer RA prescaler H'05 H'04 H'03 H'02 H'01 H'01 H'00 H'01 H'00 H'01 H'00 H'01 H'00 Reload register is written to at the first underflow after a write. Reload register for timer RA Previous value New value (H'25) Reloaded at the second underflow Timer RA counter H'03 H'25 H'24 TRAIF in TRAIR "0" IR bit does not change until an underflow occurs with the new value. Figure 13.2 Rewriting Count Value When Timer RA Counting is in Progress 13.3.2 Timer Mode This mode counts internal clocks as a count source. Setting the TMOD[2:0] bits in TRAMR to B'000 activates the timer mode operation. A count source is selected in terms of the TCK[2:0] bits in TRAMR. 13.3.3 Pulse Output Mode This mode counts internal clocks as a count source, and toggle-outputs pulses from the TRAIO pin each time the counter underflows. Setting the TMOD[2:0] bits in TRAMR to B'001 activates pulse the output mode operation. A count source is selected using the TCK[2:0] bits in TRAMR. The initial output value of the pin is set using the TEDGSEL bit in TRAIOC. By setting the TOENA bit in TRAIOC, a reverse output can be output from the TRAO pin to the TRAIO pin. Rev. 1.00 Oct. 03, 2008 Page 408 of 962 REJ09B0465-0100 Section 13 Timer RA 13.3.4 Event Counter Mode This mode counts external events that are input from the TRAIO pin as a count source. Setting the TMOD[2:0] bits in TRAMR to B'010 activates the event-counter mode operation. By setting the TEDGSEL bit in TRAIOC, it is possible to specify whether counting is to be performed on the rising or falling edge of an input event from the TRAIO pin. Also, by setting the TIOGT[1:0] bits in TRAIOC, a function enables external event input when the IRQ2 pin is at a high level. Setting the TIPF[1:0] bits in TRAIOC allows applying a filter to external event input. Similar to the pulse output operation mode, a toggle can be output from the TRAO pin in synchronization with an underflow of the timer counter. In event counter mode, even if 1 is written to the TSTART bit, the value of the TCSTF bit will not become 1 unless the corresponding event signal is input. If the event signal is input while TCSTF = 0, the counter value will be the number of times the event has occurred minus 3. If the event signal is input while TCSTF=1, the number time the event has occurred = counter value. 13.3.5 Pulse Width Measurement Mode This mode measures the pulse width of external signals that are input from the TRAIO pin. Setting the TMOD[2:0] bits in TRAMR to B'011 activates the pulse width measurement mode operation. A count source is selected in terms of the TCK[2:0] bits in TRAMR. The TEDGSEL bit in TRAIOC can be used to specify whether the low-level width or the high-level width of input pulses is to be measured. Setting the TIPF[1:0] bits in TRAIOC allows applying a filter to external pulse input. Figure 13.3 shows an operation example of pulse width measurement mode. Rev. 1.00 Oct. 03, 2008 Page 409 of 962 REJ09B0465-0100 Section 13 Timer RA 0 = Contents of TRATR (upper) and TRAPRE (lower) registers H'FFFF Start measurement. Underflow Counter value (hexadecimal) n Measurement is stopped. Measurement is stopped. H'0000 Set to 1 by a program. TSTART in TRACR "1" "0" Start Start Measurement pulse (TRAIO pin input) "1" "0" Set to 0 by a program. TRAIF in TRAIC "1" "0" Set to 0 by a program. TEDGF in TRACR "1" "0" Set to 0 by a program. "1" "0" TUNDF in TRACR When a high level is specified for measuring the pulse width (TEDGSEL = 1). Figure 13.3 Operation Example of Pulse Width Measurement Mode Rev. 1.00 Oct. 03, 2008 Page 410 of 962 REJ09B0465-0100 Section 13 Timer RA 13.3.6 Pulse Cycle Measurement Mode This mode measures the cycle of external pulses that are input from the TRAIO pin. Setting the TMOD[2:0] bits in TRAMR to B'100 activates the pulse cycle measurement operation. The TEDGSEL in TRAIOC can be used to specify whether the period from the falling edge to another falling edge of the input pulse of the TRAIO pin is to be measured or the period from the rising edge to another rising edge is to be measured. Setting the TIPF[1:0] bits in TRAIOC also enables to apply a filter to external pulse input. Count sources are selected using the TCK[2:0] bits in TRAMR. After the start of timer counting, each time a valid input edge is input from the TRAIO pin, a value is transferred from the counter of the timer RA to the read buffer in synchronization with the underflow of the timer RA prescaler. The value in the read buffer is retained until the timer RA register is read. Also, after a value is transferred to the read buffer, a value is transferred from the reload register to the counter in synchronization with the next underflow of the timer RA prescaler. Reading of the read buffer should not be performed until the TEDGF bit in TRACR is set to 1. An interrupt request is generated either when the TEDGF bit in TRACR is set to 1 or when the timer RA counter underflows. For pulse input to the TRAIO pin, pulses with a cycle greater than double the cycle of the timer RA prescaler should be input. Also, input pulses for which the high pulse width and the low pulse width are greater than the cycle of the timer RA prescaler. If pulses with a short cycle are input, the input is ignored in some cases. Figure 13.4 shows an operation example of pulse cycle measurement mode. Rev. 1.00 Oct. 03, 2008 Page 411 of 962 REJ09B0465-0100 Section 13 Timer RA 13.3.7 Operation through an Event Link Using the event link controller (ELC), timer RA can be made to operate in the following ways in relation to events occurring in other modules. (1) Starting Counter Operation The start of counting operations by timer RA can be selected by the ELOPA register of the ELC. When the event specified in ELSR0 occurs, the TSTART bit in the TRACR is set to 1, which starts counting by timer RA. However, if the specified event occurs when the TCSTF flag has already been set to 1, that event is not effective. (2) Counting Events The counting of events by timer RA can be selected by the ELOPA register of the ELC. When the event specified in ELSR0 occurs, event-counter operation proceeds with that event as the source to drive counting, regardless of the setting in TRAMR. When event-counter operation is to be employed, set the TSTART bit in TRACR to 1 beforehand. When the value of the counter is read, the value read out is the actual number of input events minus three. Rev. 1.00 Oct. 03, 2008 Page 412 of 962 REJ09B0465-0100 Section 13 Timer RA Timer RA prescaler underflow signal Set to 1 by a program. TSTART in TRACR "1" "0" Start counting Measurement pulse (TRAIO pin input) "1" "0" TRA reload TRATR content TRA reload H'01 H'00 H'0F H'0E H'0F H'0E H'0D H'0F H'0E H'0D H'0C H'0B H'0A H'09 H'0F H'0E H'0D Underflow Retained Read buffer content *1 H'0F H'0E H'0D H'0B H'0A Retained H'09 H'0D H'01 H'00 H'0F H'0E TRA read (*3) *2 *2 TEDGF in TRACR "1" "0" Set to 0 by a program. TRAIF in TRAIR "1" "0" *4 *6 Set to 0 by a program. *5 TUNDF in TRACR "1" "0" Set to 0 by a program. Measurement condition: The initial value of TRATR is H'0F and the width from the rising edge to the next rising edge of measurement pulse is measured (TEDGSEL = 0). Notes: 1. When TRATR is read in pulse cycle measurement mode, the value in the read buffer can be read. 2. The TEDGF bit in TRACR is set to 1 (valid edge exists) on the second underflow of the timer RA prescaler after a valid edge of the measurement pulses is input. 3. TRATR should be read between the TEDGF bit setting to 1 (valid edge exists) and the next valid edge input. The value in the read buffer is retained until TRATR is read. Therefore, if the value is not read before the next valid edge input, the measurement result of the previous cycle remains. 4. The MOV instruction should be used to write 0 to the TEDGF bit in TRACR using a program. Here, 1 should be written to the TUNDF bit . 5. The MOV instruction should be used to write 0 to the TUNDF bit in TRACR using a program. Here, 1 should be written to the TEDGF bit. 6. If an underflow of timer RA and reloading of timer RA by valid edge input occur at the same time, both the TUNDF and TEDGF bits are set to 1. In this case, the effectiveness of the TUNDF bit should be determined according to the read buffer contents. Figure 13.4 Operation Example of Pulse Cycle Measurement Mode Rev. 1.00 Oct. 03, 2008 Page 413 of 962 REJ09B0465-0100 Section 13 Timer RA 13.4 Usage Notes 1. The prescaler and timer are read out per byte inside the microcomputer even when they are read out in 16-byte unit. Therefore, the timer value can be updated while those two registers are read out. 2. The TEDGF and TUNDF bits in TRACR used in pulse width and pulse cycle measurement modes assume the value 0 when 0 is written by a program and do not change if 1 is written. If one flag is set to 0 by a program, use the MOV instruction to write 1 to the other flag. In this manner, unintended flag changes can be prevented. 3. When a transition is made to pulse width or pulse cycle measurement mode from another mode, the TEDGF and TUNDF bits are undefined. Timer RA counting should be started by writing 0 to the TEDGF and TUNDF bits. 4. In some cases, the TEDGF bit becomes 1 on the first timer RA prescaler underflow signal that is generated after the start of counting. 5. When using the pulse cycle measurement mode, set the TEDGF bit to 0 by allowing a length of time 2 cycles or greater of the timer RA prescaler after the counting process is started. 6. After 1 is written to the TSTART bit when counting is stopped, the TCSTF bit remains 0 for the number of cycle of count source. Registers associated with the timer RA except the TRACR for reading should not be accessed until the TCSTF bit becomes 1. Counting starts from a valid edge of the first count source after the TCSTF bit becomes 1. After 0 is written to the TSTART bit when counting is in progress, the TCSTF bit remains 1 for the number of cycle of count source. Registers associated with the timer RA except the TRACR for reading should not be accessed until the TCSTF bit becomes 0. Counting stops when the TCSTF bit becomes 0. 7. When writing successively to TRAPRE during counting (TCSTF=1), allow a minimum write interval of 4 cycles of count source. 8. When writing successively to TRATR during counting (TCSTF=1), allow a minimum write interval of 4 cycles of count source underflow. Rev. 1.00 Oct. 03, 2008 Page 414 of 962 REJ09B0465-0100 Section 14 Timer RB Section 14 Timer RB The timer RB is an 8-bit reload timer with an 8-bit prescaler. The prescaler and the timer are each comprised of a reload register and a counter. The timer RB has two reload registers: timer RB primary register and timer RB secondary register. 14.1 Overview * Four operating modes Timer mode: Counts either internal count sources or timer RA underflows. Programmable waveform generation mode: Outputs any pulse widths continuously. Programmable one-shot generation mode: Outputs one-shot pulses. Programmable wait one-shot generation mode: Outputs delayed one-shot pulses. * Selection of eight count sources , /2, /4, /8, /32, /64, /128, or an underflow of timer RA * An interrupt generated on an underflow of the timer RB counter Data bus Prescaler TCK[2:0] bits TCKCUT bit TRBPRE TRBSC TRBPR Timer counter 8 Timer RA underflow 2 4 32 64 128 Timer RB interrupt Counter Counter TMOD[1:0] = B'10 or B'11 TSTART bit TOSST bit TRGB pin Digital filter Polarity select INOSEG bit INOSTG bit TMOD[1:0] bits TOCNT TRBO pin TOPL Q Toggle flipflop CK Q CLR Write to TSTOP except in timer mode Figure 14.1 Block Diagram of Timer RB Rev. 1.00 Oct. 03, 2008 Page 415 of 962 REJ09B0465-0100 Section 14 Timer RB Table 14.1 shows the timer RB input/output pins. Table 14.1 Pin Configuration Name TRGB TRBO I/O Input Output Function External trigger input Successive pulse output or one-shot pulse output 14.2 Register Descriptions The timer RB has the following registers: * * * * * * * * Timer RB control register (TRBCR) Timer RB one-shot control register (TRBOCR) Timer RB I/O control register (TRBIOC) Timer RB mode register (TRBMR) Timer RB interrupt request status register (TRBIR) Timer RB prescaler register (TRBPRE) Timer RB secondary register (TRBSC) Timer RB primary register (TRBPR) Rev. 1.00 Oct. 03, 2008 Page 416 of 962 REJ09B0465-0100 Section 14 Timer RB 14.2.1 Timer RB Control Register (TRBCR) Address: H'FFFFA0 Bit: b7 b6 b5 b4 b3 b2 TSTOP 0 b1 TCSTF 0 b0 TSTART 0 Value after reset: 0 0 0 0 0 Bit 7 to 3 2 1 Symbol TSTOP TCSTF Bit Name Reserved Count forced stop Count status flag Description These bits are read as 0. The write value should be 0. 0: Timer RB counting is continued. 1: Timer RB counting is forcedly stopped. 0: Timer RB counting is stopped. 1: Timer RB counting is in progress. [Setting conditions] * * When 1 is written to TSTART and counting is started. The start of counting after ELOPA of the event link controller is selected counting by timer RB, the specified event is occurred, and the TATRT bit is set to 1. When 0 is written to TSTART and counting is stopped. When 1 is written to TSTOP and counting is stopped. R/W R/W R [Clearing conditions] * * 0 TSTART Count start 0: Timer RB counting is stopped. 1: Timer RB counting is started. R/W Notes: 1. A MOV instruction should be used to write to this register. 2. The timer RB registers should not be accessed until the TCSTF bit changes after the TSTART bit is set, apart from TRBCR which can be read at any time during timer operation. * TSTOP bit (count forced stop) Setting this bit to 1 stops counting forcibly. At this time, the counter of the timer RB prescaler and the timer RB counter are initialized. Also, bits TSTART and TCSTF in TRBCR, bits TOSSTF, TOSSP, TOSST in TRBOCR, and TRBO outputs are initialized. The reload register of the prescaler and the timer RB counter are hold. This bit is always read as 0. Rev. 1.00 Oct. 03, 2008 Page 417 of 962 REJ09B0465-0100 Section 14 Timer RB 14.2.2 Timer RB One-Shot Control Register (TRBOCR) Address: H'FFFFA1 Bit: b7 Value after reset: 0 b6 0 b5 0 b4 0 b3 0 b2 TOSSTF 0 b1 TOSSP 0 b0 TOSST 0 Bit 7 to 3 2 Symbol TOSSTF Bit Name Reserved One-shot status flag Description R/W These bits are read as 0. The write value should be 0. 0: Timer RB one-shot function has been stopped. 1: Timer RB one-shot function is active (including wait time). [Setting conditions] * * * * * * When 1 is written to the TOSST bit. When trigger inputs to the TRGB pin are enabled. When 1 is written to the TOSSP bit. When 0 is written to the TSTART bit in TRBCR. When 1 is written to the TSTOP bit in TRBCR. When the timer counter reaches H'00 and the reloading is performed. R [Clearing conditions] [In programmable one-shot generation mode] [In programmable wait on-shot generation mode] When the counter value reaches H'00 during the secondary counting and the reloading is performed. 1 0 Note: TOSSP*1 TOSST* 2 One-shot stop 0: Timer RB counting is not stopped. 1: Timer RB counting is stopped. One-shot start 0: Timer RB counting is stopped. 1: Timer RB counting is started. R/W R/W 1. The TOSSP bit should be modified to 1 when the TOSSTF bit is 1. 2. The TOSST bit should be modified to 1 when the TOSSTF bit is 1. Rev. 1.00 Oct. 03, 2008 Page 418 of 962 REJ09B0465-0100 Section 14 Timer RB * TOSSP bit (one-shot stop) Writing 1 to this bit stops the timer counting. This bit is always read as 0 * TOSST bit (one-shot start) In programmable one-shot generation mode or programmable wait one-shot generation mode, writing 1 to this bit starts the timer counting and one-shot pulse output in synchronization with the count source. This bit is always read as 0. 14.2.3 Timer RB I/O Control Register (TRBIOC) Address: H'FFFFA2 Bit: b7 Value after reset: 0 b6 0 0 b5 TIPF[1:0] 0 b4 b3 INOSEG 0 b2 INOSTG 0 b1 TOCNT 0 b0 TOPL 0 Bit 7, 6 5, 4 Symbol TIPF[1:0] Bit Name Reserved TRGB input filter select Description These bits are read as 0. The write value should be 0. 00: No filter operation 01: Filtered (Sampled at ) 10: Filtered (Sampled at /8) 11: Filtered (Sampled at /32) These bits should be set to B'00 for timer mode or pulse output mode. R/W R/W 3 2 INOSEG INOSTG One-shot trigger polarity select One-shot trigger control 0: Triggered at a falling edge. 1: Triggered at a rising edge. 0: The one-shot trigger function for the TRGB pin is disabled. 1: The one-shot trigger function for TRGB pin is enabled. R/W R/W 1 TOCNT Timer RB output switch 0: Waveform is output from timer RB. 1: Waveform output is disabled. R/W Rev. 1.00 Oct. 03, 2008 Page 419 of 962 REJ09B0465-0100 Section 14 Timer RB Bit 0 Symbol TOPL Bit Name Timer RB output level select Description Programmable Waveform Generation Mode 0: A high-level signal is output in primary period, a low-level signal in secondary period and a lowlevel signal when the timer stops. 1: A low-level signal is output in primary period, a high-level signal in secondary period, and a high-level signal when the timer stops. Programmable one-shot generation mode 0: A high-level signal is output for one-shot pulse output and a low-level signal when the timer stops. 1: A low-level signal is output for one-shot pulse output and a high-level signal when the timer stops. Programmable wait one-shot generation mode 0: A high-level signal is output for one-shot pulse output and a low-level signal during the wait time or the time when the timer stops. 1: A low-level signal is output for one-shot pulse output and a high-level signal during the wait time or the time when the timer stops. This bit should be 0 in timer mode. R/W R/W * INOSEG bit (one-shot trigger polarity select) Selects an edge for the one-shot trigger signal input from the TRGB pin in programmable oneshot generation mode or programmable wait one-shot generation mode. This bit should be 0 in timer mode or programmable waveform generation mode. * INOSTG bit (one-shot trigger control) Enables or disables one-shot trigger signal input from the TRGB pin. This bit should be 0 in timer mode or programmable waveform generation mode. * TOCNT bit (timer RB output switch) For TRBO output state or output change conditions in each mode, see section 14.3.6, TOCNT Settings and Pin State Update Conditions. * TOPL bit (timer RB output level select) This bit should be 0 in timer mode. Rev. 1.00 Oct. 03, 2008 Page 420 of 962 REJ09B0465-0100 Section 14 Timer RB 14.2.4 Timer RB Mode Register (TRBMR) Address: H'FFFFA3 Bit: b7 TCKCUT Value after reset: 0 0 b6 b5 TCK[2:0] 0 0 b4 b3 TWRC 0 b2 0 0 b1 TMOD[1:0] 0 b0 Bit 7 Symbol TCKCUT* 1 Bit Name Count source cutoff Count source select Description 0: Timer RB clock source is supplied. 1: Timer RB clock source is cut off. 000: 001: /8 010: Underflow of timer RA 011: /2 100: 4 101: /32 110: /64 111: /128 R/W R/W R/W 6 to 4 TCK[2:0]* 1 3 2 1, 0 TWRC 2 Write control Reserved 0: Both the reload register and counter are written to. 1: Only the reload register is written to. This bit is read as 0. The write value should be 0. 00: Timer mode 01: Programmable waveform generation mode 10: Programmable one-shot generation mode 11: Programmable wait one-shot generation mode R/W TMOD[1:0]* Operating mode select Notes: 1. A count source should not be switched or cut off during counting. The count source should be switched or cut off when both the TSTART and TCSTF bits in TRBCR are 0 (when the timer counting is stopped). 2. An operating mode should be selected when the counting is stopped (when both the TSTART and TCSTF bits in TRBCR are 0). * TWRC bit (write control) Controls the timing when the counter reflects the value of the reload register. This bit should be 1 except in timer mode. Rev. 1.00 Oct. 03, 2008 Page 421 of 962 REJ09B0465-0100 Section 14 Timer RB 14.2.5 Timer RB Interrupt Enable Status Register (TRBIR) Address: H'FFFFA7 Bit: b7 TRBIE Value after reset: 0 b6 TRBIF 0 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 Bit 7 6 Symbol TRBIE TRBIF Bit Name Interrupt enable Description 0: Timer RB interrupt requests are disabled. 1: Timer RB interrupt requests are enabled. R/W R/W R/W Interrupt request flag [Setting conditions] Timer mode * * When the timer RA underflows. Programmable waveform generation mode A half cycle of the count source after the counter underflow in the secondary period Programmable one-shot generation mode. * A half cycle of the count source after the counter underflow A half cycle of the counter source after the counter underflow in the secondary period When 1 is read from the bit and then 0 is written to. When the DTC is activated by a TRBAIF interrupt, and the DISEL bit in MRB of the DTC is 0. Programmable wait one-shot generation mode * [Clearing conditions] * * 5 to 0 Reserved These bits are read as 0. The write value should be 0. Rev. 1.00 Oct. 03, 2008 Page 422 of 962 REJ09B0465-0100 Section 14 Timer RB 14.2.6 Timer RB Prescaler Register (TRBPRE) Address: H'FFFFA4 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 TRBPRE is a reload register for the timer RB prescaler. The timer RB prescaler consists of a reload register and an 8-bit counter. If a down-count is performed using the count source selected on TRBMR and an underflow occurs, the value of the reload register is loaded to the counter. The underflow becomes a count source for TRBTR. TRBPRE and the counter are assigned to the same address. On write, a value is written to the reload register, and on read, a counter value is read. During a write to TRBPRE, the load timing from the reload register to the counter differs between counting in progress and counting stopped by the setting of the TWRC bit in TRBMR. For details, see descriptions of each operating mode. The initial values of TRBPRE and the counter are H'FF. 14.2.7 Timer RB Secondary Register (TRBSC) Address: H'FFFFA5 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 TRBSC is an 8-bit write-only register that sets the secondary period for the timer RB counter. This register is used only in programmable waveform generation mode and programmable wait oneshot generation mode. This register is not used in timer mode or programmable one-shot generation mode. When TRBSC is written to in any operating mode where TRBSC is used, both the TRBSC and TRBPR should be written to in this order. Even if only TRBSC is to be modified, TRBPR should also be set to the previous value. The initial value is H'FF. Rev. 1.00 Oct. 03, 2008 Page 423 of 962 REJ09B0465-0100 Section 14 Timer RB 14.2.8 Timer RB Primary Register (TRBPR) Address: H'FFFFA6 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 TRBPR is an 8-bit reload register that sets the cycle or primary period for the timer RB counter. The timer RB counter consists of two registers, primary and secondary registers, and a counter. The primary register and counter are assigned to the same address. On write to TRBPR, a value is written to the reload register, and on read from TRBPR, a counter value is read. During a write to TRBPR the load timing from the reload register to the counter differs between counting in progress and counting stopped. For details, see descriptions of each operating mode. The initial values of TRBPR and the counter are H'FF. Rev. 1.00 Oct. 03, 2008 Page 424 of 962 REJ09B0465-0100 Section 14 Timer RB 14.3 14.3.1 Operation Timer Mode The internal clock pulses or timer RA underflows are counted as a count source in timer mode. When an underflow occurs on the timer RB counter, the value of TRBPR is reloaded and counting is continued. TRBOCR and TRBSC are not used in timer mode. A count source is selected with the TCK[2:0] bits in TRBMR. (1) Starting and Stopping Operation Writing the value 1 to the TSTART bit in TRBCR starts counting; writing the value 0 to the TSTART bit stops the counting. (2) Forced Termination of Operation Writing 1 to the TSTOP bit in TRBCR stops the counting forcedly. When the counting is forcedly stopped, the timer RB counter, the prescaler counter, and any associated flags are initialized. (3) Interrupt Request An interrupt request is generated on the underflow of the timer RB counter. (4) Reading and Writing Count Value Reading TRBPRE and TRBTR reads count values from each register. If a write is performed to TRBPRE or TRBTR when the counting is stopped, a specified value is written to both the reload register and the counter. If a write is performed to TRBPRE during counting when TWRC in TRBMR is 0, first a set value is written to the reload register, and the set value is then transferred to the prescaler counter in synchronization with the count source. If a write is performed to TRBPR, a set value is written to the reload register in synchronization with the underflow of the prescaler after four cycles of the count source of the prescaler, and the set value is transferred to the timer counter in synchronization with the next underflow of the prescaler. For this reason, if a write is performed to TRBPRE or TRBPR during counting when TWRC is 1, the value is written only to the reload register. Loading to the counter is performed in synchronization with the underflow of the prescaler or timer counter. Rev. 1.00 Oct. 03, 2008 Page 425 of 962 REJ09B0465-0100 Section 14 Timer RB 14.3.2 Programmable Waveform Generation Mode This mode alternately reloads and counts values of TRBPR and TRBSC, and produces toggle output from the TRBO pin each time the counter underflows. At the start of counting, this mode counts beginning with the value assigned to TRBPR. TRBOCR is not used when programmable waveform generation mode is used. (1) Starting and Stopping Operation Writing the value 1 to the TSTART bit in TRBCR starts counting; writing the value 0 to the TSTART bit stops the counting. (2) Forced Termination of Operation Writing 1 to the TSTOP bit in TRBCR stops the counting forcedly. When the counting is forcedly stopped, the timer RB counter, the prescaler counter, and any associated flags are initialized. (3) Interrupt Request An interrupt request is generated on the underflow of the timer RB counter during the secondary period counting. (4) Reading and Writing Count Value Reading TRBPRE and TRBTR reads count values from each register. If a write is performed to TRBPRE, TRBPR, or TRBSC when counting is stopped, set values are written to both the reload register and the counter. If a write is performed to TRBPRE, TRBPR, or TRBSC when counting is in progress, data is written only to the respective reload registers. The output of a waveform reflects a set value beginning with the next primary period after data is written to TRBPR. However, if writing to TRBSC or TRBPR proceeds when the value of the counter is H'00, updating of the waveform will be suspended for one cycle. Rev. 1.00 Oct. 03, 2008 Page 426 of 962 REJ09B0465-0100 Section 14 Timer RB Figure 14.2 shows an operation example of the timer RB in programmable waveform generation mode. Set to 1 by a program. TSTART in TRBCR "1" "0" Count source Timer RB prescaler underflow signal Timer RB secondary reload Timer RB primary reload Timer RB counter H'01 H'00 H'02 H'01 H'00 H'01 H'00 H'02 Set to 0 by a program. TRBIF in TRBIR "1" "0" Set to 0 by a program TOPL in TRBIOC "1" "0" Waveform output is started. Waveform output is inverted. Waveform output is started "1" TRBO pin output "0" Primary period Secondary period Primary period Conditions for the above operation: TRBPRE=H'01, TRBPR=H'01, TRBSC=H'02 TOCNT = 0 in TRBIOC (Timer RB waveform is output from the TRBO pin.) Figure 14.2 Operation in Programmable Waveform Generation Mode Rev. 1.00 Oct. 03, 2008 Page 427 of 962 REJ09B0465-0100 Section 14 Timer RB 14.3.3 Programmable One-Shot Generation Mode This mode outputs one-shot pulses from the TRBO pin, based on either program or external trigger input. When a trigger is generated, beginning with that point in time the timer operates only once for any length of time specified in TRBPR. TRBSC is not used in this mode. In this mode, TRBPRE or TRBPR should not be set to H'00. (1) Starting and Stopping Operation The counting is started when 1 is written to the TOSST bit in TRBOCR or a valid trigger signal is input to the TRGB pin after the TSTART bit in TRBCR is set to 1 and the TCSTF flag is set to 1. For a trigger input, the pulse must be longer than one cycle of the clock source for counting. The counting is stopped when reloading is performed with an underflow of the counter, when 1 is written to the TOSSP bit in TRBOCR, or when 0 is written to the TSTART bit in TRBCR. (2) Forced Termination of Operation Writing 1 to the TSTOP bit in TRBCR stops the counting forcedly. When the counting is forcedly stopped, the timer RB counter, the prescaler counter, and any associated flags are initialized. (3) Interrupt Request An interrupt request is generated on the underflow of the timer RB counter. (4) Reading and Writing Count Value Reading TRBPRE and TRBTR reads count values from each register. If a write is performed to TRBPRE or TRBPR when counting is stopped, set values are written to both the reload register and the counter. If a write is performed to TRBPRE or TRBPR during counting, data is written only to the respective reload registers. The value written to TRBPRE takes effect in synchronization with the underflow of the prescaler. The value written to TRBPR takes effect during the next one-shot pulse. Figure 14.3 shows an operation example of the timer RB in programmable one-shot generation mode. Rev. 1.00 Oct. 03, 2008 Page 428 of 962 REJ09B0465-0100 Section 14 Timer RB Set to 1 by a program. TSTART in TRBCR "1" "0" Write 1 to TOSST in TRBOCR. TOSSTF in TRBOCR Change to 0 at the end of counting. Change to 1 by the TRGB pin input trigger. TRGB pin Count source Timer RB prescaler underflow signal Start of counting Timer RB primary reload H'00 H'01 Start of counting Timer RB primary reload H'00 H'01 Timer RB counter H'01 Set to 0 by a program. TRBIF in TRBIOC "1" "0" Set to 0 by a program. TOPL in TRBIOC "1" "0" Start of waveform output "1" TRBO pin "0" End of waveform output Start of waveform output End of waveform output Conditions for the above operation: TRBPRE = H'01, TRBPR=H'01 TOPL = 0 and TOCNT = 0 in TRBIOC INOSTG = 1 (TRBG pin one-shot trigger function is enabled) INOSEG = 1 (Rising edge trigger) Figure 14.3 Operation in Programmable One-Shot Generation Mode Rev. 1.00 Oct. 03, 2008 Page 429 of 962 REJ09B0465-0100 Section 14 Timer RB 14.3.4 Programmable Wait One-Shot Generation Mode This mode outputs one-shot pulses from the TRBO pin after a fixed amount of time based on either program or external trigger input. When a trigger is generated, beginning with that point in time, pulses are output only once for any length of time set in TRBSC, after any length of time set in TRBPR. (1) Starting and Stopping Operation The counting is started when 1 is written to the TOSST bit in TRBOCR or a valid trigger signal is input to the TRGB pin after the TSTART bit in TRBCR is set to 1 and the TCSTF flag is set to 1. For a trigger input, the pulse must be longer than one cycle of the clock source for counting. The counting is stopped when reloading is performed with an underflow of the timer RB counter during the secondary period counting , when 1 is written to the TOSSP bit in TRBOCR, or when 0 is written to the TSTART bit in TRBMR. (2) Forced Termination of Operation Writing 1 to the TSTOP bit in TRBCR stops the counting forcedly. When the counting is forcedly stopped, the timer RB counter, the prescaler counter, and any associated flags are initialized. (3) Interrupt Request An interrupt request is generated on the underflow of the timer RB counter during the secondary period counting. (4) Reading and Writing Count Value Reading TRBPRE and TRBTR reads count values from each register. If a write is performed to TRBPRE, TRBPR, or TRBSC when counting is stopped, set values are written to both the reload register and the counter. If a write is performed to TRBPRE, TRBPR, or TRBSC during counting, data is written only to the respective reload registers. The value written to TRBPRE takes effect in synchronization with the underflow of the prescaler. The value written to TRBPR takes effect during the next one-shot pulse. After writing to TRBSC and TRBPR when TCSTF = 1 or TOSSTF = 0, if a write is successively performed to TRBSC and then to TRBPR, allow an interval of 5 cycles of the clock source for counting before writing 1 to the TOSST bit. In this mode, TRBPRE or TRBPR should not be set to H'00. Rev. 1.00 Oct. 03, 2008 Page 430 of 962 REJ09B0465-0100 Section 14 Timer RB Figure 14.4 shows an operation example of the timer RB in programmable wait one-shot generation mode. Set to 1 by a program. TSTART in TRBCR "1" "0" Change to 1 by writing 1 to TOSST in TRBOCR or by the TRGB pin input trigger. TOSSTF in TRBOCR "1" "0" Change to 0 at the end of counting. TRGB input pin Count source Timer RB prescaler underflow signal Start of counting Timer RB secondary reload Timer RB counter H'01 H'00 H'04 H'03 H'02 H'01 Timer RB primary reload H'00 01h Set to 0 by a program. TRBIF in TRBIR "1" "0" Set to 0 by a program. TOPL in TRBIOC "1" "0" Start of waiting "1" TRBO pin output "0" Start of waveform output End of waveform output Conditions for the above operation: TRBPRE = H'01, TRBPR = H'01, TRBSC = H'04 INOSTG = 1 (TRGB one-shot trigger function is enabled.) INOSEG = 1 (Rising edge trigger) Figure 14.4 Operation in Programmable Wait One-Shot Generation Mode Rev. 1.00 Oct. 03, 2008 Page 431 of 962 REJ09B0465-0100 Section 14 Timer RB 14.3.5 Timing at Which Values Take Effect in Prescaler or Counter Depending on TWRC Bit Depending on the value assigned to the TWRC bit in TRBMR, the timing at which the value written to TRBPRE, TRBPR, or TRBSC during timer operation takes effect in the counter can vary. If TWRC is set to 1 and value is written only to the register, the counter value is updated between cycles, thus preventing the occurrence of fractional cycles. In modes other than the timer mode, TWRC should be set to 1. Figure 14.5 shows operation examples on the prescaler and the counter when the value of TWRC is 0 and 1. If TCSTF is 1, even when TWRC is cleared to 0, any transfer to the prescaler or the counter is performed in synchronization with the count source; therefore, the counter value is not updated immediately after the execution of a write instruction. Rev. 1.00 Oct. 03, 2008 Page 432 of 962 REJ09B0465-0100 Section 14 Timer RB (1) TWRC=0 Write H'01 to TRBPRE and H'25 to TRBPR by program. Count source After a writing, data are written to the reload register after 4 cycles of the source for counting have elapsed. Reload register of timer RB prescaler Counter of timer RB prescaler H'06 Underflow of timer RB prescaler Previous value New value (H'01) Reloaded at the second count source Reloaded on underflow H'05 H'04 H'03 H'02 H'01 H'01 H'00 H'01 H'00 H'01 H'00 H'01 H'00 Reload register is written to at the first underflow after a write. Previous value New value (H'25) Reloaded at the second underflow of prescaler TRBPR Counter of timer RB H'03 H'25 H'24 (2) TWRC=1 Write H'01 to TRBPRE and H'25 to TRBPR by program. Count source After a writing, data are written to the reload register after 4 cycles of the source for counting have elapsed. Reload register of timer RB prescaler Counter of H'06 timer RB prescaler Underflow of timer RB prescaler Previous value Reloaded at the second count source H'05 H'04 H'03 H'02 H'01 H'00 New value (H'01) Reloaded on underflow H'01 H'00 H'01 H'00 H'01 H'00 H'01 H'00 Reload register is written to at the first underflow after a write. Previous value New value (H'25) Reloaded at underflow of prescaler TRBPR Counter of timer RB H'03 H'02 H'01 H'00 H'25 Figure 14.5 TWRC Settings and Operation of Prescaler and Counter Rev. 1.00 Oct. 03, 2008 Page 433 of 962 REJ09B0465-0100 Section 14 Timer RB 14.3.6 TOCNT Settings and Pin State Update Conditions Depending on the TOCNT bit in TRBIOC and the corresponding bit in PMR, the user can select whether the pin is used as a general I/O port or as a specific timer waveform output. In the case of timer mode, however, the pin operates as a general I/O port, irrespective of TOCNT bit settings. When the TOCNT bit is rewritten, the pin state is not updated immediately; the change takes effect when either of the following conditions occurs: Pin state update conditions: * When the TSTART bit in TRBCR is changed from 0 to 1 * When TRBPR is reloaded to the counter Rev. 1.00 Oct. 03, 2008 Page 434 of 962 REJ09B0465-0100 Section 14 Timer RB 14.3.7 Operation through an Event Link Using the event link controller (ELC), timer RB can be made to operate in the following ways in relation to events occurring in other modules. (1) Starting Counter Operation The start of counting operations by timer RB can be selected by the ELOPA register of the ELC. When the event specified in ELSR1 occurs, the TSTART bit in the TRBCR is set to 1, which starts counting by timer RB. However, if the specified event occurs when the TCSTF flag has already been set to 1, that event is not effective. (2) Counting Events The counting of events by timer RB can be selected by the ELOPA register of the ELC. When the event specified in ELSR1 occurs, event counter operation proceeds with that event as the source to drive counting, regardless of the setting in TRBMR. When event-counter operation is to be employed, set the TSTART bit in TRBCR to 1 beforehand. When the value of the counter is read, the value read out is the actual number of input events minus three. 14.4 Interrupt Request This module provides a timer RB interrupt enable bit (the TRBIE bit in TRBIR) and a timer RB interrupt request flag (the TRBIF bit in TRBIR). An interrupt request is issued to the CPU when the TRBIE bit is set to 1 while the TRBIF bit is 1, or when the TRBIE bit changes from 0 to 1 while the TRBIF bit is 1. Since the condition under which the TRBIF bit is set varies with operation modes, see the explanation on the TRBIF bit and the description of the various operation modes. Rev. 1.00 Oct. 03, 2008 Page 435 of 962 REJ09B0465-0100 Section 14 Timer RB 14.5 Usage Notes 1. In programmable one-shot generation mode and programmable wait one-shot generation mode, if the counting is stopped by clearing the TSTART bit in TRBCR to 0, the timer counter holds a count value, and then stops. 2. After 1 is written to the TSTART bit when the counting is stopped, the TCSTF bit remains 0 for the number of cycles of the count source. The timer RB related registers*, with the exception of the TRBCR for reading should not be accessed until the TCSTF bit is set to 1. After 0 is written to the TSTART bit during counting, the TCSTF bit remains 1 for the number of cycles of the count source. The timer RB related registers*, with the exception of the TRBCR for reading should not be accessed until the TCSTF bit is cleared to 0. Note: Timer RB-related registers refer to registers TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and TRBPR. 3. TRBPRE and TRBPR should not be set to H'00 at the same time. 4. When rewriting the bits TRBPRE, TRBPR, and TRBSC at TSTART = 0, set TSTART to 1 after the passage of at least 2-cycle of the system clock. 5. When TSTART = 1 or TCSTF = 1, TRBIOC, or TRBMR should not be rewritten. 6. When writing 1 to the TOSST bit, read the TCSTF bit and write by verifying the value 1. 7. In programmable waveform generation mode or programmable wait one-shot mode, make sure another write to TRBSC does not occur between writing to TRBPR and reloading to the counter. 8. When writing successively to TRBPRE during counting (TCSTF=1), allow a minimum write interval of 4 cycles of count source. 9. When writing successively to TRBPR and TRBSC during counting (TCSTF=1), allow a minimum write interval of 4 cycles of count source. 10. When 1 is written to the TOSST or TOSSP bit in TRBOCR, the value of the TOSSTF bit changes accordingly after 1 to 2 cycles of the source for counting. If 1 is written to the TOSSP bit during the period between the TOSST bit having been set to 1 and the value of the TOSSTF bit becoming 1, the value of the TOSSTF bit will become 0 in some cases and 1 in others, depending on the internal state. In the same way, if 1 is written to the TOSST bit during the period between the TOSSP bit having been set to 1 and the value of the TOSSTF bit becoming 0, whether the value of the TOSSTF bit will become 0 or 1 is not defined. Rev. 1.00 Oct. 03, 2008 Page 436 of 962 REJ09B0465-0100 Section 15 Timer RC Section 15 Timer RC Timer RC is a 16-bit timer having output compare and input capture functions. Timer RC can count external events and output pulses with a desired duty cycle using the compare match function between the timer counter and four general registers. Thus, it can be applied to various systems. Note: Timer RC is not supported in H8S/20223 and H8S/20203 groups. 15.1 Features * Selection of seven counter clock sources Six internal clocks (, /2, /4, /8, /32, and 40) and an external clock (for counting external events) * Capability to process up to four pulse outputs or four pulse inputs * Four general registers Can be used as output compare or input capture registers independently Can be used as buffer registers for the output compare or input capture registers * Timer inputs and outputs Timer mode Output compare function (Selection of 0 output, 1 output, or toggle output) Input capture function (Rising edge, falling edge, or both edges can be detected.) Counter clearing function (Counter cycle can be set.) PWM mode Generates up to three-phase PWM output. PWM2 mode Generates pulses with a desired period and duty cycle. * Any initial timer output value can be set * Five interrupt sources Four compare match/input capture interrupts and an overflow interrupt. Rev. 1.00 Oct. 03, 2008 Page 437 of 962 REJ09B0465-0100 Section 15 Timer RC Table 15.1 summarizes the timer RC functions, and figure 15.1 shows a block diagram of timer RC. Table 15.1 Timer RC Functions Input/Output Pins Item Count clock General registers (output compare/input capture registers) Counter clearing function Counter FTIOA FTIOB FTIOC FTIOD Internal clocks: , /2, /4, /8, /32, and 40 External clock: FTCI Period GRA specified in GRA GRA input capture/ compare match 0 output 1 output Toggle output Input capture function PWM mode PWM2 mode Interrupt sources Overflow GRA input capture/ compare match GRB GRC (buffer register for GRA in buffer mode) GRD (buffer register for GRB in buffer mode) TGRC input Initial output value setting function Buffer function Compare match output Yes Yes Yes Yes Yes Yes Compare match/input capture Yes Yes Yes Yes Yes Yes Yes Yes Compare match/input capture Yes Yes Yes Yes Yes Yes Compare match/input capture Yes Yes Yes Yes Yes Yes Compare match/input capture Rev. 1.00 Oct. 03, 2008 Page 438 of 962 REJ09B0465-0100 Section 15 Timer RC Internal clock: /2 /4 /8 /32 40 External clock: FTCI TRCOI FTIOA/TRGC Clock selection FTIOB Control logic Comparator FTIOC FTIOD OVF IMFA IMFB IMFC IMFD TRCADCR TRCIOR0 TRCIOR1 TRCOER TRCCNT TRCCR1 TRCCR2 TRCIER TRCMR TRCSR TRCDF GRC GRD GRA GRB Figure 15.1 Timer RC Block Diagram Table 15.2 summarizes the timer RC pins. Table 15.2 Pin Configuration Pin Name FTCI FTIOA/TRGC FTIOB FTIOC FTIOD TRCOI Input/ Output Input I/O I/O I/O I/O Input Function External clock input pin Output pin for GRA output compare/input pin for GRA input capture/ external trigger input pin (TRGC) Output pin for GRB output compare/input pin for GRB input capture/ PWM output pin in PWM mode Output pin for GRC output compare/input pin for GRC input capture/ PWM output pin in PWM mode Output pin for GRD output compare/input pin for GRD input capture/ PWM output pin in PWM mode Input pin for timer output disabling signal Rev. 1.00 Oct. 03, 2008 Page 439 of 962 REJ09B0465-0100 Internal data bus Bus interface Section 15 Timer RC 15.2 Register Descriptions The timer RC has the following registers. * * * * * * * * * * * * * * * Timer RC mode register (TRCMR) Timer RC control register 1 (TRCCR1) Timer RC control register 2 (TRCCR2) Timer RC interrupt enable register (TRCIER) Timer RC status register (TRCSR) Timer RC I/O control register 0 (TRCIOR0) Timer RC I/O control register 1 (TRCIOR1) Timer RC output enable register (TRCOER) Timer RC digital filtering function select register (TRCDF) Timer RC A/D conversion start trigger control register (TRCADCR) Timer RC counter (TRCCNT) General register A (GRA) General register B (GRB) General register C (GRC) General register D (GRD) Rev. 1.00 Oct. 03, 2008 Page 440 of 962 REJ09B0465-0100 Section 15 Timer RC 15.2.1 Timer RC Mode Register (TRCMR) Address: H'FFFF8A Bit: b7 CTS Value after reset: 0 b6 b5 BUFEB 0 b4 BUFEA 0 b3 PWM2 1 b2 PWMD 0 b1 PWMC 0 b0 PWMB 0 1 Bit 7 Symbol CTS Bit Name Counter start Description 0: TRCCNT stops counting. 1: TRCCNT starts counting. [Setting conditions] * * When 1 is written in CTS When the specified event is occurred after ELOPA of the event link controller is selected counting by timer RC. When 0 is written in CTS In PWM2 mode, when the CSTP bit in TRCCR2 is set to 1 and a compare match signal is generated. R/W R/W [Clearing conditions] * * 6 5 BUFEB Reserved Buffer operation B Buffer operation A PWM2 mode This bit is read as 1. The write value should be 1. 0: GRD functions as an input capture/output compare register 1: GRD functions as the buffer register for GRB 0: GRC functions as an input capture/output compare register 1: GRC functions as the buffer register for GRA 0: Timer RC functions in PWM2 mode. The following settings are invalid: TRCIOR0, TRCIOR1, and the PWMB, PWMC, and PWMD bits in TRCMR. 1: Timer RC functions in timer mode or PWM mode. The following settings are valid: TRCIOR0, TRCIOR1, and the PWMB, PWMC, and PWMD bits in TRCMR. R/W 4 BUFEA R/W 3 PWM2 R/W Rev. 1.00 Oct. 03, 2008 Page 441 of 962 REJ09B0465-0100 Section 15 Timer RC Bit 2 Symbol PWMD Bit Name Description R/W R/W PWM mode D Selects the output mode of the FTIOD pin. 0: Functions in timer mode 1: Functions in PWM mode 1 PWMC PWM mode C Selects the output mode of the FTIOC pin. 0: Functions in timer mode 1: Functions in PWM mode R/W 0 PWMB PWM mode B Selects the output mode of the FTIOB pin. 0: Functions in timer mode 1: Functions in PWM mode R/W 15.2.2 Timer RC Control Register 1 (TRCCR1) Address: H'FFFF8B Bit: b7 CCLR Value after reset: 0 0 b6 b5 CKS[2:0] 0 0 b4 b3 TOD 0 b2 TOC 0 b1 TOB 0 b0 TOA 0 Bit 7 Symbol CCLR Bit Name Description R/W R/W Counter clear 0: TRCCNT functions as a free-running counter. 1: The TRCCNT value is cleared by input capture A/compare match A. 6 to 4 CKS[2:0]*3 Clock select 2 to 0 Select the source of the clock input to TRCCNT. 000: TRCCNT counts the internal clock . 001: TRCCNT counts the internal clock /2. 010: TRCCNT counts the internal clock /4. 011: TRCCNT counts the internal clock /8. 100: TRCCNT counts the internal clock /32. 101: TRCCNT counts the rising edge of the external event (FTCI). 110: TRCCNT counts the internal clock 40.* 111: Reserved (setting prohibited) 1 R/W Rev. 1.00 Oct. 03, 2008 Page 442 of 962 REJ09B0465-0100 Section 15 Timer RC Bit 3 2 1 0 Symbol TOD TOC TOB TOA Bit Name Description 2 R/W R/W R/W R/W R/W Timer output 0: Output value is 0* . level setting D 1: Output value is 1*2. Timer output 0: Output value is 0*2. level setting C 1: Output value is 1*2. Timer output 0: Output value is 0*2. level setting B 1: Output value is 1*2. Timer output 0: Output value is 0*2. level setting A 1: Output value is 1*2. Notes: 1. If the internal /40 clock is selected, the high-speed on-chip oscillator must be operating. As long as the internal 40 clock is selected, do not stop the high-speed onchip oscillator. Restrictions on access to registers are applied when the internal /40 clock is selected. For details, see 6 in section 15.5, Usage Notes. 6. 2. The change of the setting is immediately reflected in the output value. 3. When the counter clock is switched over, the counter should be halted. * TOD bit (timer output level setting D) Sets the output value of the FTIOD pin until the first compare match D is generated. In PWM mode, controls the output polarity of the FTIOD pin. * TOC bit (timer output level setting C) Sets the output value of the FTIOC pin until the first compare match C is generated. In PWM mode, controls the output polarity of the FTIOC pin. * TOB bit (timer output level setting B) Sets the output value of the FTIOB pin until the first compare match B is generated. In PWM mode, controls the output polarity of the FTIOB pin. * TOA bit (timer output level setting A) Sets the output value of the FTIOA pin until the first compare match A is generated. In PWM mode, controls the output polarity of the FTIOA pin. Rev. 1.00 Oct. 03, 2008 Page 443 of 962 REJ09B0465-0100 Section 15 Timer RC 15.2.3 Timer RC Control Register 2 (TRCCR2) Address: H'FFFF90 Bit: b7 TCEG[1:0] Value after reset: 0 0 b6 b5 CSTP 0 b4 b3 b2 POLD 0 b1 POLC 0 b0 POLB 0 1 1 Bit 7, 6 Symbol Bit Name Description 00: A trigger input on TRGC is disabled. 01: The rising edge is selected. 10: The falling edge is selected. 11: Both edges are selected. R/W R/W TCEG[1:0] TRGC input edge select 5 4, 3 2 1 0 CSTP Count stop Reserved PWM mode output level control D PWM mode output level control C PWM mode output level control B 0: TRCCNT counting up continues. 1: TRCCNT counting up is halted. These bits are read as 1. The write value should be 1. 0: The TRCIOD output is active low. 1: The TRCIOD output is active high. 0: The TRCIOC output is active low. 1: The TRCIOC output is active high. 0: The TRCIOB output is active low. 1: The TRCIOB output is active high. R/W POLD POLC POLB R/W R/W R/W * TCEG[1:0] bits (TRGC input edge select) These bits select the input edge of the TRGC signal. This function is only enabled when the PWM2 bit in TRCMR is set to 0. * CSTP bit (count stop) Specifies whether TRCCNT counting up is halted by the compare match A signal. This function is enabled in all operating modes. To resume counting after counting has been stopped on a compare match, set the CTS bit in the timer RC mode register (TRCMR) to 1. Rev. 1.00 Oct. 03, 2008 Page 444 of 962 REJ09B0465-0100 Section 15 Timer RC 15.2.4 Timer RC Interrupt Enable Register (TRCIER) Address: H'FFFF8C Bit: b7 OVIE Value after reset: 0 b6 b5 b4 b3 IMIED 0 b2 IMIEC 0 b1 IMIEB 0 b0 IMIEA 0 1 1 1 Bit 7 Symbol OVIE Bit Name Description R/W Timer overflow 0: An interrupt (FOVI) requested by the OVF flag in R/W interrupt TRCSR is disabled. enable 1: An interrupt (FOVI) requested by the OVF flag in TRCSR is enabled. Reserved These bits are read as 1. The write value should be 1. 6 to 4 3 IMIED Input capture/ 0: An interrupt (IMID) requested by the IMFD flag in R/W compare TRCSR is disabled. match interrupt 1: An interrupt (IMID) requested by the IMFD flag in enable D TRCSR is enabled. Input capture/ 0: An interrupt (IMIC) requested by the IMFC flag in R/W compare TRCSR is disabled. match interrupt 1: An interrupt (IMIC) requested by the IMFC flag in enable C TRCSR is enabled. Input capture/ 0: An interrupt (IMIB) requested by the IMFB flag in R/W compare TRCSR is disabled. match interrupt 1: An interrupt (IMIB) requested by the IMFB flag in enable B TRCSR is enabled. Input capture/ 0: An interrupt (IMIA) requested by the IMFA flag in R/W compare TRCSR is disabled. match interrupt 1: An interrupt (IMIA) requested by the IMFA flag in enable A TRCSR is enabled. 2 IMIEC 1 IMIEB 0 IMIEA Rev. 1.00 Oct. 03, 2008 Page 445 of 962 REJ09B0465-0100 Section 15 Timer RC 15.2.5 Timer RC Status Register (TRCSR) Address: H'FFFF8D Bit: b7 OVF Value after reset: 0 b6 1 b5 1 b4 1 b3 IMFD 0 b2 IMFC 0 b1 IMFB 0 b0 IMFA 0 Bit 7 Symbol OVF Bit Name Description R/W R/W Timer overflow flag 0: TRCCNT has not overflowed. 1: TRCCNT has overflowed. [Setting condition] * When TRCCNT overflows from H'FFFF to H'0000. Read OVF when OVF = 1, then write 0 in OVF. [Clearing condition] * 6 to 4 3 IMFD Reserved Input capture/ compare match flag D These bits are read as 1. The write value should be 1. [Setting conditions] * * TRCCNT = GRD when GRD functions as an output compare register. The TRCCNT value is transferred to GRD by an input capture signal when GRD functions as an input capture register. TRCCNT = GRD when the PWMD bit is set to 1 or the PWM2 bit to 0 in TRCMR. Read IMFD when IMFD = 1, then write 0 in IMFD. The DTC is activated by an IMFD interrupt and the DISEL bit in MRB of DTC is 0. R/W * [Clearing conditions] * * Rev. 1.00 Oct. 03, 2008 Page 446 of 962 REJ09B0465-0100 Section 15 Timer RC Bit 2 Symbol IMFC Bit Name Input capture/ compare match flag C Description [Setting conditions] * * TRCCNT = GRC when GRC functions as an output compare register. The TRCCNT value is transferred to GRC by an input capture signal when GRC functions as an input capture register. TRCCNT = GRC when the PWMC bit is set to 1 or the PWM2 bit to 0 in TRCMR. Read IMFC when IMFC = 1, then write 0 in IMFC. The DTC is activated by an IMFC interrupt when the DISEL bit in MRB of DTC is 0. R/W R/W * [Clearing conditions] * * 1 IMFB Input capture/ compare match flag B [Setting conditions] * * TRCCNT = GRB when GRB functions as an output compare register. The TRCCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register. TRCCNT = GRB when the PWMB bit is set to 1 or the PWM2 bit to 0 in TRCMR. Read IMFB when IMFB = 1, then write 0 in IMFB. The DTC is activated by an IMFB interrupt when the DISEL bit in MRB of DTC is 0. R/W * [Clearing conditions] * * Rev. 1.00 Oct. 03, 2008 Page 447 of 962 REJ09B0465-0100 Section 15 Timer RC Bit 0 Symbol IMFA Bit Name Input capture/ compare match flag A Description [Setting conditions] * * TRCCNT = GRA when GRA functions as an output compare register. The TRCCNT value is transferred to GRA by an input capture signal when GRA functions as an input capture register. Read IMFA when IMFA = 1, then write 0 in IMFA. R/W R/W [Clearing condition] * The DTC is activated by an IMFA interrupt when the DISEL bit in MRB of DTC is 0. Rev. 1.00 Oct. 03, 2008 Page 448 of 962 REJ09B0465-0100 Section 15 Timer RC 15.2.6 Timer RC I/O Control Register 0 (TRCIOR0) Address: H'FFFF8E Bit: b7 Value after reset: 1 b6 IOB2 0 0 b5 IOB[1:0] 0 b4 b3 1 b2 IOA2 0 0 b1 IOA[1:0] 0 b0 Bit 7 6 Symbol IOB2 Bit Name Reserved Description This bit is read as 1. The write value should be 1. 0: GRB functions as an output compare register 1: GRB functions as an input capture register R/W R/W I/O control B2 Selects the GRB function. 5, 4 IOB[1:0] I/O control B1 When IOB2 = 0, and B0 00: No output on compare match 01: 0 output to the FTIOB pin on compare match of GRB 10: 1 output to the FTIOB pin on compare match of GRB 11: Toggle output to the FTIOB pin on compare match of GRB When IOB2 = 1, 00: Input capture to GRB at rising edge at the FTIOB pin 01: Input capture to GRB at falling edge at the FTIOB pin 1X: Input capture to GRB at rising and falling edges of the FTIOB pin R/W 3 2 IOA2 Reserved This bit is read as 1. The write value should be 1. 0: GRA functions as an output compare register 1: GRA functions as an input capture register R/W I/O control A2 Selects the GRA function. Rev. 1.00 Oct. 03, 2008 Page 449 of 962 REJ09B0465-0100 Section 15 Timer RC Bit 1, 0 Symbol IOA[1:0] Bit Name Description R/W R/W I/O control A1 When IOA2 = 0, and A0 00: No output on compare match 01: 0 output to the FTIOA pin on compare match of GRA 10: 1 output to the FTIOA pin on compare match of GRA 11: Toggle output to the FTIOA pin on compare match of GRA When IOA2 = 1, 00: Input capture to GRA at rising edge of the FTIOA pin 01: Input capture to GRA at falling edge of the FTIOA pin 1X: Input capture to GRA at rising and falling edges of the FTIOA pin [Legend] X: Don't care. Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings in the IOA2 and IOB2 bits in TRCIOR0 and the IOC2 and IOD2 bits in TRCIOR1 of both registers should be the same. 2. The setting of TRCIOR is invalid in PWM mode and PWM2 mode. TRCIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Rev. 1.00 Oct. 03, 2008 Page 450 of 962 REJ09B0465-0100 Section 15 Timer RC 15.2.7 Timer RC I/O Control Register 1 (TRCIOR1) Address: H'FFFF8F Bit: b7 IOD3 Value after reset: 1 b6 IOD2 0 0 b5 IOD[1:0] 0 b4 b3 IOC3 1 b2 IOC2 0 0 b1 IOC[1:0] 0 b0 Bit 7 6 5, 4 Symbol IOD3 IOD2 IOD[1:0] Bit Name Description R/W R/W R/W I/O control D3 0: GRD is used as GR for the FTIOB pin 1: GRD is used as GR for the FTIOD pin I/O control D2 0: GRD functions as an output compare register 1: GRD functions as an input capture register I/O control D1 When IOD3 = 0, and D0 00: No output on compare match 01: 0 output to the FTIOB pin on compare match of GRD 10: 1 output to the FTIOB pin on compare match of GRD 11: Toggle output to the FTIOB pin on compare match of GRD When IOD3 = 1 and IOD2 = 0, 00: No output on compare match 01: 0 output to the FTIOD pin on compare match of GRD 10: 1 output to the FTIOD pin on compare match of GRD 11: Toggle output to the FTIOD pin on compare match of GRD When IOD3 = 1 and IOD2 = 1, 00: Input capture to GRD at rising edge of the FTIOD pin 01: Input capture to GRD at falling edge of the FTIOD pin 1X: Input capture to GRD at rising and falling edges of the FTIOD pin Rev. 1.00 Oct. 03, 2008 Page 451 of 962 REJ09B0465-0100 Section 15 Timer RC Bit 3 2 1, 0 Symbol IOC3 IOC2 IOC[1:0] Bit Name I/O control C3 I/O control C2 I/O control C1 and C0 Description 0: GRC is used as GR for the FTIOA pin 1: GRC is used as GR for the FTIOC pin 0: GRC functions as an output compare register 1: GRC functions as an input capture register When IOC3 = 0, 00: No output on compare match 01: 0 output to the FTIOA pin on compare match of GRC 10: 1 output to the FTIOA pin on compare match of GRC 11: Toggle output to the FTIOA pin on compare match of GRC When IOC3 = 1 and IOC2 = 0, 00: No output on compare match 01: 0 output to the FTIOC pin on compare match of GRC 10: 1 output to the FTIOC pin on compare match of GRC 11: Toggle output to the FTIOC pin on compare match of GRC When IOC3 = 1 and IOC2 = 1, 00: Input capture to GRC at rising edge of the FTIOC pin 01: Input capture to GRC at falling edge of the FTIOC pin 1X: Input capture to GRC at rising and falling edges of the FTIOC pin R/W R/W R/W R/W [Legend] X: Don't care. Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings in the IOA2 and IOB2 bits in TRCIOR0 and the IOC2 and IOD2 bits in TRCIOR1 of both registers should be the same. 2. The setting of TRCIOR1 is invalid in PWM mode and PWM2 mode. Rev. 1.00 Oct. 03, 2008 Page 452 of 962 REJ09B0465-0100 Section 15 Timer RC 15.2.8 Timer RC Output Enable Register (TRCOER) Address: H'FFFF92 Bit: b7 PTO Value after reset: 0 b6 1 b5 1 b4 1 b3 ED 1 b2 EC 1 b1 EB 1 b0 EA 1 Bit 7 Symbol Bit Name PTO Timer output disabled mode Description R/W 0: The ED, EC, EB and EA bits are not set to 1 by R/W the low level input of the TRCOI signal. 1: The ED, EC, EB and EA bits are set to 1 by the low level input of the TRCOI signal. 6 to 4 3 ED Reserved Master enable D These bits are read as 1. The write value should be 1. 0: The FTIOD output is enabled according to the TRCMR and TRCIOR1 settings 1: The FTIOD output is disabled regardless of the TRCMR and TRCIOR1 settings. R/W 2 EC Master enable C 0: The FTIOC output is enabled according to the TRCMR and TRCIOR1 settings. 1: The FTIOC output is disabled regardless of the TRCMR and TRCIOR1 settings. R/W 1 EB Master enable B 0: The FTIOB output is enabled according to the TRCMR and TRCIOR0 settings 1: The FTIOB output is disabled regardless of the TRCMR and TRCIOR0 settings. R/W 0 EA Master enable A 0: The FTIOA output is enabled according to the TRCIOR0 settings 1: The FTIOA output is disabled regardless of the TRCIOR0 settings. R/W TRCOER enables or disables the timer outputs. When setting the PTO bit to 1 and driving the TRCOI signal low, the ED, EC, EB and EA bits are set to 1 and timer RC outputs are disabled. Rev. 1.00 Oct. 03, 2008 Page 453 of 962 REJ09B0465-0100 Section 15 Timer RC 15.2.9 Timer RC Digital Filtering Function Select Register (TRCDF) Address: H'FFFF91 Bit: b7 DFCK[1:0] Value after reset: 0 0 b6 b5 0 b4 DFTRG 0 b3 DFD 0 b2 DFC 0 b1 DFB 0 b0 DFA 0 Bit 7, 6 Symbol DFCK[1:0] Bit Name Description R/W R/W Digital filter clock These bits select the clock to be used by the select digital filter. 00: /32 01: /8 10: 11: Clock specified by bits CKS2 to CKS0 in TRCCR1 5 4 DFTRG Reserved Digital filter function trigger pin Digital filter function D Digital filter function C Digital filter function B Digital filter function A This bit is read as 0. The write value should be 0. 0: Disables the digital filter for the TRGC pin 1: Enables the digital filter for the TRGC pin 0: Disables the digital filter for the FTIOD pin 1: Enables the digital filter for the FTIOD pin 0: Disables the digital filter for the FTIOC pin 1: Enables the digital filter for the FTIOC pin 0: Disables the digital filter for the FTIOB pin 1: Enables the digital filter for the FTIOB pin 0: Disables the digital filter for the FTIOA pin 1: Enables the digital filter for the FTIOA pin R/W 3 2 1 0 DFD DFC DFB DFA R/W R/W R/W R/W Note: The setting in this register is valid on the corresponding pin when the FTIOA to FTIOD inputs are enabled by TRCIOR0 and TRCIOR1 and the TRGC input is selected by bits TCEG1 and TCEG0 in TRCCR2. Rev. 1.00 Oct. 03, 2008 Page 454 of 962 REJ09B0465-0100 Section 15 Timer RC 15.2.10 Timer RC A/D Conversion Start Trigger Control Register (TRCADCR) Address: H'FFFF93 Bit: b7 b6 b5 b4 b3 ADTRGAE 0 b2 ADTRGBE 0 b1 ADTRGCE 0 b0 ADTRGDE 0 Value after reset: 1 1 1 1 Bit 7 to 4 3 Symbol Bit Name Reserved Description These bits are read as 1. The write value should be 1. R/W ADTRGAE A/D conversion start trigger A enable ADTRGBE A/D conversion start trigger B enable ADTRGCE A/D conversion start trigger C enable ADTRGDE A/D conversion start trigger D enable 0: A/D conversion start trigger is not generated by R/W compare match of GRA 1: A/D conversion start trigger is generated by compare match of GRA 0: A/D conversion start trigger is not generated by R/W compare match of GRB 1: A/D conversion start trigger is generated by compare match of GRB 0: A/D conversion start trigger is not generated by R/W compare match of GRC 1: A/D conversion start trigger is generated by compare match of GRC 0: A/D conversion start trigger is not generated by R/W compare match of GRD 1: A/D conversion start trigger is generated by compare match of GRD 2 1 0 TRCADCR selects the trigger source to start A/D conversion. A/D conversion start trigger is generated by a corresponding compare match. Rev. 1.00 Oct. 03, 2008 Page 455 of 962 REJ09B0465-0100 Section 15 Timer RC 15.2.11 Timer RC Counter (TRCCNT) Address: H'FFFF80 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCCNT is a 16-bit readable/writable up-counter. The input clock is selected by bits CKS2 to CKS0 in TRCCR1. TRCCNT can be cleared to H'0000 through a compare match of GRA by setting the CCLR bit in TRCCR1 to 1. When TRCCNT overflows from H'FFFF to H'0000, the OVF flag in TRCSR is set to 1. If the OVIE bit in TRCIER is set to 1 at this time, an interrupt request is generated. TRCCNT must always be read from or written to in units of 16 bits; 8-bit accesses are not allowed. The initial value of TRCCNT is H'0000. Rev. 1.00 Oct. 03, 2008 Page 456 of 962 REJ09B0465-0100 Section 15 Timer RC 15.2.12 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD) GRA Address: H'FFFF82 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GRB Address: H'FFFF84 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GRC Address: H'FFFF86 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GRD Address: H'FFFF88 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. 1.00 Oct. 03, 2008 Page 457 of 962 REJ09B0465-0100 Section 15 Timer RC Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TRCIOR0 and TRCIOR1. When a general register is used as an input-compare register, its value is constantly compared with the TRCCNT value. When the two values match (a compare match), the corresponding flag (the IMFA, IMFB, IMFC, or IMFD bit) in TRCSR is set to 1. An interrupt request is generated at this time, when the IMIEA, IMIEB, IMIEC, or IMIED bit in TRCIER is set to 1. A compare match output can be selected in TRCIOR. When a general register is used as an input-capture register, an external input-capture signal is detected and the current TRCCNT value is stored in the general register. The corresponding flag (the IMFA, IMFB, IMFC, or IMFD bit) in TRCSR is set to 1. If the corresponding interruptenable bit (the IMIEA, IMIEB, IMIEC, or IMIED bit) in TRIER is set to 1 at this time, an interrupt request is generated. The edge of the input-capture signal is selected in TRCIOR. GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA and BUFEB in TRCMR. For example, when GRA is set as an output-compare register and GRC is set as the buffer register for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is generated. When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the value in TRCCNT is transferred to GRA and the value in the buffer register GRA is transferred to GRC whenever an input capture is generated. GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are initialized to H'FFFF by a reset. Rev. 1.00 Oct. 03, 2008 Page 458 of 962 REJ09B0465-0100 Section 15 Timer RC 15.3 Operation Timer RC has the following operating modes. * Timer mode operation Enables output compare and input capture functions by setting the IOA2 to IOA0 and IOB2 to IOB0 bits in TRCIOR0 and the IOC3 to IOC0 and IOD3 to IOD0 bits in TRCIOR1. * PWM mode operation Enables PWM mode operation by setting the PWMD, PWMC, and PWMB bits in TRCMR. * PWM2 mode operation Enables PWM2 mode operation by setting the PWM2 bit in TRCMR. The FTIOA to FTIOD pins indicate the timer output mode by each register setting. Set 1 to the PMCR and PMR bits corresponding to the pins selected by the PMC. Table 15.3 FTIOA Pin Functions Register Name Bit Name Setting values TRCOER EA 0 X X TRCMR PWM2 1 1 1 TRCIOR0 IOA2 to IOA0 001, 01X 1XX 000 Function Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when PCR = 0 on the corresponding pin) Setting prohibited Other than above [Legend] X: Don't care. Rev. 1.00 Oct. 03, 2008 Page 459 of 962 REJ09B0465-0100 Section 15 Timer RC Table 15.4 FTIOB Pin Functions Register Name Bit Name Setting values TRCOER EB 0 0 0 X X TRCMR PWM2 0 1 1 1 1 PWMB X 1 0 0 0 Other than above [Legend] X: Don't care. TRCIOR0 IOB2 to IOB0 XXX XXX 001, 01X 1XX 000 Function PWM2 mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when PCR = 0 on the corresponding pin) Setting prohibited Table 15.5 FTIOC Pin Functions Register Name Bit Name Setting values TRCOER EC 0 0 X X TRCMR PWM2 1 1 1 1 PWMC 1 0 0 0 Other than above [Legend] X: Don't care. TRCIOR1 IOC2 to IOC0 XXX 001, 01X 1XX 000 Function PWM mode waveform output Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when PCR = 0 on the corresponding pin) Setting prohibited Rev. 1.00 Oct. 03, 2008 Page 460 of 962 REJ09B0465-0100 Section 15 Timer RC Table 15.6 FTIOD Pin Functions Register Name Bit Name Setting values TRCOER ED 0 0 X X TRCMR PWM2 1 1 1 1 PWMD 1 0 0 0 Other than above [Legend] X: Don't care. TRCIOR1 IOD2 to IOD0 XXX 001, 01X 1XX 000 Function PWM mode waveform output Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when PCR = 0 on the corresponding pin) Setting prohibited 15.3.1 Timer Mode Operation TRCCNT performs free-running or periodic counting operations. After a reset, TRCCNT is set as a free-running counter. When the CTS bit in TRCMR is set to 1, TRCCNT starts counting. When the TRCCNT value overflows from H'FFFF to H'0000, the OVF flag in TRCSR is set to 1. If the OVIE in TRCIER is set to 1, an interrupt request is generated. Figure 15.2 shows an example of free-running counting. TRCCNT H'FFFF H'0000 CTS bit Flag cleared by software OVF Time Figure 15.2 Free-Running Counter Operation Rev. 1.00 Oct. 03, 2008 Page 461 of 962 REJ09B0465-0100 Section 15 Timer RC Periodic counting operation can be performed when GRA is set as an output compare register and the CCLR bit in TRCCR1 is set to 1. When the counter value matches GRA, TRCCNT is cleared to H'0000, and the IMFA flag in TRCSR is set to 1. If the corresponding IMIEA bit in TRCIER is set to 1, an interrupt request is generated. TRCCNT continues counting from H'0000. Figure 15.3 shows an example of periodic counting. TRCCNT GRA H'0000 CTS bit Flag cleared by software IMFA Time Figure 15.3 Periodic Counter Operation By setting a general register as an output compare register, the specified level of a signal can be output on the FTIOA, FTIOB, FTIOC, or FTIOD pin on compare match A, B, C, or D. The output level can be selected from 0, 1, or toggle. Figure 15.4 shows an example of TRCCNT functioning as a free-running counter. In this example, 1 is output on compare match A and 0 is output on compare match B. When the signal level is already at the selected output level, it is not changed on a compare match. TRCCNT H'FFFF GRA GRB H'0000 FTIOA FTIOB No change No change Time No change No change Figure 15.4 0 and 1 Output Example (TOA = 0, TOB = 1) Rev. 1.00 Oct. 03, 2008 Page 462 of 962 REJ09B0465-0100 Section 15 Timer RC Figure 15.5 shows an example of toggled output when TRCCNT functions as a free-running counter, and the toggled output is selected for both compare matches A and B. TRCCNT H'FFFF GRA GRB H'0000 FTIOA FTIOB Time Output toggled Output toggled Figure 15.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 15.6 shows another example of toggled output when TRCCNT functions as a periodic counter on both compare matches A and B. TRCCNT Counter cleared by compare match of GRA H'FFFF GRA GRB H'0000 FTIOA FTIOB Time Output toggled Output toggled Figure 15.6 Toggle Output Example (TOA = 0, TOB = 1) Rev. 1.00 Oct. 03, 2008 Page 463 of 962 REJ09B0465-0100 Section 15 Timer RC The TRCCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when signal levels are changed on an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD) by specifying the general register as an input capture register. The capture timing can be selected from the rising, falling, or both edges. By using the input-capture function, the width or cycle of a pulse can be measured. Figure 15.7 shows an example of an input capture when both edges of the FTIOA signal and the falling edge of the FTIOB signal are selected as capture timings. TRCCNT functions as a free-running counter. TRCCNT H'FFFF H'F000 H'AA55 H'55AA H'1000 H'0000 Time FTIOA GRA H'1000 H'F000 H'55AA FTIOB GRB H'AA55 Figure 15.7 Input Capture Operating Example Rev. 1.00 Oct. 03, 2008 Page 464 of 962 REJ09B0465-0100 Section 15 Timer RC Figure 15.8 shows an example of buffer operation when GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TRCCNT functions as a free-running counter and is captured at both rising and falling edges of the FTIOA signal. Due to the buffer operation, the GRA value is transferred to GRC on an input-capture A and the TRCCNT value is stored in GRA. TRCCNT H'FFFF H'DA91 H'5480 H'0245 H'0000 FTIOA Time GRA GRC H'0245 H'5480 H'0245 H'DA91 H'5480 Figure 15.8 Buffer Operation Example (Input Capture) Rev. 1.00 Oct. 03, 2008 Page 465 of 962 REJ09B0465-0100 Section 15 Timer RC 15.3.2 PWM Mode Operation In PWM mode, PWM waveforms are generated by using GRA as the cycle register and GRB, GRC, and GRD as duty cycle registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically. The initial output level of each pin depends on the settings in TRCCR1 and TRCCR2. Table 15.7 shows an example of the initial output level of the FTIOB pin. Table 15.7 Initial Output Level of FTIOB Pin Bit TOB (TRCCR1) 0 0 1 1 Bit POLB (TRCCR2) 0 1 0 1 Initial Output Level 1 0 0 1 The output level of each pin is determined by the value of the corresponding PWM mode output level control bit (POLB, POLC, or POLD) in TRCCR2. When POLB is 0, the FTIOB output pin is set to 0 on compare match B, and set to 1 on compare match A, whereas when POLB is 1, the FTIOB output pin is set to 1 on compare match B, and set to 0 on compare match A. When an output pin is set to PWM mode, the settings in TRCIOR0 and TRCIOR1 are ignored. If the same value is set in the cycle register and duty cycle register, output levels are not changed when a compare match occurs. Figure 15.9 shows an example of operation in PWM mode. The output signals go 1 and TRCCNT is cleared on compare match A, and the output signals go 0 on compare match B, C, and D. Rev. 1.00 Oct. 03, 2008 Page 466 of 962 REJ09B0465-0100 Section 15 Timer RC TRCCNT Counter cleared by compare match A GRA GRB GRC GRD H'0000 FTIOB FTIOC Time FTIOD Figure 15.9 PWM Mode Example (1) Figure 15.10 shows another example of operation in PWM mode. The output signals go 0 and TRCCNT is cleared on compare match A, and the output signals go 1 on compare match B, C, and D. TRCCNT Counter cleared by compare match A GRA GRB GRC GRD H'0000 FTIOB FTIOC Time FTIOD Figure 15.10 PWM Mode Example (2) Rev. 1.00 Oct. 03, 2008 Page 467 of 962 REJ09B0465-0100 Section 15 Timer RC Figure 15.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TRCCNT is cleared on compare match A, and the FTIOB pin outputs 1 on compare match B and 0 on compare match A. Due to the buffer operation, the FTIOB output levels are changed and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs. TRCCNT value GRA H'0200 H'0450 H'0520 GRB H'0000 GRD Time H'0200 H'0450 H'0520 GRB H'0200 H'0450 H'0520 FTIOB Figure 15.11 Buffer Operation Example (Output Compare) Rev. 1.00 Oct. 03, 2008 Page 468 of 962 REJ09B0465-0100 Section 15 Timer RC Figures 15.12 and 15.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%. TRCCNT GRB changed GRA GRB H'0000 Duty cycle 0% GRB changed Time FTIOB TRCCNT GRB changed GRA Output levels of FTIOB are not changed when compare matches of cycle register and duty cycle register occur simultaneously. GRB changed GRB changed GRB H'0000 Duty cycle 100% Time FTIOB TRCCNT GRB changed GRA Output levels of FTIOB are not changed when compare matches of cycle register and duty cycle register occur simultaneously. GRB changed GRB changed Time Duty cycle 100% Duty cycle 0% GRB H'0000 FTIOB Figure 15.12 PWM Mode Example (Initial Output Set to 0) Rev. 1.00 Oct. 03, 2008 Page 469 of 962 REJ09B0465-0100 Section 15 Timer RC TRCCNT GRB changed GRA GRB H'0000 GRB changed Time Duty cycle 100% FTIOB TRCCNT GRB changed GRA Output levels of FTIOB are not changed when compare matches of cycle register and duty cycle register occur simultaneously. GRB changed GRB changed GRB H'0000 Duty cycle 0% Time FTIOB TRCCNT GRB changed GRA Output levels of FTIOB are not changed when compare matches of cycle register and duty cycle register occur simultaneously. GRB changed GRB changed Time Duty cycle 0% Duty cycle 100% GRB H'0000 FTIOB Figure 15.13 PWM Mode Example (Initial Output Set to 1) Rev. 1.00 Oct. 03, 2008 Page 470 of 962 REJ09B0465-0100 Section 15 Timer RC 15.3.3 PWM2 Mode Operation In PWM2 mode, waveforms are output on the FTIOB pin when a compare match occurs on GRB or GRC. GRD functions as a buffer register for GRB by setting the BUFEB bit in TRCMR to 1. The output level of the FTIOB signal is specified by the TOB bit in TRCCR1. When TOB = 0, 1 is output on a compare match of GRC and 0 is output on a compare match of GRB. When TOB = 1, 0 is output on a compare match of GRC and 1 is output on a compare match of GRB. Table 15.8 shows the correspondence between the pin configuration and GR registers and figure 15.14 is a block diagram in PWM2 mode. Figures 15.15 and 15.16 show the GRD and GRB buffer operating timing in PWM2 mode. In PWM2 mode, the value of GRD is transferred to GRB on a compare match of GRA and the counter is cleared. Note, however, that the counter is only cleared when the CCLR bit in TRCCR1 is set to 1. Moreover, when the trigger input is enabled by the TCEG1 and TCEG0 bits in TRCCR2, the value of GRD is transferred to GRB by the trigger signal and the counter is cleared. The input/output pins of timers which do not operate in PWM2 mode are only used as general I/O ports. Table 15.8 Pin Configuration in PWM2 Mode and GR Registers Pin Name FTIOA FTIOB Input/Output I/O Output Compare Match Register Port*/TRGC GRB GRC FTIOC FTIOD Note: * I/O I/O Port* Port* Buffer Register Port*/TRGC GRD Port* Port* When the port functions, clear the PMR bit on the corresponding pin to 0. Rev. 1.00 Oct. 03, 2008 Page 471 of 962 REJ09B0465-0100 Section 15 Timer RC Trigger signal FTIOA/TRGC Input control Counter clear signal Compare match signal TRCCNT Compare match signal FTIOB Output control Compare match signal Comparator GRA Comparator GRB GRD Comparator GRC Figure 15.14 Block Diagram in PWM2 Mode TRCCNT L H'0000 GRA L GRD M GRB N M Compare match signal Figure 15.15 GRD and GRB Buffer Operating Timing in PWM2 Mode (1) Rev. 1.00 Oct. 03, 2008 Page 472 of 962 REJ09B0465-0100 Section 15 Timer RC TRCCNT N N+1 H'0000 GRA L GRD M GRB Counter clear signal by trigger input N M Figure 15.16 GRD and GRB Buffer Operating Timing in PWM2 Mode (2) In PWM2 mode, a pulse with arbitrary pulse width and delay time to the TRGC input can be output from the FTIOB pin Figures 15.17 and 15.18 show these examples in PWM2 mode. In these examples, the falling edge of the TRGC input is selected by TRCCR2 (setting the TCEG1 bit to 1 and clearing the TCEG0 bit to 0), TRCCNT continues counting-up on compare match A of GRA (clearing the CSTP bit in TRCCR2 to 0), and GRD is set as the buffer register (setting the BUFEB bit in TRCMR to 1). The initial value of the output signal is set to either 0 or 1 by TRCCR1 (clearing the TOB bit to 0 or setting the TOB bit to 1), TRCCNT is cleared on compare match A (setting the CCLR bit in TRCCR1 to 1), and the waveform is output from the FTIOB pin (clearing the PWM2 bit in TRCMR to 0). When the TOB bit in TRCCR1 is cleared to 0 with the PWM2 mode function, the input edge is ignored while the FTIOB pin is driven high. Whereas, when the TOB bit is set to 1, the input edge is ignored while the FTIOB pin is driven low. The transfer from GRD to GRB is carried out on a compare match of GRA and the TRGC input. However, if the TRGC input is canceled due to the change of the FTIOB level, the transfer from GRD to GRB is not carried out. Rev. 1.00 Oct. 03, 2008 Page 473 of 962 REJ09B0465-0100 Section 15 Timer RC The value of TRCCNT H'FFFF GRA GRB GRC H'0000 FTIOA/TRGC FTIOB (Output transformation when TOB = 0) FTIOB (Output transformation when TOB = 1) GRD GRB A A B B C C D D Time When TOB = 0, the trigger input is ignored while the FTIOB pin is driven high, whereas when TOB = 1, the trigger input is ignored while the FTIOB pin is driven low Figure 15.17 Example (1) of TRGC Synchronous Operation in PWM2 Mode The value of TRCCNT H'FFFF GRA GRB GRC H'0000 CTS High Time FTIOA/TRGC FTIOB (Output transformation when TOB = 0) FTIOB (Output transformation when TOB = 1) GRD GRB A A B C B A A A Data written from the CPU to GRD Data copied from GRD to GRB Figure 15.18 Example (2) of TRGC Synchronous Operation in PWM2 Mode The following is an example of stopping operation of the counter in PWM2 mode. When the CSTP bit in TRCCR2 is set to 1 and the CCLR bit in TRCCR1 is set to 1, TRCCNT is cleared to H'0000 on a compare match with GRA and stops counting. Moreover, TRCCNT is forcibly stopped and cleared to the initial value when the CTS bit in TRCMR is cleared to 0. Figure 15.19 shows such an example when the TOB bit in TRCCR1 is cleared to 0 and set to 1. Rev. 1.00 Oct. 03, 2008 Page 474 of 962 REJ09B0465-0100 Section 15 Timer RC The value of TRCCNT H'FFFF GRA GRB GRC H'0000 CTS FTIOA/TRGC FTIOB (Output transformation when TOB = 0) FTIOB (Output transformation when TOB = 1) High Time Figure 15.19 Example of Stopping Operation of the Counter in PWM2 Mode The following is an example of output operation of the one-shot pulse waveform in PWM2 mode. When the TRGC input is disabled by TRCCR2 (clearing the TCEG1 and TCEG0 bits to 0), TRCCNT is set to stop counting-up on compare match A with GRA (setting the CSTP bit in TRCCR2 to 1), TRCCNT is cleared on compare match A (setting the CCRL bit in TRCCR1 to 1), and the initial value of the output signal is set to 0 by TRCCR1 (clearing the TOB bit to 0), TRCCNT starts counting when the CTS bit in TRCMR is set to 1. Then, TRCCNT is cleared to H'0000 on a compare match with GRA and stops counting, and the one-shot pulse waveform is output. Figure 15.20 shows such an example. The value of TRCCNT H'FFFF GRA GRB GRC H'0000 Time CTS High FTIOA/TRGC FTIOB Figure 15.20 Example (1) of Output Operation of One-Shot Pulse Waveform in PWM2 Mode Rev. 1.00 Oct. 03, 2008 Page 475 of 962 REJ09B0465-0100 Section 15 Timer RC The following is an example of operation when TRCCNT starts counting by the TRGC input and the one-shot pulse waveform is output in PWM2 mode. When the falling edge of the TRGC input is selected by TRCCR2 (setting the TCEG1 bit to 1 and clearing the TCEG0 bit to 0), TRCCNT is set to counting-up on compare match A with GRA (setting the CSTP bit in TRCCR2 to 1), TRCCNT is cleared on compare match A (setting the CCRL bit in TRCCR1 to 1), and the initial value of the output signal is set to 0 by TRCCR1 (clearing the TOB bit to 0), TRCCNT starts counting at the falling edge of FTIOA/TRGC after the CTS bit in TRCMR has been set to 1. Then, TRCCNT is cleared to H'0000 on a compare match with GRA and stops counting, and the oneshot pulse waveform is output. Figure 15.21 shows such an example. The value of TRCCNT H'FFFF GRA GRB GRC H'0000 CTS High FTIOA/TRGC Time FTIOB Figure 15.21 Example (2) of Output Operation of One-Shot Pulse Waveform in PWM2 Mode Rev. 1.00 Oct. 03, 2008 Page 476 of 962 REJ09B0465-0100 Section 15 Timer RC 15.3.4 Digital Filtering Function for Input Capture Inputs Input signals on the FTIOA to FIOD and TRGC pin can be input via the digital filters. The digital filter includes three latches connected in series and a match detector circuit. The input signals on the FTIOA to FTIOD or TRGC pins are using on the sampling clock specified by the DFCK1 and DFCK0 bits in TRCDF. When outputs of the three latches match, the match detector circuit outputs the signal level of the input. Otherwise, the output remains unchanged. That is, when a pulse width is equal to or greater than three sampling clock cycles, the pulse is input as a signal. When a pulse width is less than three sampling clock cycles, the pulse is considered as noise to be removed. CKS2 to CKS0 DFCK1 and DFCK0 40 /32 FTCI /8 /4 /2 /32 /8 Sampling clock DFTRG and DFA to DFD IOA[1:0] to IOD[1:0] FTIOA to FTIOD and TRGC input signals C D Latch , 40 C D Latch Q Q D C Q Latch D C Q Latch D C Q Latch Match detector circuit Selecter Edge detecting circuit Cycle of a clock specified by CKS2 to CKS0 or DFCK1 and DFCK0 Sampling clock FTIOA to FTIOD or TRGC input signal Digital-filtered signal Signal propagation delay: 5 sampling clocks Signal change is not output unless signal levels match three times. Figure 15.22 Block Diagram of Digital Filter Rev. 1.00 Oct. 03, 2008 Page 477 of 962 REJ09B0465-0100 Section 15 Timer RC 15.3.5 A/D Conversion Start Trigger Setting Function Timer RC can generate the A/D conversion start trigger signal on compare matches A, B, C, and D by setting the timer RC A/D conversion start trigger control register (TRCADCR). Figure 15.23 shows an example where the A/D conversion start trigger signal is set to be output on compare matches B and C. GRA GRB GRC H'0000 ADTRG A/D conversion start trigger is generated. Figure 15.23 Example of Compare Match In buffer operation, a buffer register cannot be used to generate the A/D conversion start trigger. Moreover, GRC cannot serve as a buffer register for GRA in PWM2 mode. Table 15.9 shows the A/D conversion start trigger source in each operating mode. Rev. 1.00 Oct. 03, 2008 Page 478 of 962 REJ09B0465-0100 Section 15 Timer RC Table 15.9 A/D Conversion Start Trigger Generation in Each Operating Mode A/D Conversion Start Trigger Generation Operating Mode Input capture Buffer Operation Enabled Disabled Compare match Enabled Disabled PWM mode Enabled Disabled PWM2 mode Enabled Disabled GRA x x O O O O O O GRB x x O O O O O O GRC x x x O x O O O GRD x x x O x O x O [Legend] O: The A/D conversion start trigger signal is generated. x: The A/D conversion start trigger signal is not generated. Rev. 1.00 Oct. 03, 2008 Page 479 of 962 REJ09B0465-0100 Section 15 Timer RC 15.3.6 Function of Changing Output Pins for GR With the settings of bits IOC3 and IOD3 in TRCIOR1, pins for outputs of compare match signals for GRC and GRD can be changed from the FTIOC and FTIOD pins to the FTIOA and FTIOB pins. This means that the compare match A signal with the compare match C signal can be output on the FTIOA pin. The compare match B with the compare match D signal can be output on the FTIOB pin. Figure 15.24 is a block diagram of this function. Channel 0 and channel 1 can be set independently. Compare match signal FTIOA Output control Compare match signal FTIOC Output control Compare match signal FTIOB Output control Compare match signal FTIOD Output control Comparator Comparator TRCCNT GRA Comparator GRC GRB Comparator GRD Figure 15.24 Block Diagram of Output Pins for GR Rev. 1.00 Oct. 03, 2008 Page 480 of 962 REJ09B0465-0100 Section 15 Timer RC Figure 15.25 is an example when non-overlapped pulses are output on pins FTIOA and FTIOB. In this example, TRCCNT functions as a periodic counter which is cleared on compare match A (bit CCLR in TRCCR1 is set to 1), an output signal is toggled on compare match A (bits IOA2 to IOA0 in TRCIOR0 are set to B'011), the output signal on the FTIOA pin is toggled on compare match C (GRC) (bits IOC3 to IOC0 in TRCIOR1are set to B'0X11), an output signal is toggled on compare match B (GRB) (bits IOB2 to IOB0 in TRCIOR0 are set to B'011), and the output signal on the FTIOB pin is toggled on compare match D (GRD) (bits IOD3 to IOD0 in TRCIOR1 are set to B'0X11). The cycle of the pulse is arbitrary. TRCCNT H'FFFF GRA GRC GRB GRD H'0000 FTIOA Counter cleared by compare match of GRA Time FTIOB Figure 15.25 Example of Non-Overlapped Pulses Output on Pins FTIOA and FTIOB (TRCCNT Used) Rev. 1.00 Oct. 03, 2008 Page 481 of 962 REJ09B0465-0100 Section 15 Timer RC 15.3.7 Operation through an Event Link Using the event link controller (ELC), timer RC can be made to operate in the following ways in relation to events occurring in other modules. (1) Staring Counter Operation The start of counting operations by timer RC can be selected by ELOPA of the ELC. When the event specified by ELSR2 occur, the CTS bit in TRCMR is set to 1, which stars counting by timer RC. However, if the specified event occurs when the CTS bit has already been set to 1, the event is not effective. (2) Counting Event The counting of events by timer RC can be selected by ELOPA of the ELC. When the event specified in ELSR2 occurs, event counter operation proceeds with that event as the source to drive counting, regardless of the setting of the CKS[2:0] bits in TRCCR1. When the value of the counter is read, the value read out is the actual number of input events. (3) Input Capture Input capture operation of timer RC can be selected by ELOPA of the ELC. When the event specified in ELSR2 occurs, GRD captures the value of TRCCNT. When input capture operation initiated by an event link is in use, set the IOD[3:0] bits = b'1101 in TRCIOR1 of timer RC, set the CTS bit in TRCMR to 1, and then start the counter. Since input on the FTIOD pin becomes valid at the same time, fix the input to the FTIOD pin or take other measures such as not allocating the FTIOD pin to the port in the PMC, etc. Rev. 1.00 Oct. 03, 2008 Page 482 of 962 REJ09B0465-0100 Section 15 Timer RC 15.4 15.4.1 Operation Timing TRCCNT Counting Timing Figure 15.26 shows the TRCCNT count timing when the internal clock source is selected. Figure 15.27 shows the timing when the external clock source is selected. Internal clock Rising edge TRCCNT input clock TRCCNT N N+1 N+2 Figure 15.26 Count Timing for Internal Clock Source External clock Rising edge Rising edge TRCCNT input clock TRCCNT N N+1 N+2 Figure 15.27 Count Timing for External Clock Source Rev. 1.00 Oct. 03, 2008 Page 483 of 962 REJ09B0465-0100 Section 15 Timer RC 15.4.2 Output Compare Output Timing The compare match signal is generated in the last state in which TRCCNT and GR match (when TRCCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TRCIOR is output on the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TRCCNT matches GR, the compare match signal is generated only after the next counter clock pulse is input. Figure 15.28 shows the output compare timing. TRCCNT input clock TRCCNT N N+1 GRA to GRD Compare match signal FTIOA to FTIOD N Figure 15.28 Output Compare Output Timing Rev. 1.00 Oct. 03, 2008 Page 484 of 962 REJ09B0465-0100 Section 15 Timer RC 15.4.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TRCIOR0 and TRCIOR1. Figure 15.29 shows the timing when the falling edge is selected. Input capture input Input capture signal TRCCNT N-1 N N+1 N+2 GRA to GRD N Figure 15.29 Input Capture Input Signal Timing 15.4.4 Timing of Counter Clearing by Compare Match Figure 15.30 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N + 1. Compare match signal TRCCNT N H'0000 GRA N Figure 15.30 Timing of Counter Clearing by Compare Match Rev. 1.00 Oct. 03, 2008 Page 485 of 962 REJ09B0465-0100 Section 15 Timer RC 15.4.5 Buffer Operation Timing Figures 15.31 and 15.32 show the buffer operation timing. Compare match signal TRCCNT N N+1 GRC, GRD M GRA, GRB M Figure 15.31 Buffer Operation Timing (Compare Match) Input capture signal TRCCNT GRA, GRB N N+1 M N N+1 GRC, GRD M N Figure 15.32 Buffer Operation Timing (Input Capture) Rev. 1.00 Oct. 03, 2008 Page 486 of 962 REJ09B0465-0100 Section 15 Timer RC 15.4.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) matches TRCCNT, the corresponding IMFA to IMFD flag which is used as output compare register is set to 1. The compare match signal is generated in the last state in which the values match (when TRCCNT is updated from the matching count to the next count). Therefore, when TRCCNT matches a general register (GRA, GRB, GRC, or GRD), the compare match signal is generated only after the next TRCCNT clock pulse is input. Figure 15.33 shows the timing of the IMFA to IMFD flag setting at compare match. TRCCNT input clock TRCCNT N N+1 GRA to GRD N Compare match signal IMFA to IMFD Figure 15.33 Timing of IMFA to IMFD Flag Setting at Compare Match Rev. 1.00 Oct. 03, 2008 Page 487 of 962 REJ09B0465-0100 Section 15 Timer RC 15.4.7 Timing of IMFA to IMFD Setting at Input Capture The corresponding IMFA, IMFB, IMFC, or IMFD flag which functions as a general register is set to 1 when an input capture occurs. Figure 15.34 shows the timing of the IMFA to IMFD flag setting at input capture. Input capture signal TRCCNT N GRA to GRD N IMFA to IMFD Figure 15.34 Timing of IMFA to IMFD Flag Setting at Input Capture Rev. 1.00 Oct. 03, 2008 Page 488 of 962 REJ09B0465-0100 Section 15 Timer RC 15.4.8 Timing of Status Flag Clearing When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 15.35 shows the status flag clearing timing. TRCSR write cycle T1 T2 Address TRCSR address Write signal IMFA to IMFD Figure 15.35 Timing of Status Flag Clearing by CPU Rev. 1.00 Oct. 03, 2008 Page 489 of 962 REJ09B0465-0100 Section 15 Timer RC 15.4.9 Timing of A/D Conversion Start Trigger Generation on Compare Match Figure 15.36 shows the timing of the A/D conversion start trigger generation on compare match. TRCCNT input TRCCNT N N+1 GR N Compare match signal A/D conversion trigger signal Figure 15.36 Timing of A/D Conversion Start Trigger Generation on Compare Match Rev. 1.00 Oct. 03, 2008 Page 490 of 962 REJ09B0465-0100 Section 15 Timer RC 15.5 Usage Notes The following types of contention or operation can occur in timer RC operation. 1. When the digital filtering function for input is not in use, the pulse width of the input clock signal and the input capture signal must be at least three system clock () cycles when the CKS2 to CKS0 bits in TRCCR1 = B'0XX or B'10X, and at least 3 x 40 cycles for B'110; shorter pulses will not be detected correctly. 2. Writing to registers is performed in the T2 state of a TRCCNT write cycle. If counter clear signal occurs in the T2 state of a TRCCNT write cycle, clearing of the counter takes priority and the write is not performed, as shown in figure 15.37. If the TRCCNT write cycle contends with the TRCCNT counting-up, writing takes precedence. 3. TRCCNT may erroneously count up depends on the timing of switching internal clocks. The count clock is generated by detecting the rising edge of the divided system clock () when the internal clock is selected. If clocks are switched as shown in figure 15.38, the change from the low level of the previous clock to the high level of the new clock is considered as the rising edge. In this case, TRCCNT counts up the clock erroneously. 4. If timer RC enters the module standby mode while an interrupt is being requested, the interrupt request cannot be cleared. Before entering the module standby mode, disable interrupt requests. TRCCNT write cycle T2 T1 Address TRCCNT address Write signal Counter clear signal TRCCNT N H'0000 Figure 15.37 Contention between TRCCNT Write and Clear Rev. 1.00 Oct. 03, 2008 Page 491 of 962 REJ09B0465-0100 Section 15 Timer RC Previous clock New clock Counter clock TRCCNT N N+1 N+2 N+3 The rising edge may occur depending on the timing of changing bits CKS2 to CKS0. In this case, TRCCNT counts up. Figure 15.38 Internal Clock Switching and TRCCNT Operation 5. The TOA to TOD bits in TRCCR1 decide the output value of the FTIO pin until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the values read from the TOA to TOD bits may differ. Moreover, when the writing to TRCCR1 and the generation of the compare match A to D occur at the same timing, the writing to TRCCR1 has the priority. Thus, output change due to the compare match is not reflected to the FTIOA to FTIOD pins. Therefore, when bit manipulation instruction is used to write to TRCCR1, the values of the FTIOA to FTIOD pin output may result in an unexpected result. When TRCCR1 is to be written to while compare match is operating, stop the counter once before accessing to TRCCR1, read the port H state to reflect the values of FTIOA to FTIOD output, to TOA to TOD, and then restart the counter. Figure 15.39 shows an example when the compare match and the bit manipulation instruction to TRCCR1 occur at the same timing. Rev. 1.00 Oct. 03, 2008 Page 492 of 962 REJ09B0465-0100 Section 15 Timer RC TRCCR1 has been set to H'06. Compare match B and compare match C are used. The FTIOB pin output 1, and is set to the toggle output or the 0 output on compare match B. When the TOC bit is cleared (the FTIOC signal is low) by execution of BCLR #2,@TRCCR1 and compare match B occurs at the same timing as shown below, writing H'02 to TRCCR1 has priority and the FTIOB signal is not driven low on compare match B; the FTIOB signal remains high. Bit TRCCR1 Setting 7 CCLR 0 6 CKS2 0 5 CKS1 0 4 CKS0 0 3 TOD 0 2 TOC 1 1 TOB 1 0 TOA 0 BCLR #2,@TRCCR1 (1) TRCCR1 is read as H'06. (2) TRCCR1 is modified from H'06 to H'02. (3) H'02 is written to TRCCR1. TRCCR1 write signal Compare match B signal FTIOB pin Remains high because the writing 1 to TOB has priority Expected output Figure 15.39 When Compare Match and Bit Manipulation Instruction to TRCCR1 Occur at the Same Timing Rev. 1.00 Oct. 03, 2008 Page 493 of 962 REJ09B0465-0100 Section 15 Timer RC 6. When the internal 40 clock is selected as the counter source (the CKS[2:0] bits in TRCCR1 = B'110), if any register of timer RC is to be read immediately after writing to another register in a given module, proceed with reading after having executed one NOP instruction. Write to TRCMR. Execute NOP. Read TRCCNT. Figure 15.40 Example of Flow for Reading Immediately after Writing to a Register Rev. 1.00 Oct. 03, 2008 Page 494 of 962 REJ09B0465-0100 Section 16 Timer RD Section 16 Timer RD This LSI has two units of 16-bit timers (timer RD_0 and timer RD_1), each of which has two channels. Table 16.1 lists the timer RD functions, table 16.2 lists the channel configuration of timer RD, and figure 16.1 is a block diagram of the entire timer RD. Block diagrams of channels 0 and 1 are shown in figures 16.2 and 16.3. Timer RD_0 has the same functions as timer RD_1. Therefore, the unit number (_0 or _1) is not explicitly mentioned in this section unless otherwise noted. 16.1 Features * Capability to process up to eight inputs/outputs * Eight general registers (GR): four registers for each channel Independently assignable output compare or input capture functions * Selection of seven counter clock sources: six internal clocks (, /2, /4, /8, /32, and 40M) and an external clock * Seven selectable operating modes Timer mode Output compare function (Selection of 0 output, 1 output, or toggle output) Input capture function (Rising edge, falling edge, or both edges) Synchronous operation Timer counters_0 and _1 (TRDCNT_0 and TRDCNT_1) can be written simultaneously. Simultaneous clearing by compare match or input capture is possible. PWM mode Up to six-phase PWM output can be provided with desired duty ratio. PWM3 mode One-phase PWM output for non-overlapped normal and counter phases Reset synchronous PWM mode Three-phase PWM output for normal and counter phases Complementary PWM mode Three-phase PWM output for non-overlapped normal and counter phases The A/D conversion start trigger can be set for PWM cycles. Buffer operation The input capture register can be consisted of double buffers. The output compare register can automatically be modified. Rev. 1.00 Oct. 03, 2008 Page 495 of 962 REJ09B0465-0100 Section 16 Timer RD * High-speed access by the internal 16-bit bus 16-bit TRDCNT and GR registers can be accessed in high speed by a 16-bit bus interface * Any initial timer output value can be set * Output of the timer is disabled by external trigger * Eleven interrupt sources Four compare match/input capture interrupts and an overflow interrupt are available for each channel. An underflow interrupt can be set for channel 1. Rev. 1.00 Oct. 03, 2008 Page 496 of 962 REJ09B0465-0100 Section 16 Timer RD Table 16.1 Timer RD Functions (One Unit) Item Count clock General registers (output compare/input capture registers) Buffer register I/O pins Counter clearing function Channel 0 Channel 1 Internal clocks: , /2, /4, /8, /32, 40M External clock: FTIOA0 (TCLK) GRA_0, GRB_0, GRC_0, GRD_0 GRA_1, GRB_1, GRC_1, GRD_1 GRC_0, GRD_0 FTIOA0, FTIOB0, FTIOC0, FTIOD0 Compare match/input capture of GRA_0, GRB_0, GRC_0, or GRD_0 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Compare match/ input capture A0 to D0 Overflow GRC_1, GRD_1 FTIOA1, FTIOB1, FTIOC1, FTIOD1 Compare match/input capture of GRA_1, GRB_1, GRC_1, or GRD_1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Compare match/ input capture A1 to D1 Overflow Underflow Compare match output 0 output 1 output Toggle output Input capture function Synchronous operation PWM mode PWM3 mode Reset synchronous PWM mode Complementary PWM mode Buffer function Interrupt sources Rev. 1.00 Oct. 03, 2008 Page 497 of 962 REJ09B0465-0100 Section 16 Timer RD Table 16.2 Channel Configuration of Timer RD Unit Timer RD_0 (Unit 0) Channel 0 Pin FTIOA0 FTIOB0 FTIOC0 FTIOD0 1 FTIOA1 FTIOB1 FTIOC1 FTIOD1 Shared by channels 0 and 1 Timer RD_1 (Unit 1) 2 TRDOI_0 FTIOA2 FTIOB2 FTIOC2 FTIOD2 3 FTIOA3 FTIOB3 FTIOC3 FTIOD3 Shared by channels 2 and 3 TRDOI_1 Rev. 1.00 Oct. 03, 2008 Page 498 of 962 REJ09B0465-0100 Section 16 Timer RD TRDOI_0 FTIOA0 FTIOB0 FTIOC0 FTIOD0 FTIOA1 FTIOB1 FTIOC1 FTIOD1 , /2, /4, /8, /32, 40 Control logic Channel 0 Interrupt request signal ITDMA0 ITDMB0 ITDMC0 ITDMD0 ITDOV0 ITDUD0 Channel 1 Interrupt request signal ITDMA1 ITDMB1 ITDMC1 ITDMD1 ITDOV1 ADTRG TRDSTR TRDMDR TRDOER2 Channel 0 timer Channel 1 timer TRDPMR TRDFCR TRDADCR TRDOER1 TRDOCR Module data bus Figure 16.1 Timer RD (One Unit) Block Diagram Rev. 1.00 Oct. 03, 2008 Page 499 of 962 REJ09B0465-0100 Section 16 Timer RD FTIOA0 , /2, /4, /8, /32, 40 Comparator FTIOB0 FTIOC0 FTIOD0 ITDMA0 ITDMB0 ITDMC0 ITDMD0 ITDOV0 ITDUD0 TRDOI_0 Clock select Control logic TRDIORC_0 TRDIORA_0 TRDCNT_0 TRDIER_0 TRDCR_0 TRDSR_0 Module data bus Figure 16.2 Timer RD (Channel 0) Block Diagram Rev. 1.00 Oct. 03, 2008 Page 500 of 962 REJ09B0465-0100 TRDDF_0 POCR_0 GRC_0 GRD_0 GRA_0 GRB_0 Section 16 Timer RD FTIOA1 , /2, /4, /8, /32, 40 Comparator FTIOB1 FTIOC1 FTIOD1 ITDMA1 ITDMB1 ITDMC1 ITDMD1 ITDOV1 TRDOI_0 Clock select Control logic TRDIORC_1 TRDIORA_1 TRDCNT_1 TRDIER_1 TRDCR_1 TRDSR_1 Module data bus Figure 16.3 Timer RD (Channel 1) Block Diagram Rev. 1.00 Oct. 03, 2008 Page 501 of 962 REJ09B0465-0100 TRDDF_1 POCR_1 GRC_1 GRD_1 GRA_1 GRB_1 Section 16 Timer RD Table 16.3 summarizes the timer RD pins. Table 16.3 Pin Configuration (One Unit) Pin Name FTIOA0 FTIOB0 FTIOC0 Input/Output I/O I/O I/O Function GRA_0 output compare output, GRA_0 input capture input, or external clock input (TCLK) GRB_0 output compare output, GRB_0 input capture input, or PWM output GRC_0 output compare output, GRC_0 input capture input, or PWM synchronous output (in reset synchronous PWM and complementary PWM modes) GRD_0 output compare output, GRD_0 input capture input, or PWM output GRA_1 output compare output, GRA_1 input capture input, or PWM output (in reset synchronous PWM and complementary PWM modes) GRB_1 output compare output, GRB_1 input capture input, or PWM output GRC_1 output compare output, GRC_1 input capture input, or PWM output GRD_1 output compare output, GRD_1 input capture input, or PWM output Input pin for timer output disabling signal FTIOD0 FTIOA1 I/O I/O FTIOB1 FTIOC1 FTIOD1 TRDOI_0 I/O I/O I/O Input Rev. 1.00 Oct. 03, 2008 Page 502 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2 Register Descriptions Timer RD has the following registers. Common * * * * * * * * Timer RD start register (TRDSTR) Timer RD mode register (TRDMDR) Timer RD PWM mode register (TRDPMR) Timer RD function control register (TRDFCR) Timer RD output master enable register 1 (TRDOER1) Timer RD output master enable register 2 (TRDOER2) Timer RD output control register (TRDOCR) Timer RD A/D conversion start trigger control register (TRDADCR) Channel 0 * * * * * * * * * * * * Timer RD control register_0 (TRDCR_0) Timer RD I/O control register A_0 (TRDIORA_0) Timer RD I/O control register C_0 (TRDIORC_0) Timer RD status register_0 (TRDSR_0) Timer RD interrupt enable register_0 (TRDIER_0) PWM mode output level control register_0 (POCR_0) Timer RD digital filtering function select register_0 (TRDDF_0) Timer RD counter_0 (TRDCNT_0) General register A_0 (GRA_0) General register B_0 (GRB_0) General register C_0 (GRC_0) General register D_0 (GRD_0) Rev. 1.00 Oct. 03, 2008 Page 503 of 962 REJ09B0465-0100 Section 16 Timer RD Channel 1 * * * * * * * * * * * * Timer RD control register_1 (TRDCR_1) Timer RD I/O control register A_1 (TRDIORA_1) Timer RD I/O control register C_1 (TRDIORC_1) Timer RD status register_1 (TRDSR_1) Timer RD interrupt enable register_1 (TRDIER_1) PWM mode output level control register_1 (POCR_1) Timer RD digital filtering function select register_1 (TRDDF_1) Timer RD counter_1 (TRDCNT_1) General register A_1 (GRA_1) General register B_1 (GRB_1) General register C_1 (GRC_1) General register D_1 (GRD_1) Rev. 1.00 Oct. 03, 2008 Page 504 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.1 Timer RD Start Register (TRDSTR) Address: H'FFFFD2 Bit: b7 b6 b5 b4 b3 CSTPN1 1 b2 CSTPN0 1 b1 STR1 0 b0 STR0 0 Value after reset: 1 1 1 1 Bit Symbol Bit Name Reserved Description These bits are read as 1. The write value should be 1. R/W R/W 7 to 4 3 CSTPN1 Channel 1 counter 0: Counting is stopped on a compare match of stop TRDCNT_1 and GRA_1 1: Counting is continued on a compare match of TRDCNT_1 and GRA_1 Set this bit to 1 to restart counting after the counting has been stopped on a compare match. 2 CSTPN0 Channel 0 counter 0: Counting is stopped on a compare match of stop TRDCNT_0 and GRA_0 1: Counting is continued on a compare match of TRDCNT_0 and GRA_0 Set this bit to 1 to restart counting after the counting has been stopped on a compare match. R/W 1 STR1 Channel 1 counter 0: TRDCNT_1 stops counting. start 1: TRDCNT_1 starts counting. [Setting conditions] * * When 1 is written in STR1 When the specified event is occurred after ELOPB of the event link controller is selected counting by timer RD_0 for channel 1. When 0 is written in STR1 while CSTPN1 = 1 When the compare match A1 signal is generated while CSTPN1 = 0 R/W [Clearing conditions] * * Rev. 1.00 Oct. 03, 2008 Page 505 of 962 REJ09B0465-0100 Section 16 Timer RD Bit 0 Symbol STR0 Bit Name Description R/W R/W Channel 0 counter 0: TRDCNT_0 stops counting. start 1: TRDCNT_0 starts counting. [Setting conditions] * * When 1 is written in STR0 When the specified event is occurred after ELOPA of the event link controller is selected counting by timer RD_0 for channel 0. When 0 is written in STR0 while CSTPN0 = 1 When the compare match A1 signal is generated while CSTPN0 = 0 [Clearing conditions] * * Note: Use a MOV instruction to modify this register. Rev. 1.00 Oct. 03, 2008 Page 506 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.2 Timer RD Mode Register (TRDMDR) Address: H'FFFFD3 Bit: b7 BFD1 b6 BFC1 0 b5 BFD0 0 b4 BFC0 0 b3 b2 b1 b0 SYNC 0 Value after reset: 0 1 1 1 Bit 7 Symbol BFD1 Bit Name Buffer operation D1 Buffer operation C1 Buffer operation D0 Buffer operation C0 Reserved Description 0: GRD_1 operates normally 1: GRB_1 and GRD_1 are used together for buffer operation 0: GRC_1 operates normally 1: GRA_1 and GRC_1 are used together for buffer operation 0: GRD_0 operates normally 1: GRB_0 and GRD_0 are used together for buffer operation 0: GRC_0 operates normally 1: GRA_0 and GRC_0 are used together for buffer operation These bits are read as 1. The write value should be 1. R/W R/W 6 BFC1 R/W 5 BFD0 R/W 4 BFC0 R/W 3 to 1 0 SYNC R/W Timer 0: TRDCNT_1 and TRDCNT_0 operate as synchronization independent timer counters 1: TRDCNT_1 and TRDCNT_0 operate synchronously TRDCNT_1 and TRDCNT_0 can be pre-set or cleared synchronously. Rev. 1.00 Oct. 03, 2008 Page 507 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.3 Timer RD PWM Mode Register (TRDPMR) Address: H'FFFFD4 Bit: b7 b6 PWMD1 0 b5 PWMC1 0 b4 PWMB1 0 b3 b2 PWMD0 0 b1 PWMC0 0 b0 PWMB0 0 Value after reset: 1 1 Bit 7 6 5 4 3 2 1 0 Symbol PWMD1 PWMC1 PWMB1 PWMD0 PWMC0 PWMB0 Bit Name Reserved PWM mode D1 PWM mode C1 PWM mode B1 Reserved PWM mode D0 PWM mode C0 PWM mode B0 Description This bit is read as 1. The write value should be 1. 0: FTIOD1 operates normally 1: FTIOD1 operates in PWM mode 0: FTIOC1 operates normally 1: FTIOC1 operates in PWM mode 0: FTIOB1 operates normally 1: FTIOB1 operates in PWM mode This bit is read as 1. The write value should be 1. 0: FTIOD0 operates normally 1: FTIOD0 operates in PWM mode 0: FTIOC0 operates normally 1: FTIOC0 operates in PWM mode 0: FTIOB0 operates normally 1: FTIOB0 operates in PWM mode R/W R/W R/W R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 508 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.4 Timer RD Function Control Register (TRDFCR) Address: H'FFFFD5 Bit: b7 PWM3 b6 STCLK 0 b5 ADEG 0 b4 ADTRG 0 b3 OLS1 0 b2 OLS0 0 0 b1 CMD[1:0] 0 b0 Value after reset: 1 Bit 7 6 5 Symbol PWM3 STCLK ADEG Bit Name PWM3 mode select Description 0: PWM3 mode is selected 1: PWM3 mode is not selected* 1 R/W R/W R/W R/W External clock 0: External clock input is disabled input select 1: External clock input is enabled A/D trigger edge select 0: The A/D trigger signal is asserted when TRDCNT_0 matches GRA_0 in complementary PWM mode 1: The A/D trigger signal is asserted when TRDCNT_1 underflows in complementary PWM mode 4 ADTRG External 0: A/D trigger for PWM cycles is disabled in trigger disable complementary PWM mode 1: A/D trigger for PWM cycles is enabled in complementary PWM mode*2 R/W 3 2 OLS1 OLS0 Output level select 1 Output level select 0 0: Initial output is high and the active level is low. 1: Initial output is low and the active level is high. 0: Initial output is high and the active level is low. 1: Initial output is low and the active level is high. R/W R/W Rev. 1.00 Oct. 03, 2008 Page 509 of 962 REJ09B0465-0100 Section 16 Timer RD Bit 1, 0 Symbol CMD[1:0] Bit Name Description R/W R/W Combination 00: Channel 0 and channel 1 operate normally mode 1 and 0 01: Channel 0 and channel 1 are used together to operate in reset synchronous PWM mode 10: Channel 0 and channel 1 are used together to operate in complementary PWM mode (transferred when TRDCNT_0 matches GRA_0) 11: Channel 0 and channel 1 are used together to operate in complementary PWM mode (transferred when TRDCNT_1 underflows) Note: When the reset synchronous PWM mode or complementary PWM mode is selected by these bits, this setting has the priority to the settings for PWM mode by each bit in TRDPMR. Stop TRDCNT_0 and TRDCNT_1 before making settings for reset synchronous PWM mode or complementary PWM mode. Notes: 1. This bit is valid when both bits CMD1 and CMD0 are cleared to 0. When PWM3 mode is selected, TRDPMR, TRDIORA, and TRDIORC are invalid. 2. The A/D converter registers should be set so that A/D conversion is started by an external trigger. * OLS1 bit (output level select 1) This bit selects the output level for counter phase in reset synchronous PWM mode and complementary PWM mode. * OLS0 bit (output level select 0) This bit selects the output level for normal phase in reset synchronous PWM mode and complementary PWM mode. Rev. 1.00 Oct. 03, 2008 Page 510 of 962 REJ09B0465-0100 Section 16 Timer RD TRDCNT_0 TRDCNT_1 Normal phase Counter phase Initial output Active level Normal phase Counter phase Initial output Active level Complementary PWM mode Active level Active level Reset synchronous PWM mode Note: Write H'00 to TRDOCR to start initial outputs after stopping the counter. Figure 16.4 Example of Outputs in Reset Synchronous PWM Mode and Complementary PWM Mode 16.2.5 Timer RD Output Master Enable Register 1 (TRDOER1) Address: H'FFFFD6 Bit: b7 ED1 Value after reset: 1 b6 EC1 1 b5 EB1 1 b4 EA1 1 b3 ED0 1 b2 EC0 1 b1 EB0 1 b0 EA0 1 Bit 7 Symbol ED1 Bit Name Description R/W R/W Master enable 0: FTIOD1 pin output is enabled according to the D1 TRDPMR, TRDFCR, and TRDIORC_1 settings 1: FTIOD1 pin output is disabled regardless of the TRDMR, TRDFCR, and TRDIORC_1 settings (FTIOD1 pin is operated as an I/O port). 6 EC1 Master enable 0: FTIOC1 pin output is enabled according to the C1 TRDPMR, TRDFCR, and TRDIORC_1 settings 1: FTIOC1 pin output is disabled regardless of the TRDPMR, TRDFCR, and TRDIORC_1 settings (FTIOC1 pin is operated as an I/O port). R/W Rev. 1.00 Oct. 03, 2008 Page 511 of 962 REJ09B0465-0100 Section 16 Timer RD Bit 5 Symbol EB1 Bit Name Description R/W R/W Master enable 0: FTIOB1 pin output is enabled according to the B1 TRDPMR, TRDFCR, and TRDIORA_1 settings 1: FTIOB1 pin output is disabled regardless of the TRDPMR, TRDFCR, and TRDIORA_1 settings (FTIOB1 pin is operated as an I/O port). 4 EA1 Master enable 0: FTIOA1 pin output is enabled according to the A1 TRDPMR, TRDFCR, and TRDIORA_1 settings 1: FTIOA1 pin output is disabled regardless of the TRDPMR, TRDFCR, and TRDIORA_1 settings (FTIOA1 pin is operated as an I/O port). R/W 3 ED0 Master enable 0: FTIOD0 pin output is enabled according to the D0 TRDPMR, TRDFCR, and TRDIORC_0 settings 1: FTIOD0 pin output is disabled regardless of the TRDPMR, TRDFCR, and TRDIORC_0 settings (FTIOD0 pin is operated as an I/O port). R/W 2 EC0 Master enable 0: FTIOC0 pin output is enabled according to the C0 TRDPMR, TRDFCR, and TRDIORC_0 settings 1: FTIOC0 pin output is disabled regardless of the TRDPMR, TRDFCR, and TRDIORC_0 settings (FTIOC0 pin is operated as an I/O port). R/W 1 EB0 Master enable 0: FTIOB0 pin output is enabled according to the B0 TRDPMR, TRDFCR, and TRDIORA_0 settings 1: FTIOB0 pin output is disabled regardless of the TRDPMR, TRDFCR, and TRDIORA_0 settings (FTIOB0 pin is operated as an I/O port). R/W 0 EA0 Master enable 0: FTIOA0 pin output is enabled according to the A0 TRDPMR, TRDFCR, and TRDIORA_0 settings 1: FTIOA0 pin output is disabled regardless of the TRDPMR, TRDFCR, and TRDIORA_0 settings (FTIOA0 pin is operated as an I/O port). R/W TRDOER1 enables/disables the outputs for channel 0 and channel 1. When TRDOI is selected for inputs, if a low level signal is input to TRDOI, the bits in TRDOER1 are set to 1 to disable the output for timer RD. Rev. 1.00 Oct. 03, 2008 Page 512 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.6 Timer RD Output Master Enable Register 2 (TRDOER2) Address: H'FFFFD7 Bit: b7 PTO b6 b5 b4 b3 b2 b1 b0 Value after reset: 0 1 1 1 1 1 1 1 Bit 7 Symbol PTO Bit Name Description R/W Timer output 0: The corresponding bit in TRDOER1 is not set to 1 R/W disabled mode when the low level is input to the TRDOI pin 1: The corresponding bit in TRDOER1 is set to 1 when the low level is input to the TRDOI pin 6 to 0 Reserved These bits are read as 1. The write value should be 1. 16.2.7 Timer RD Output Control Register (TRDOCR) Address: H'FFFFD8 Bit: b7 TOD1 b6 TOC1 b5 TOB1 b4 TOA1 b3 TOD0 b2 TOC0 b1 TOB0 b0 TOA0 Value after reset: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 Symbol TOD1 TOC1 TOB1 TOA1 TOD0 Bit Name Output level select D1 Output level select C1 Output Level Select B1 Output level select A1 Output level select D0 Description 0: 0 output at the FTIOD1 pin* 1: 1 output at the FTIOD1 pin* 0: 0 output at the FTIOC1 pin* 1: 1 output at the FTIOC1 pin* 0: 0 output at the FTIOB1 pin* 1: 1 output at the FTIOB1 pin* 0: 0 output at the FTIOA1 pin* 1: 1 output at the FTIOA1 pin* 0: 0 output at the FTIOD0 pin* 1: 1 output at the FTIOD0 pin* R/W R/W R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 513 of 962 REJ09B0465-0100 Section 16 Timer RD Bit 2 1 Symbol TOC0 TOB0 Bit Name Output level select C0 Output level select B0 Description 0: 0 output at the FTIOC0 pin* 1: 1 output at the FTIOC0 pin* * In modes other than PWM3 mode 0: 0 output at the FTIOB0 pin* 1: 1 output at the FTIOB0 pin* * In PWM3 mode 0: 1 output at the FTIOB0 pin on GRB_1 compare match and 0 output at the FTIOB0 pin on GRB_0 compare match 1: 0 output at the FTIOB0 pin on GRB_1 compare match and 1 output at the FTIOB0 pin on GRB_0 compare match R/W R/W R/W 0 TOA0 Output level select A0 * In modes other than PWM3 mode 0: 0 output at the FTIOA0 pin* 1: 1 output at the FTIOA0 pin* R/W * In PWM3 mode 0: 1 output at the FTIOB0 pin on GRA_1 compare match and 0 output at the FTIOB0 pin on GRA_0 compare match 1: 0 output at the FTIOB0 pin on GRA_1 compare match and 1 output at the FTIOB0 pin on GRA_0 compare match Note: * The change of the setting is immediately reflected in the output value. TRDOCR selects the initial outputs before the first occurrence of a compare match. Note that bits OLS1 and OLS0 in TRDFCR set these initial outputs in reset synchronous PWM mode and complementary PWM mode. In PWM3 mode, TRDOCR selects the output level of the FTIOA0 and FTIOB0 pins. Rev. 1.00 Oct. 03, 2008 Page 514 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.8 Timer RD A/D Conversion Start Trigger Control Register (TRDADCR) Address: H'FFFFD9 Bit: b7 b6 b5 b4 b3 b2 b1 b0 ADTRGD1E ADTRGC1E ADTRGB1E TDTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E Value after reset: 0 0 0 0 0 0 0 0 Bit 7 Symbol Bit Name Description 0: A/D conversion start trigger is not generated by compare match of GRD_1 1: A/D conversion start trigger is generated by compare match of GRD_1 0: A/D conversion start trigger is not generated by compare match of GRC_1 1: A/D conversion start trigger is generated by compare match of GRC_1 R/W R/W ADTRGD1E A/D conversion start trigger D1 enable ADTRGC1E A/D conversion start trigger C1 enable 6 R/W 5 ADTRGB1E A/D 0: A/D conversion start trigger is not generated by conversion compare match of GRB_1 start trigger B1 1: A/D conversion start trigger is generated by enable compare match of GRB_1 ADTRGA1E A/D 0: A/D conversion start trigger is not generated by conversion compare match of GRA_1 start trigger A1 1: A/D conversion start trigger is generated by enable compare match of GRA_1 ADTRGD0E A/D conversion start trigger D0 enable ADTRGC0E A/D conversion start trigger C0 enable 0: A/D conversion start trigger is not generated by compare match of GRD_0 1: A/D conversion start trigger is generated by compare match of GRD_0 0: A/D conversion start trigger is not generated by compare match of GRC_0 1: A/D conversion start trigger is generated by compare match of GRC_0 R/W 4 R/W 3 R/W 2 R/W 1 ADTRGB0E A/D 0: A/D conversion start trigger is not generated by conversion compare match of GRB_0 start trigger B0 1: A/D conversion start trigger is generated by enable compare match of GRB_0 R/W Rev. 1.00 Oct. 03, 2008 Page 515 of 962 REJ09B0465-0100 Section 16 Timer RD Bit 0 Symbol Bit Name Description R/W R/W ADTRGA0E A/D 0: A/D conversion start trigger is not generated by conversion compare match of GRA_0 start trigger A0 1: A/D conversion start trigger is generated by enable compare match of GRA_0 TRDADCR selects the trigger source to start A/D conversion. A/D conversion start trigger is generated by a corresponding compare match. 16.2.9 Timer RD Counter (TRDCNT) Address: H'FFFFB0, H'FFFFBA Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Timer RD has two TRDCNT counters (TRDCNT_0 and TRDCNT_1), one for each channel. The TRDCNT counters are 16-bit readable/writable registers that increment/decrement according to input clocks. Input clocks can be selected by bits TPSC2 to TPSC0 in TRDCR. TRDCNT_0 and TRDCNT_1 increment/decrement in complementary PWM mode while they only increment in other modes. The TRDCNT counters are initialized to H'0000 by compare matches with corresponding GRA, GRB, GRC, or GRD, or input captures to GRA, GRB, GRC, or GRD (counter clearing function). When the TRDCNT counters overflow, an OVF flag in TRDSR for the corresponding channel is set to 1. When TRDCNT_1 underflows, an UDF flag in TRDSR is set to 1. The TRDCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Rev. 1.00 Oct. 03, 2008 Page 516 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.10 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD) GRA Address: H'FFFFB2, H'FFFFBC Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GRB Address: H'FFFFB4, H'FFFFBE Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GRC Address: H'FFFFB6, H'FFFFC0 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GRD Address: H'FFFFB8, H'FFFFC2 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. 1.00 Oct. 03, 2008 Page 517 of 962 REJ09B0465-0100 Section 16 Timer RD GR are 16-bit registers. Timer RD has eight general registers (GR), four for each channel. The GR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. Functions can be switched by TRDIORA and TRDIORC. The values in GR and TRDCNT are constantly compared with each other when the GR registers are used as output compare registers. When the both values match, the IMFA to IMFD flags in TRDSR are set to 1. Compare match outputs can be selected by TRDIORA and TRDIORC. When the GR registers are used as input capture registers, the TRDCNT value is stored after detecting external signals. At this point, IMFA to IMFD flags in the corresponding TRDSR are set to 1. Detection edges for input capture signals can be selected by TRDIORA and TRDIORC. When PWM mode, complementary PWM mode, or reset synchronous PWM mode is selected, the values in TRDIORA and TRDIORC are ignored. Upon reset, the GR registers are set as output compare registers (no output) and initialized to H'FFFF. The GR registers cannot be accessed in 8bit units; they must always be accessed as a 16-bit unit. Rev. 1.00 Oct. 03, 2008 Page 518 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.11 Timer RD Control Register (TRDCR) Address: H'FFFFCA, H'FFFFD1 Bit: b7 b6 CCLR[2:0] Value after reset: 0 0 0 0 b5 b4 CKEG[1:0] 0 0 b3 b2 b1 TPSC[2:0] 0 0 b0 Bit Symbol Bit Name Counter clear 2 to 0 Description 000: Disables TRDCNT clearing 001: Clears TRDCNT by GRA compare match/input 1 capture* 010: Clears TRDCNT by GRB compare match/input 1 capture* 011: Synchronization clear; Clears TRDCNT in synchronous with counter clearing of the other 2 channel's timer* 100: Disables TRDCNT clearing 101: Clears TRDCNT by GRC compare match/input 1 capture* 110: Clears TRDCNT by GRD compare match/input 1 capture* 111: Synchronization clear; Clears TRDCNT in synchronous with counter clearing of the other channel's timer*2 R/W R/W 7 to 5 CCLR[2:0] 4, 3 CKEG[1:0] Clock edge 1 and 0 00: Count at rising edge 01: Count at falling edge 1X: Count at both edges R/W Rev. 1.00 Oct. 03, 2008 Page 519 of 962 REJ09B0465-0100 Section 16 Timer RD Bit Symbol Bit Name Description R/W R/W 2 to 0 TPSC[2:0] *3*4 Time 000: Internal clock: count by prescaler 2 to 001: Internal clock: count by /2 0 010: Internal clock: count by /4 011: Internal clock: count by /8 100: Internal clock: count by /32 101: External clock: count by FTIOA0 (TCLK) pin input 110: Internal clock: count by 40M 111: Reserved (setting prohibited) [Legend] X: Don't care Notes: 1. When GR functions as an output compare register, TRDCNT is cleared by compare match. When GR functions as input capture, TRDCNT is cleared by input capture. 2. Synchronous operation is set by TRDMDR. 3. If the internal /40 clock is selected, the high-speed on-chip oscillator must be operating. As long as the internal 40 clock is selected, do not stop the high-speed onchip oscillator. When the counter clock is switched over, the counter should be halted. 4. When the internal 40 clock is selected, restrictions on access to registers are applied. For details, see section 16.5, Usage Notes. (11) Restrictions on Access to Registers when Internal 40 Clock is Selected as Counter Clock. TRDCR selects a TRDCNT counter clock, an edge when an external clock is selected, and counter clearing sources. Timer RD has a total of two TRDCR registers, one for each channel. Rev. 1.00 Oct. 03, 2008 Page 520 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.12 Timer RD I/O Control Registers (TRDIORA and TRDIORC) TRDIORA Address: H'FFFFC5, H'FFFFCC Bit: b7 b6 IOB2 0 b5 IOB[1:0] 0 b4 b3 b2 IOA2 0 b1 IOA[1:0] 0 b0 Value after reset: TRDIORC 1 0 1 0 Address: H'FFFFD6, H'FFFFCD Bit: b7 IOD3 Value after reset: 2 b6 IOD2 0 0 b5 IOD[1:0] 0 b4 b3 IOC3 1 b2 IOC2 0 0 b1 IOC[1:0] 0 b0 * TRDIORA Bit 7 6 Symbol IOB2 Bit Name Reserved Description This bit is read as 1. The write value should be 1. 0: GRB functions as an output compare register 1: GRB functions as an input capture register 5, 4 IOB[1:0] I/O control B1 When IOB2 = 0, and B0 00: No output at compare match 01: 0 output to the FTIOB pin at GRB compare match 10: 1 output to the FTIOB pin at GRB compare match 11: Output toggles to the FTIOB pin at GRB compare match When IOB2 = 1, 00: Input capture to GRB at rising edge at the FTIOB pin 01: Input capture to GRB at falling edge at the FTIOB pin 1X: Input capture to GRB at rising and falling edges at the FTIOB pin R/W R/W R/W I/O control B2 Selects the GRB function. Rev. 1.00 Oct. 03, 2008 Page 521 of 962 REJ09B0465-0100 Section 16 Timer RD Bit 3 2 Symbol IOA2 Bit Name Reserved Description This bit is read as 1. The write value should be 1. 0: GRA functions as an output compare register 1: GRA functions as an input capture register R/W R/W I/O control A2 Selects the GRA function. 1, 0 IOA[1:0] I/O control A1 When IOA2 = 0, and A0 00: No output at compare match 01: 0 output to the FTIOA pin at GRA compare match 10: 1 output to the FTIOA pin at GRA compare match 11: Output toggles to the FTIOA pin at GRA compare match When IOA2 = 1, 00: Input capture to GRA at rising edge at the FTIOA pin 01: Input capture to GRA at falling edge at the FTIOA pin 1X: Input capture to GRA at rising and falling edges at the FTIOA pin R/W [Legend] X: Don't care. Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings in the IOA2 and IOB2 bits in TRDIORA and the IOC2 and IOD2 bits in TRDIORC of both registers should be the same. The IOA3 bit exists only in TRDIORA_0. 2. In PWM mode, PWM3 mode, complementary PWM mode, and reset synchronous PWM mode, the settings of TRDIORA are invalid. TRDIORA selects whether GRA or GRB is used as an output compare register or an input capture register. When an output compare register is selected, the output setting is selected. When an input capture register is selected, an input edge of an input capture signal is selected. TRDIORA also selects the function of FTIOA or FTIOB pin. Rev. 1.00 Oct. 03, 2008 Page 522 of 962 REJ09B0465-0100 Section 16 Timer RD * TRDIORC Bit 7 Symbol IOD3 Bit Name Description R/W R/W I/O control D3 Specifies GRD to be used as GR for the FTIOB or FTIOD pin. 0: GRD is used as GR for the FTIOB pin 1: GRD is used as GR for the FTIOD pin 6 IOD2 I/O control D2 Selects the GRD function. 0: GRD functions as an output compare register 1: GRD functions as an input capture register R/W 5, 4 IOD[1:0] I/O control D1 When IOD3 = 0, and D0 00: No output at compare match 01: 0 output to the FTIOB pin at GRD compare match 10: 1 output to the FTIOB pin at GRD compare match 11: Output toggles to the FTIOB pin at GRD compare match When IOD3 = 1 and IOD2 = 0, 00: No output at compare match 01: 0 output to the FTIOD pin at GRD compare match 10: 1 output to the FTIOD pin at GRD compare match 11: Output toggles to the FTIOD pin at GRD compare match When IOD3 = 1 and IOD2 = 1, 00: Input capture to GRD at rising edge at the FTIOD pin 01: Input capture to GRD at falling edge at the FTIOD pin 1X: Input capture to GRD at rising and falling edges at the FTIOD pin R/W 3 IOC3 I/O control C3 Specifies GRC to be used as GR for the FTIOA or FTIOC pin. 0: GRC is used as GR for the FTIOA pin 1: GRC is used as GR for the FTIOC pin R/W Rev. 1.00 Oct. 03, 2008 Page 523 of 962 REJ09B0465-0100 Section 16 Timer RD Bit 2 Symbol IOC2 Bit Name Description R/W R/W I/O control C2 Selects the GRC function. 0: GRC functions as an output compare register 1: GRC functions as an input capture register 1, 0 IOC[1:0] I/O control C1 When IOC3 = 0, and C0 00: No output at compare match 01: 0 output to the FTIOA pin at GRC compare match 10: 1 output to the FTIOA pin at GRC compare match 11: Output toggles to the FTIOA pin at GRC compare match When IOC3 = 1 and IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC3 = 1 and IOC2 = 1, 00: Input capture to GRC at rising edge at the FTIOC pin 01: Input capture to GRC at falling edge at the FTIOC pin 1X: Input capture to GRC at rising and falling edges at the FTIOC pin R/W [Legend] X: Don't care. Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings in the IOA2 and IOB2 bits in TRDIORA and the IOC2 and IOD2 bits in TRDIORC of both registers should be the same. 2. In PWM mode, PWM3 mode, complementary PWM mode, and reset synchronous PWM mode, the settings of TRDIORC are invalid. TRDIORC selects whether GRC or GRD is used as an output compare register or an input capture register. When an output compare register is selected, the output setting is selected. When an input capture register is selected, an input edge of an input capture signal is selected. TRDIORC also selects the function of the FTIOA to FTIOD pins. Rev. 1.00 Oct. 03, 2008 Page 524 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.13 Timer RD Status Register (TRDSR) Address: H'FFFFC7, H'FFFFCE Bit: b7 b6 b5 UDF 0 b4 OVF 0 b3 IMFD 0 b2 IMFC 0 b1 IMFB 0 b0 IMFA 0 Value after reset: 1 1 Bit 7, 6 5 Symbol UDF* Bit Name Reserved Description These bits are read as 1. The write value should be 1. 1: TRDCNT_1 has underflowed. [Setting condition] * When TRDCNT underflows [Clearing condition] * When 0 is written to UDF after reading UDF = 1 R/W R/W Underflow flag 0: TRDCNT_1 has not underflowed. 4 OVF Overflow flag 0: TRDCNT has not overflowed. 1: TRDCNT has overflowed. [Setting condition] * When TRDCNT value is underflowed [Clearing condition] When 0 is written to OVF after reading OVF = 1 R/W 3 IMFD Input capture/ [Setting conditions] compare * When TRDCNT = GRD and GRD is functioning match flag D as output compare register * When TRDCNT = GRD while the FTIOD pin operates in PWM mode * When TRDCNT = GRD in PWM3 mode, reset synchronous PWM mode, or complementary PWM mode * When TRDCNT value is transferred to GRD by input capture signal and GRD is functioning as input capture register [Clearing conditions] * * When the DTC is activated by an IMFD interrupt and the DISEL bit in MRB of the DTC is 0 When 0 is written to IMFD after reading IMFD = 1 R/W Rev. 1.00 Oct. 03, 2008 Page 525 of 962 REJ09B0465-0100 Section 16 Timer RD Bit 2 Symbol IMFC Bit Name Description R/W R/W Input capture/ [Setting conditions] compare * When TRDCNT = GRC and GRC is functioning match flag C as output compare register * * When TRDCNT = GRC while the FTIOC pin operates in PWM mode When TRDCNT = GRC in PWM3 mode, reset synchronous PWM mode, or complementary PWM mode When TRDCNT value is transferred to GRC by input capture signal and GRC is functioning as input capture register When the DTC is activated by an IMFC interrupt and the DISEL bit in MRB of the DTC is 0 When 0 is written to IMFC after reading IMFC = 1 * [Clearing conditions] * * 1 IMFB Input capture/ [Setting conditions] compare * When TRDCNT = GRB and GRB is functioning match flag B as output compare register * * When TRDCNT = GRB while the FTIOB pin operates in PWM mode When TRDCNT = GRB in PWM mode, PWM3 mode, reset synchronous PWM mode, or complementary PWM mode (in reset synchronous PWM mode, however, while TRDCNT_0 = GRB_1 and TRDCNT_0 = GRB_0) When TRDCNT value is transferred to GRB by input capture signal and GRB is functioning as input capture register When the DTC is activated by an IMFB interrupt and the DISEL bit in MRB of the DTC is 0 When 0 is written to IMFB after reading IMFB = 1 R/W * [Clearing conditions] * * Rev. 1.00 Oct. 03, 2008 Page 526 of 962 REJ09B0465-0100 Section 16 Timer RD Bit 0 Symbol IMFA Bit Name Description R/W R/W Input capture/ [Setting conditions] compare * When TRDCNT = GRA and GRA is functioning match flag A as output compare register * When TRDCNT = GRA in PWM mode, PWM3 mode, reset synchronous PWM mode, or complementary PWM mode (in reset synchronous PWM mode, however, while TRDCNT_0 = GRA_1 and TRDCNT_0 = GRA_0) When TRDCNT value is transferred to GRA by input capture signal and GRA is functioning as input capture register When the DTC is activated by an IMFA interrupt and the DISEL bit in MRB of the DTC is 0 When 0 is written to IMFA after reading IMFA = 1 * [Clearing conditions] * * Note: * Bit 5 is not the UDF flag in TRDSR_0. It is a reserved bit. It is always read as 1. TRDSR is each interrupt request flag of the timer RD. If an interrupt is enabled by a corresponding bit in TRDIER, TRDSR requests an interrupt for the CPU. Timer RD has two TRDSR registers, one for each channel. Rev. 1.00 Oct. 03, 2008 Page 527 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.14 Timer RD Interrupt Enable Register (TRDIER) Address: H'FFFFC8, H'FFFFCF Bit: b7 b6 b5 b4 OVIE 0 b3 IMIED 0 b2 IMIEC 0 b1 IMIEB 0 b0 IMIEA 0 Value after reset: 1 1 1 Bit Symbol Bit Name Reserved Description These bits are read as 1. The write value should be 1. R/W R/W 7 to 5 4 OVIE Overflow interrupt 0: Interrupt requests (OVI) by OVF or UDF flag are enable disabled. 1: Interrupt requests (OVI) by OVF or UDF flag are enabled. 3 IMIED Input capture/ 0: Interrupt requests (IMID) by IMFD flag are disabled. R/W compare match 1: Interrupt requests (IMID) by IMFD flag are enabled. interrupt enable D Input capture/ 0: Interrupt requests (IMIC) by IMFC flag are disabled. R/W compare match 1: Interrupt requests (IMIC) by IMFC flag are enabled. interrupt enable C Input capture/ 0: Interrupt requests (IMIB) by IMFB flag are disabled. compare match 1: Interrupt requests (IMIB) by IMFB flag are enabled. interrupt enable B Input capture/ 0: Interrupt requests (IMIA) by IMFA flag are disabled. compare match 1: Interrupt requests (IMIA) by IMFA flag are enabled. interrupt enable A R/W 2 IMIEC 1 IMIEB 0 IMIEA R/W Timer RD has two TRDIER registers, one for each channel. Rev. 1.00 Oct. 03, 2008 Page 528 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.15 PWM Mode Output Level Control Register (POCR) Address: H'FFFFC9, H'FFFFD0 Bit: b7 b6 b5 b4 b3 b2 POLD 0 b1 POLC 0 b0 POLB 0 Value after reset: 1 1 1 1 1 Bit Symbol Bit Name Reserved PWM mode output level control D PWM mode output level control C PWM mode output level control B Description These bits are read as 1. The write value should be 1. 0: The output level of FTIOD is active low. 1: The output level of FTIOD is active high. 0: The output level of FTIOC is active low. 1: The output level of FTIOC is active high. 0: The output level of FTIOB is active low. 1: The output level of FTIOB is active high. R/W R/W R/W R/W 7 to 3 2 1 0 POLD POLC POLB Timer RD has two POCR registers, one for each channel. Rev. 1.00 Oct. 03, 2008 Page 529 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.16 Timer RD Digital Filtering Function Select Register (TRDDF) Address: H'FFFFCA, H'FFFFD1 Bit: b7 DFCK[1:0] Value after reset: 0 0 b6 b5 b4 b3 DFD 0 b2 DFC 0 b1 DFB 0 b0 DFA 0 0 0 Bit 7, 6 Symbol DFCK[1:0] Bit Name Digital filter clock select Description 00: /32 01: /8 10: 11: Clock specified by bits TPSC2 to TPSC0 in TRDCR R/W R/W 5, 4 3 2 1 0 DFD DFC DFB DFA Reserved Digital filter function D Digital filter function C Digital filter function B Digital filter function A These bits are read as 0. The write value should be 0. 0: Disables the digital filter for the FTIOD pin 1: Enables the digital filter for the FTIOD pin 0: Disables the digital filter for the FTIOC pin 1: Enables the digital filter for the FTIOC pin 0: Disables the digital filter for the FTIOB pin 1: Enables the digital filter for the FTIOB pin 0: Disables the digital filter for the FTIOA pin 1: Enables the digital filter for the FTIOA pin R/W R/W R/W R/W Note: The setting in this register is valid on the corresponding pin when the FTIOA to FTIOD inputs are enabled by TRDIORA and TRDIORC. Timer RD has two TRDDF registers, one for each channel. Rev. 1.00 Oct. 03, 2008 Page 530 of 962 REJ09B0465-0100 Section 16 Timer RD 16.2.17 Interface with CPU (1) 16-Bit Register TRDCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be accessed in a 16-bit unit. Figure 16.5 shows an example of accessing the 16-bit registers. Internal data bus H C P U L Bus interface Module data bus TRDCNTH TRDCNTL Figure 16.5 Accessing Operation of 16-Bit Register (between CPU and TRDCNT (16 bits)) (2) 8-Bit Register Registers other than TRDCNT and GR are 8-bit registers that are connected internally with the CPU in an 8-bit width. Figure 16.6 shows an example of accessing the 8-bit registers. Internal data bus H C P U L Bus interface Module data bus TRDSTR Figure 16.6 Accessing Operation of 8-Bit Register (between CPU and TRDSTR (8 bits)) Rev. 1.00 Oct. 03, 2008 Page 531 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3 Operation Timer RD has the following operating modes. * Timer mode operation Enables output compare and input capture functions by setting the IOA2 to IOA0 and IOB2 to IOB0 bits in TRDIORA and the IOC3 to IOC0 and IOD3 to IOD0 bits in TRDIORC * PWM mode operation Enables PWM mode operation by setting TRDPMR * PWM3 mode operation Enables PWM3 mode operation by setting the PWM3 bit in TRDFCR * Reset synchronous PWM mode operation Enables reset synchronous PWM mode operation by setting the CMD1 and CMD0 bits in TRDFCR * Complementary PWM mode operation Enables complementary PWM mode operation by setting the CMD1 and CMD0 bits in TRDFCR The following tables show the operating modes of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pins set by the appropriate bits in the registers mentioned above. Set 1 to the PMR bits corresponding to the pins allocated by the PMC. Rev. 1.00 Oct. 03, 2008 Page 532 of 962 REJ09B0465-0100 Section 16 Timer RD * FTIOA0 pin Register Name Bit Name Setting values TRDOER1 EA0 0 0 STCLK 0 0 TRDFCR CMD1, CMD0 00 00 PWM3 0 1 TRDIORA IOA2 to IOA0 XXX 001, 01X Function PWM3 mode waveform output Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when the corresponding pin PCR = 0) External clock input Setting prohibited X 0 00 1 1XX X 0 00 1 000 X 1 XX X 0XX Other than above Rev. 1.00 Oct. 03, 2008 Page 533 of 962 REJ09B0465-0100 Section 16 Timer RD * FTIOB0 pin Register Name Bit Name Setting values TRDOER1 EB0 0 0 TRDFCR CMD1, CMD0 10, 11 01 PWM3 X X TRDPMR PWMB0 X X TRDIORA IOB2 to IOB0 XXX XXX Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM3 mode waveform output PWM mode waveform output Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when the corresponding pin PCR = 0) Setting prohibited 0 0 0 00 00 00 0 1 1 X 1 0 XXX XXX 001, 01X X 00 1 0 1XX X 00 1 0 000 Other than above Rev. 1.00 Oct. 03, 2008 Page 534 of 962 REJ09B0465-0100 Section 16 Timer RD * FTIOC0 pin Register Name Bit Name Setting values TRDOER1 EC0 0 0 TRDFCR CMD1, CMD0 10, 11 01 PWM3 X X TRDPMR PWMC0 X X TRDIORC IOC2 to IOC0 XXX XXX Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform out Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when the corresponding pin PCR = 0) Setting prohibited 0 0 00 00 1 1 1 0 XXX 001, 01X X 00 1 0 1XX X 00 1 0 000 Other than above Rev. 1.00 Oct. 03, 2008 Page 535 of 962 REJ09B0465-0100 Section 16 Timer RD * FTIOD0 pin Register Name Bit Name Setting values TRDOER1 ED0 0 0 TRDFCR CMD1, CMD0 10, 11 01 PWM3 X X TRDPMR PWMD0 X X TRDIORC IOD2 to IOD0 XXX XXX Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform out Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when the corresponding pin PCR = 0) Setting prohibited 0 0 00 00 1 1 1 0 XXX 001, 01X X 00 1 0 1XX X 00 1 0 000 Other than above Rev. 1.00 Oct. 03, 2008 Page 536 of 962 REJ09B0465-0100 Section 16 Timer RD * FTIOA1 pin Register Name Bit Name Setting values TRDOER1 EA1 0 0 0 X X TRDFCR CMD1, CMD0 10, 11 01 00 00 00 PWM3 X X 1 1 1 TRDIORA IOA2 to IOA0 XXX XXX 001, 01X 1XX 000 Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when the corresponding pin PCR = 0) Setting prohibited Other than above Rev. 1.00 Oct. 03, 2008 Page 537 of 962 REJ09B0465-0100 Section 16 Timer RD * FTIOB1 pin Register Name Bit Name Setting values TRDOER1 EB1 0 0 0 0 TRDFCR CMD1, CMD0 10, 11 01 00 00 PWM3 X X 1 1 TRDPMR PWMB1 X X 1 0 TRDIORA IOB2 to IOB0 XXX XXX XXX 001, 01X Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform out Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when the corresponding pin PCR = 0) Setting prohibited X 00 1 0 1XX X 00 1 0 000 Other than above Rev. 1.00 Oct. 03, 2008 Page 538 of 962 REJ09B0465-0100 Section 16 Timer RD * FTIOC1 pin Register Name Bit Name Setting values TRDOER1 EC1 0 0 0 0 TRDFCR CMD1, CMD0 10, 11 01 00 00 PWM3 X X 1 1 TRDPMR PWMC1 X X 1 0 TRDIORC IOC2 to IOC0 XXX XXX XXX 001, 01X Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform out Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when the corresponding pin PCR = 0) Setting prohibited X 00 1 0 1XX X 00 1 0 000 Other than above Rev. 1.00 Oct. 03, 2008 Page 539 of 962 REJ09B0465-0100 Section 16 Timer RD * FTIOD1 pin Register Name Bit Name Setting values TRDOER1 ED1 0 0 0 0 TRDFCR CMD1, CMD0 10, 11 01 00 00 PWM3 X X 1 1 TRDPMR PWMD1 X X 1 0 TRDIORC IOD2 to IOD0 XXX XXX XXX 001, 01X Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform out Timer mode waveform output (output compare function) Timer mode (input capture function) General input port (when the corresponding pin PCR = 0) Setting prohibited X 00 1 0 1XX X 00 1 0 000 Other than above Rev. 1.00 Oct. 03, 2008 Page 540 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.1 Counter Operation When one of bits STR0 and STR1 in TRDSTR is set to 1, the TRDCNT counter for the corresponding channel begins counting. TRDCNT can operate as a free-running counter, periodic counter, for example. Figure 16.7 shows an example of the counter operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TRDCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TRDCR. For periodic counter operation, select the TRDCNT clearing source with bits CCLR2 to CCLR0 in TRDCR. Designate the general register selected in [2] as an output compare register by means of TRDIOR. Set the periodic counter cycle in the general register selected in [2]. Set the STR bit in TRDSTR to 1 to start the counter operation. Operation selection [1] Select counter clock [2] Periodic counter Free-running counter [3] Select counter clearing source [2] [4] Select output compare register [3] [5] Set period [4] Start count operation [5] Figure 16.7 Example of Counter Operation Setting Procedure Rev. 1.00 Oct. 03, 2008 Page 541 of 962 REJ09B0465-0100 Section 16 Timer RD (1) Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the TRDCNT counters for channels 0 and 1 are all designated as freerunning counters. When the relevant bit in TRDSTR is set to 1, the corresponding TRDCNT counter starts an increment operation as a free-running counter. When TRDCNT overflows, the OVF flag in TRDSR is set to 1. If the value of the OVIE bit in the corresponding TRDIER is 1 at this point, timer RD requests an interrupt. After overflow, TRDCNT starts an increment operation again from H'0000. Figure 16.8 illustrates free-running counter operation. TRDCNT value H'FFFF H'0000 Time STR0, STR1 OVF Figure 16.8 Free-Running Counter Operation When compare match is selected as the TRDCNT clearing source, the TRDCNT counter for the relevant channel performs periodic count operation. The GR registers for setting the period are designated as output compare registers, and counter clearing by compare match is selected by means of bits CCLR1 and CCLR0 in TRDCR. After the settings have been made, TRDCNT starts an increment operation as a periodic counter when the corresponding bit in TRDSTR is set to 1. When the count value matches the value in GR, the IMFA, IMFB, IMFC, or IMFD flag in TRDSR is set to 1 and TRDCNT is cleared to H'0000. If the value of the corresponding IMIEA, IMIEB, IMIEC, or IMIED bit in TRDIER is 1 at this point, timer RD requests an interrupt. After a compare match, TRDCNT starts an increment operation again from H'0000. Rev. 1.00 Oct. 03, 2008 Page 542 of 962 REJ09B0465-0100 Section 16 Timer RD Figure 16.9 illustrates periodic counter operation. TRDCNT value Counter cleared by GR compare match GR value H'0000 Time STR IMF Figure 16.9 Periodic Counter Operation (2) TRDCNT Count Timing * Internal clock operation A system clock (), four types of clocks (/2, /4, /8, or /32) that are generated by dividing the system clock, or on-chip oscillator clock (40M) can be selected by bits TPSC2 to TPSC0 in TRDCR. Figure 16.10 illustrates this timing. Internal clock TRDCNT input TRDCNT N -1 N N+1 Figure 16.10 Count Timing in Internal Clock Operation Rev. 1.00 Oct. 03, 2008 Page 543 of 962 REJ09B0465-0100 Section 16 Timer RD * External clock operation An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TRDCR, and a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the rising edge, falling edge, or both edges can be selected. Figure 16.11 illustrates the detection timing of the rising and falling edges. External clock input pin TRDCNT input TRDCNT N-1 N N+1 Figure 16.11 Count Timing in External Clock Operation (Both Edges Detected) 16.3.2 Waveform Output by Compare Match Timer RD can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or FTIOD output pin using compare match A, B, C, or D. Figure 16.12 shows an example of the setting procedure for waveform output by compare match. Output selection [1] Select 0 output, 1 output, or toggle output as a compare much output, by means of TRDIOR. The initial values set in TRDOCR are output unit the first compare match occurs. Set the timing for compare match generation in GRA/GRB/GRC/GRD. Enable or disable the timer output by TRDOER1. Set the STR bit in TRDSTR to 1 to start the TRDCNT count operation. Select waveform output mode [1] Set output timing Enable waveform output Start count operation [2] [2] [3] [3] [4] [4] Figure 16.12 Example of Setting Procedure for Waveform Output by Compare Match Rev. 1.00 Oct. 03, 2008 Page 544 of 962 REJ09B0465-0100 Section 16 Timer RD (1) Examples of Waveform Output Operation Figure 16.13 shows an example of 0 output/1 output. In this example, TRDCNT has been designated as a free-running counter, and settings have been made such that 0 is output by compare match A, and 1 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TRDCNT value H'FFFF H'0000 FTIOB No change No change No change No change Time FTIOA Figure 16.13 Example of 0 Output/1 Output Operation Figure 16.14 shows an example of toggle output. In this example, TRDCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. Rev. 1.00 Oct. 03, 2008 Page 545 of 962 REJ09B0465-0100 Section 16 Timer RD TRDCNT value GRB GRA H'0000 FTIOB Time Toggle output FTIOA Toggle output Figure 16.14 Example of Toggle Output Operation (2) Output Compare Timing The compare match signal is generated in the last state in which TRDCNT and GR match (when TRDCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TRDIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TRDCNT matches GR, the compare match signal is generated only after the next TRDCNT input clock pulse is input. Figure 16.15 shows an example of the output compare timing. TRDCNT input TRDCNT N N+1 GR N Compare match signal FTIOA to FTIOD Figure 16.15 Output Compare Timing Rev. 1.00 Oct. 03, 2008 Page 546 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.3 Input Capture Function The TRDCNT value can be transferred to GR on detection of the input edge of the input capture/output compare pin (FTIOA, FTIOB, FTIOC, or FTIOD). Rising edge, falling edge, or both edges can be selected as the detected edge. When the input capture function is used, the pulse width or period can be measured. Figure 16.16 shows an example of the input capture operation setting procedure. Input selection Select input edge of input capture Start counter operation [1] Designate GR as an input capture register by means of TRDIOR, and select rising edge, falling edge, or both edges as the input edge of the input capture signal. Set the STR bit in TRDSTR to 1 to start the TRDCNT counter operation. [1] [2] [2] Figure 16.16 Example of Input Capture Operation Setting Procedure Rev. 1.00 Oct. 03, 2008 Page 547 of 962 REJ09B0465-0100 Section 16 Timer RD (1) Example of Input Capture Operation Figure 16.17 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the FTIOA pin input capture input edge, the falling edge has been selected as the FTIOB pin input capture input edge, and counter clearing by GRB input capture has been designated for TRDCNT. Counter cleared by FTIOB input (falling edge) TRDCNT value H'0180 H'0160 H'0005 H'0000 Time FTIOB FTIOA GRA H'0005 H'0160 GRB H'0180 Figure 16.17 Example of Input Capture Operation Rev. 1.00 Oct. 03, 2008 Page 548 of 962 REJ09B0465-0100 Section 16 Timer RD (2) Input Capture Signal Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TRDIOR. Figure 16.18 shows the timing when the rising edge is selected. Input capture input Input capture signal TRDCNT N GR N Figure 16.18 Input Capture Signal Timing Rev. 1.00 Oct. 03, 2008 Page 549 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.4 Synchronous Operation In synchronous operation, the values in a number of TRDCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TRDCNT counters can be cleared simultaneously by making the appropriate setting in TRDCR (synchronous clearing). Synchronous operation enables GR to be increased with respect to a single time base. Figure 16.19 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TRDCNT [2] Clearing source generation channel? Yes Select counter clearing source No [3] Select counter clearing source [4] Start counter operation [5] Start counter operation [5] Set the SYNC bits in TRDMDR to 1. When a value is written to either of the TRDCNT counters, the same value is simultaneously written to the other TRDCNT counter. Set bits CCLR1 and CCLR0 in TRDCR to specify counter clearing by compare match/input capture. Set bits CCLR1 and CCLR0 in TRDCR to designate synchronous clearing for the counter clearing source. Set the STR bit in TRDSTR to 1 to start the count operation. Figure 16.19 Example of Synchronous Operation Setting Procedure Rev. 1.00 Oct. 03, 2008 Page 550 of 962 REJ09B0465-0100 Section 16 Timer RD Figure 16.20 shows an example of synchronous operation. In this example, synchronous operation has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. The same input clock has been set for the channel 0 and channel 1 counter input clocks. Two-phase PWM waveforms are output from pins FTIOB0 and FTIOB1. At this time, synchronous presetting and synchronous operation by GRA_0 compare match are performed by TRDCNT counters. For details on PWM mode, see section 16.3.5, PWM Mode. TRDCNT values GRA_0 GRA_1 GRB_0 GRB_1 H'0000 Time Synchronous clearing by GRA_0 compare match FTIOB0 FTIOB1 Figure 16.20 Example of Synchronous Operation 16.3.5 PWM Mode In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD output pins with GRA as a cycle register and GRB, GRC, and GRD as duty registers. The initial output level of the corresponding pin depends on the setting values of TRDOCR and POCR. Table 16.4 shows an example of the initial output level of the FTIOB0 pin. The output level is determined by the POLB to POLD bits corresponding to POCR. When POLB is 0, the FTIOB output pin is set to 0 by compare match B and set to 1 by compare match A. When POLB is 1, the FTIOB output pin is set to 1 by compare match B and cleared to 0 by compare match A. In PWM mode, maximum 6-phase PWM outputs are possible. Rev. 1.00 Oct. 03, 2008 Page 551 of 962 REJ09B0465-0100 Section 16 Timer RD Figure 16.21 shows an example of the PWM mode setting procedure. Table 16.4 Initial Output Level of FTIOB0 Pin TOB0 0 0 1 1 POLB 0 1 0 1 Initial Output Level 1 0 0 1 PWM mode [1] Select counter clock [1] Select the counter clock with bits TPSC2 to TOSC0 in TRDCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TRDCR. Use bits CCLR2 to CCLR0 in TRDCR to select the counter clearing source. Select the PWM mode with bits PWMB0 to PWMD0 and PWMB1 to PWMD1 in TRDPMR. Set the initial output value with bits TOB0 to TOD0 and TOB1 to TOD1 in TRDOCR. Set the output level with bits POLB to POLD in POCR. Set the cycle in GRA, and set the duty in the other GR. Enable or disable the timer output by TRDOER1. Set the STR bit in TRDSTR to 1 and start the counter operation. Select counter clearing source [2] [2] Set PWM mode [3] [3] Set initial output level [4] [4] Select output level [5] [5] Set GR [6] [6] Enable waveform output [7] [7] Start counter operation [8] [8] Figure 16.21 Example of PWM Mode Setting Procedure Rev. 1.00 Oct. 03, 2008 Page 552 of 962 REJ09B0465-0100 Section 16 Timer RD Figure 16.22 shows an example of operation in PWM mode. The output signals go to 1 and TRDCNT is reset at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0). TRDCNT value GRA GRB GRC GRD H'0000 Time Counter cleared by GRA compare match FTIOB FTIOC FTIOD Figure 16.22 Example of PWM Mode Operation (1) Rev. 1.00 Oct. 03, 2008 Page 553 of 962 REJ09B0465-0100 Section 16 Timer RD Figure 16.23 shows another example of operation in PWM mode. The output signals go to 0 and TRDCNT is reset at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1). TRDCNT value GRA GRB GRC GRD H'0000 Time Counter cleared by GRA compare match FTIOB FTIOC FTIOD Figure 16.23 Example of PWM Mode Operation (2) Rev. 1.00 Oct. 03, 2008 Page 554 of 962 REJ09B0465-0100 Section 16 Timer RD Figures 16.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 16.25 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1) show examples of the output of PWM waveforms with duty cycles of 0% and 100% in PWM mode. TRDCNT value GRA GRB rewritten GRB GRB rewritten H'0000 FTIOB 0% duty Time TRDCNT value GRB rewritten GRA When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRB rewritten GRB rewritten GRB H'0000 FTIOB 100% duty Time When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. TRDCNT value GRB rewritten GRA GRB rewritten GRB rewritten GRB H'0000 FTIOB 100% duty 0% duty Time Figure 16.24 Example of PWM Mode Operation (3) Rev. 1.00 Oct. 03, 2008 Page 555 of 962 REJ09B0465-0100 Section 16 Timer RD TRDCNT value GRB rewritten GRA GRB rewritten GRB H'0000 FTIOB 0% duty Time TRDCNT value GRB rewritten GRA When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRB rewritten GRB rewritten GRB H'0000 FTIOB 100% duty Time TRDCNT value GRB rewritten GRA When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRB rewritten GRB rewritten GRB H'0000 FTIOB 100% duty 0% duty Time Figure 16.25 Example of PWM Mode Operation (4) Rev. 1.00 Oct. 03, 2008 Page 556 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.6 Reset Synchronous PWM Mode Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TRDCNT_0 performs an increment operation. Tables 16.5 and 16.6 show the PWM-output pins used and the register settings, respectively. Figure 16.29 shows the example of reset synchronous PWM mode setting procedure. Table 16.5 Output Pins in Reset Synchronous PWM Mode Channel 0 0 0 1 1 1 1 Pin Name FTIOC0 FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 Input/Output Output Output Output Output Output Output Output Pin Function Toggle output in synchronous with PWM cycle PWM output 1 PWM output 1 (counter-phase waveform of PWM output 1) PWM output 2 PWM output 2 (counter-phase waveform of PWM output 2) PWM output 3 PWM output 3 (counter-phase waveform of PWM output 3) Table 16.6 Register Settings in Reset Synchronous PWM Mode Register TRDCNT_0 TRDCNT_1 GRA_0 GRB_0 GRA_1 GRB_1 Description Initial setting of H'0000 Not used (independently operates) Sets counter cycle of TRDCNT_0 Set a changing point of the PWM waveform output from pins FTIOB0 and FTIOD0. Set a changing point of the PWM waveform output from pins FTIOA1 and FTIOC1. Set a changing point of the PWM waveform output from pins FTIOB1 and FTIOD1. Rev. 1.00 Oct. 03, 2008 Page 557 of 962 REJ09B0465-0100 Section 16 Timer RD Reset synchronous PWM mode [1] Clear bit STR0 in TRDSTR to 0 and stop the counter operation of TRDCNT_0. Set reset synchronous PWM mode after TRDCNT_0 stops. [1] [2] Select the counter clock with bits TPSC2 to TPSC0 in TRDCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TRDCR. [3] Use bits CCLR2 to CCLR0 in TRDCR to select counter clearing source GRA_0. [4] Select the reset synchronous PWM mode with bits CMD1 and CMD0 in TRDFCR. FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 become PWM output pins automatically. [5] Set TRDCNT_0 as H'0000. TRDCNT_1 does not need to be set. [6] [6] GRA_0 is a cycle register. Set a cycle for GRA_0. Set the changing point timing of the PWM output waveform for GRB_0, GRA_1, and GRB_1. [7] Enable or disable the timer output by TRDOER1. [8] Set the STR bit in TRDSTR to 1 and start the counter operation. Stop counter operation Select counter clock [2] Select counter clearing source [3] Set reset synchronous PWM mode [4] Set TRDCNT [5] Set GR Enable waveform output [7] Start counter operation [8] Figure 16.26 Example of Reset Synchronous PWM Mode Setting Procedure Rev. 1.00 Oct. 03, 2008 Page 558 of 962 REJ09B0465-0100 Section 16 Timer RD Figures 16.27 and 16.28 show examples of operation in reset synchronous PWM mode. Counter cleared by GRA compare match TRDCNT value GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 16.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) Rev. 1.00 Oct. 03, 2008 Page 559 of 962 REJ09B0465-0100 Section 16 Timer RD TRDCNT value Counter cleared by GRA compare match GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 16.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) In reset synchronous PWM mode, TRDCNT_0 and TRDCNT_1 perform increment and independent operations, respectively. However, GRA_1 and GRB_1 are separated from TRDCNT_1. When a compare match occurs between TRDCNT_0 and GRA_0, a counter is cleared and an increment operation is restarted from H'0000. The PWM pin outputs 0 or 1 whenever a compare match between GRB_0, GRA_1, GRB_1 and TRDCNT_0 or counter clearing occur. For details on operations when reset synchronous PWM mode and buffer operation are simultaneously set, see section 16.3.9, Buffer Operation. Rev. 1.00 Oct. 03, 2008 Page 560 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.7 Complementary PWM Mode Three PWM waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TRDCNT_0 and TRDCNT_1 perform an increment or decrement operation. Tables 16.7 and 16.8 show the output pins and register settings in complementary PWM mode, respectively. Figure 16.29 shows the example of complementary PWM mode setting procedure. Table 16.7 Output Pins in Complementary PWM Mode Channel 0 0 0 1 1 1 1 Pin Name FTIOC0 FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 Input/Output Output Output Output Output Output Output Output Pin Function Toggle output in synchronous with PWM cycle PWM output 1 PWM output 1 (counter-phase waveform nonoverlapped with PWM output 1) PWM output 2 PWM output 2 (counter-phase waveform nonoverlapped with PWM output 2) PWM output 3 PWM output 3 (counter-phase waveform nonoverlapped with PWM output 3) Table 16.8 Register Settings in Complementary PWM Mode Register TRDCNT_0 TRDCNT_1 GRA_0 GRB_0 GRA_1 GRB_1 Description Initial setting of non-overlapped periods (non-overlapped periods are differences with TRDCNT_1) Initial setting of H'0000 Sets (upper limit value - 1) of TRDCNT_0 Set a changing point of the PWM waveform output from pins FTIOB0 and FTIOD0. Set a changing point of the PWM waveform output from pins FTIOA1 and FTIOC1. Set a changing point of the PWM waveform output from pins FTIOB1 and FTIOD1. Rev. 1.00 Oct. 03, 2008 Page 561 of 962 REJ09B0465-0100 Section 16 Timer RD Complementary PWM mode [1] Stop counter operation [1] [2] Select counter clock Set complementary PWM mode Set TCNT [2] [3] [4] [3] Set GR [5] [4] Enable waveform output [6] [5] Start counter operation [7] Clear bits STR0 and STR1 in TRDSTR to 0, and stop the counter operation of TRDCNT_0. Stop TRDCNT_0 and TRDCNT_1 and set complementary PWM mode. Use bits TPSC2 to TPSC0 in TRDCR to select the same counter clock for channels 0 and 1. When an external clock is selected, select the edge of the external clock by bits CKEG1 and CKEG0 in TRDCR. Set bits CCLR2 to CCLR0 in TRDCR so that the counter is not cleared. Use bits CMD1 and CMD0 in TRDFCR to set complementary PWM mode. FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 automatically become PWM output pins. TRDCNT_1 must be H'0000. Set a nonoverlapped period to TRDCNT_0. GRA_0 is a cycle register. Set the cycle to GRA_0. Set the timing to change the PWM output waveform to GRB_0, GRA_1, and GRB_1. The settings must be set so that a compare match occurs on TRDCNT_0 and TRDCNT_1. T X (X: Initial value in GRB_0, GRA_1, or GRB_1). Use TRDOER1 to enable or disable the timer output. Set the STR0 and STR1 bits in TRDSTR to 1 to start the count operation. Note: To modify the settings for the complementary PWM mode, clear settings other than those for the mode. After that, repeat setting from step [1]. Figure 16.29 Example of Complementary PWM Mode Setting Procedure (1) Canceling Procedure of Complementary PWM Mode Figure 16.30 shows the complementary PWM mode canceling procedure. Complementary PWM mode [1] Stop counter operation [1] [2] Clear bit CMD1 in TRDFCR to 0, and set channels 0 and 1 to normal operation. After setting channels 0 and 1 to normal operation, clear bits STR0 and STR1 in TRDSTR to 0 and stop TRDCNT_0 and TRDCNT_1. Cancel complementary PWM mode [2] Figure 16.30 Canceling Procedure of Complementary PWM Mode Rev. 1.00 Oct. 03, 2008 Page 562 of 962 REJ09B0465-0100 Section 16 Timer RD (2) Examples of Complementary PWM Mode Operation Figure 16.31 shows an example of complementary PWM mode operation. In complementary PWM mode, TRDCNT_0 and TRDCNT_1 perform an increment or decrement operation. When TRDCNT_0 and GRA_0 are compared and their contents match, the counter is decremented. And when TRDCNT_1 underflows, the counter is incremented. In GRA_0, GRA_1, and GRB_1, compare match is carried out in the order of TRDCNT_0 TRDCNT_1 TRDCNT_1 TRDCNT_0 and PWM waveform is output, during one cycle of an up/down counter. In this mode, the initial setting will be TRDCNT_0 > TRDCNT_1. TRDCNT values GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time TRDCNT_0 and GRA_0 are compared and their contents match FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 16.31 Example of Complementary PWM Mode Operation (1) Rev. 1.00 Oct. 03, 2008 Page 563 of 962 REJ09B0465-0100 Section 16 Timer RD Figure 16.32 shows an example of PWM waveform output with 0% duty and 100% duty in complementary PWM mode (for one phase). In this figure, GRB_0 is set to a value equal to or greater than GRA_0 and H'0000. The waveform with a duty cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation. For details on buffer operation, see section 16.3.9, Buffer Operation. TRDCNT values GRA_0 GRB_0 H'0000 Time FTIOB0 FTIOD0 0% duty (a) When duty is 0% TRDCNT values GRA_0 GRB_0 H'0000 FTIOB0 Time FTIOD0 100% duty (b) When duty is 100% Figure 16.32 Example of Complementary PWM Mode Operation (2) Rev. 1.00 Oct. 03, 2008 Page 564 of 962 REJ09B0465-0100 Section 16 Timer RD In complementary PWM mode, when the counter switches from up-counter to down-counter or vice versa, TRDCNT_0 and TRDCNT_1 overshoots or undershoots, respectively. In this case, the conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings are shown in figures 16.33 and 16.34. TRDCNT N-1 N N+1 N N-1 GRA_0 N IMFA Set to 1. Flag is not set. Buffer transfer signal GR Transferred to buffer Not transferred to buffer Figure 16.33 Timing of Overshooting TRDCNT H'0001 H'0000 H'FFFF H'0000 H'0001 UDF Set to 1. OVF Buffer transfer signal Flag is not set. GR Transferred to buffer Not transferred to buffer Figure 16.34 Timing of Undershooting Rev. 1.00 Oct. 03, 2008 Page 565 of 962 REJ09B0465-0100 Section 16 Timer RD When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been designated for GR, the value in the buffer registers is transferred to GR when the counter is incremented by compare match A0 or when TRDCNT_1 is underflowed. In complementary PWM mode, the OVF flag is not set to 1 at the timing that the counter value changes from H'FFFF to H'0000 as shown in figure 16.34. (3) Setting GR Value in Complementary PWM Mode To set the general register (GR) or modify GR during operation in complementary PWM mode, see the following notes. 1. Initial value H'0000 to T - 1 (T: Initial value of TRDCNT_0) must not be set for the initial value. GRA_0 - (T - 1) or more must not be set for the initial value. When using buffer operation, the same values must be set in the buffer registers and corresponding general registers. 2. Modifying the setting value Use the buffer operation to change the GR value. If the GR value is changed by writing to it directly, the intended waveform may not be output. Do not change settings of GRA_0 during operation. Rev. 1.00 Oct. 03, 2008 Page 566 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.8 PWM3 Mode Operation In PWM3 mode, single-phase PWM waveforms can be output using TRDCNT_0. The waveform does not overlap its counter-phase waveform. When the PWM3 mode is selected, the FTIOA0 and FTIOB0 pins are automatically set to output pins for the PWM function using TRDCNT_0 regardless of the TRDPMR value. The waveform is output on a GRA_0, GRA_1, GRB_0, or GRB_1 compare match according to bits TOA0 and TOB0 in TRDOCR regardless of the TRDIORA and TRDIORC settings. * When TOA0 = 0, 1 is output on a compare match of GRA_1 and 0 is output on a compare match of GRA_0 on the FTIOA0 pin. * When TOA0 = 1, 0 is output on a compare match of GRA_1 and 1 is output on a compare match of GRA_0 on the FTIOA0 pin. * When TOB0 = 0, 1 is output on a compare match of GRB_1 and 0 is output on a compare match of GRB_0 on the FTIOB0 pin. * When TOB0 = 1, 0 is output on a compare match of GRB_1 and 1 is output on a compare match of GRB_0 on the FTIOB0 pin. Table 16.9 lists the correspondence between pin functions and GR registers, figure 16.35 shows a block diagram in PWM3 mode, and figure 16.36 shows a flowchart of setting in PWM3 mode. When the buffer operation is used, set TRDMDR. The timer input/output pins, which are not used in PWM3 mode, can be used as general port pins. When the buffer operation is not set, since GRC or GRD is not used, a compare match interrupt can be generated when GRC or GRD matches with TRDCNT_1. Rev. 1.00 Oct. 03, 2008 Page 567 of 962 REJ09B0465-0100 Section 16 Timer RD Table 16.9 Pin Configuration in PWM3 Mode and GR Registers Channel 0 Pin Name FTIOA0 Input/Output Output Compare Match Register GRA_0 GRA_1 FTIOB0 GRB_0 GRB_1 FTIOC0 FTIOD0 1 FTIOA1 FTIOB1 FTIOC1 FTIOD1 I/O General I/O port Buffer Register GRC_0 GRC_1 GRD_0 GRD_1 General I/O port Compare match signal TRDCNT_0 FTIOA0 Output control Compare match signal Comparator Compare match signal Comparator FTIOB0 Output control Compare match signal Comparator GRB_1 GRD_1 GRB_0 GRD_0 GRA_1 GRC_1 Comparator GRA_0 GRC_0 Figure 16.35 Block Diagram in PWM3 Mode Rev. 1.00 Oct. 03, 2008 Page 568 of 962 REJ09B0465-0100 Section 16 Timer RD PWM mode 3 [1] Select the counter clock with bits TPSC2 to TPSC0 in TRDCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TRDCR. [2] Use bits CCLR2 to CCLR0 in TRDCR to select counter clearing source GRA_0. [3] Select PWM mode 3 with bit PWM3 in TRDFCR. Set output level [4] [4] Set output levels with bits TOB0 and TOA0 in TRDOCR. Select buffer operation [5] [5] Set the GR buffer operation with bits BFC0, BFC1, BFD0, and BFD1 in TRDMDR. [6] Set a cycle in GRA. Set the duty cycle in other GR registers. [7] Enable or disable the timer output by TRDOER. [8] Set the STR bit in TRDSTR to 1 and start the counter operation. Select counter clock [1] Select counter clearing source [2] Set PWM mode 3 [3] Set GR [6] Enable waveform output [7] Start counter operation [8] Figure 16.36 Flowchart of Setting in PWM3 Mode Rev. 1.00 Oct. 03, 2008 Page 569 of 962 REJ09B0465-0100 Section 16 Timer RD Figure 16.37 is an example when non-overlapped pulses are output on pins FTIOA0 and FTIOB0. In this example, TRDCNT_0 functions as a periodic counter which is cleared on compare match A0 (bits CCLR2 to CCLR0 in TRDCR_0 are set to B'001), and PWM3 mode is selected (bit PWM3 in TRDFCR is cleared to 0). The cycle of the pulse is arbitrary. Counter cleared on GRA_0 compare match TRDCNT value H'FFFF GRA_0 GRA_1 GRB_0 GRB_1 H'0000 Time FTIOA0 FTIOB0 Figure 16.37 Example of Non-Overlap Pulses Rev. 1.00 Oct. 03, 2008 Page 570 of 962 REJ09B0465-0100 Section 16 Timer RD Figures 16.38 and 16.39 show examples of stopping operation of the counter in PWM3 mode, when the CCLR2 to CCLR0 bits in TRDCR are set to clear TRDCNT_0 on GRA_0 compare match. For details on PWM3 mode, see section 16.3.8, PWM3 Mode Operation. Counter cleared by GRA_0 compare match The value of TRDCNT H'FFFF GRA_0 GRA_1 GRB_0 GRB_1 H'0000 FTIOA0 Time FTIOB0 STR0 CSTPN0 Set to 1 by writing from the CPU Cleared to 0 by GRA_0 compare match Figure 16.38 Example (1) of Stopping Operation of the Counter (in PWM3 Mode) The value of TRDCNT H'FFFF GRA_0 GRA_1 GRB_0 GRB_1 H'0000 FTIOA0 Counter cleared by GRA_0 compare match Time FTIOB0 STR0 High CSTPN0 Set to 1 by writing from the CPU Cleared to 0 by writing from the CPU Figure 16.39 Example (2) of Stopping Operation of the Counter (in PWM3 Mode) Rev. 1.00 Oct. 03, 2008 Page 571 of 962 REJ09B0465-0100 Section 16 Timer RD Figure 16.40 shows an example of starting and stopping operations of counters in PWM3 mode, when TRDCNT_0 is set to be cleared and stopped on GRA_0 compare match (CCLR2 to CCLR0 = 001, CSTPNT0 = 0) and TRDCNT_1 is used as a free-running counter. When TRDCNT_1 starts counting by setting the STR1 bit to 1 after TRDCNT_0 has started counting by setting the STR0 bit to 1, set 0 in the STR0 bit and 1 in the STR1 bit by using a MOV instruction. If the bit manipulation instruction is used to set 1 in the STR1 bit, there is a possibility that the STR0 bit is set to 1 after the counting has stopped on GRA_0 compare match, and that TRDCNT_0 starts counting again. Counter cleared by GRA_0 compare match The value of TRDCNT H'FFFF GRA_0 GRA_1 GRB_0 GRB_1 H'0000 FTIOA0 Time TRDCNT_0 TRDCNT_1 FTIOB0 STR0 0 written in STR0 by the CPU is not reflected CSTPN0 Low STR1 High CSTPN1 0 is written in STR0, 1 in STR1, 0 in CSTPN0, and 1 in CSTPN1 by the CPU Figure 16.40 Example of Starting and Stopping Operations of Counters (in PWM3 Mode) Rev. 1.00 Oct. 03, 2008 Page 572 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.9 Buffer Operation Buffer operation differs depending on whether GR has been designated for an input capture register or an output compare register, or in reset synchronous PWM mode or complementary PWM mode. Table 16.10 shows the register combinations used in buffer operation. Table 16.10 Register Combinations in Buffer Operation General Register (GR) GRA GRB Buffer Register GRC GRD (1) When GR is an Output Compare Register When a compare match occurs, the value in the buffer register of the corresponding channel is transferred to the general register. This operation is illustrated in figure 16.41. Compare match signal Buffer register General register Comparator TRDCNT Figure 16.41 Compare Match Buffer Operation Rev. 1.00 Oct. 03, 2008 Page 573 of 962 REJ09B0465-0100 Section 16 Timer RD (2) When GR is an Input Capture Register When an input capture occurs, the value in TRDCNT is transferred to GR and the value previously stored in the general register is transferred to the buffer register. This operation is illustrated in figure 16.42. Input capture signal Buffer register General register TRDCNT Figure 16.42 Input Capture Buffer Operation (3) PWM3 Mode When compare match A0 occurs, the value of the buffer register is transferred to GR. (4) Complementary PWM Mode When the counter switches from counting up to counting down or vice versa, the value of the buffer register is transferred to GR. Here, the value of the buffer register is transferred to GR in the following timing: * When TRDCNT_0 and GRA_0 are compared and their contents match * When TRDCNT_1 underflows (5) Reset Synchronous PWM Mode When compare match A0 occurs, the value in the buffer register is transferred to GR. Rev. 1.00 Oct. 03, 2008 Page 574 of 962 REJ09B0465-0100 Section 16 Timer RD (6) Example of Buffer Operation Setting Procedure Figure 16.43 shows an example of the buffer operation setting procedure. Buffer operation [1] Designate GR as an input capture register or output compare register by means of TRDIOR. Designate GR for buffer operation with bits BFD1, BFC1, BFD0, or BFC0 in TRDMDR. Set the STR bit in TRDSTR to 1 to start the count operation of TRDCNT. Select GR function [1] [2] Set buffer operation [2] [3] Start count operation [3] Figure 16.43 Example of Buffer Operation Setting Procedure (7) Examples of Buffer Operation Figure 16.44 shows an operation example in which GRA has been designated as an output compare register, and buffer operation has been designated for GRA and GRC. This is an example of TRDCNT operating as a periodic counter cleared by compare match B. Pins FTIOA and FTIOB are set for toggle output by compare match A and B. As buffer operation has been set, when compare match A occurs, the FTIOA pin performs toggle outputs and the value in buffer register is simultaneously transferred to the general register. This operation is repeated each time that compare match A occurs. Rev. 1.00 Oct. 03, 2008 Page 575 of 962 REJ09B0465-0100 Section 16 Timer RD The timing to transfer data is shown in figure 16.45. Counter is cleared by GRB compare match TRDCNT value GRB H'0250 H'0200 H'0100 H'0000 Time GRC H'0200 H'0100 H'0200 GRA H'0250 H'0200 H'0100 H'0200 FTIOB FTIOA Compare match A Figure 16.44 Example of Buffer Operation (1) (Buffer Operation for Output Compare Register) Rev. 1.00 Oct. 03, 2008 Page 576 of 962 REJ09B0465-0100 Section 16 Timer RD TRDCNT Compare match signal Buffer transfer signal GRC n n+1 N GRA n N Figure 16.45 Example of Compare Match Timing for Buffer Operation Figure 16.46 shows an operation example in which GRA has been designated as an input capture register, and buffer operation has been designated for GRA and GRC. Counter clearing by input capture B has been set for TRDCNT, and falling edges have been selected as the FIOCB pin input capture input edge. And both rising and falling edges have been selected as the FIOCA pin input capture input edge. As buffer operation has been set, when the TRDCNT value is stored in GRA upon the occurrence of input capture A, the value previously stored in GRA is simultaneously transferred to GRC. The transfer timing is shown in figure 16.47. Rev. 1.00 Oct. 03, 2008 Page 577 of 962 REJ09B0465-0100 Section 16 Timer RD TRDCNT value H'0180 H'0160 Counter is cleared by the input capture B H'0005 H'0000 Time FTIOB FTIOA GRA H'0005 H'0160 GRC H'0005 H'0160 GRB H'0180 Input capture A Figure 16.46 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register) FTIO pin Input capture signal TRDCNT n n+1 N N+1 GRA M n n N GRC m M M n Figure 16.47 Input Capture Timing of Buffer Operation Rev. 1.00 Oct. 03, 2008 Page 578 of 962 REJ09B0465-0100 Section 16 Timer RD Figures 16.48 and 16.49 show the operation examples when buffer operation has been designated for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM waveform of 0% duty is created by using the buffer operation and performing GRD_0 GRA_0. Data is transferred from GRD_0 to GRB_0 according to the settings of CMD0 and CMD1 when TRDCNT_0 and GRA_0 are compared and their contents match or when TRDCNT_1 underflows. However, when GRD_0 GRA_0, data is transferred from GRD_0 to GRB_0 when TRDCNT_1 underflows regardless of the setting of CMD0 and CMD1. When GRD_0 = H'0000, data is transferred from GRD_0 to GRB_0 when TRDCNT_0 and GRA_0 are compared and their contents match regardless of the settings of CMD0 and CMD1. GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values) TRDCNT values TRDCNT_0 GRA_0 TRDCNT_1 H'0999 H'0000 GRD_0 H'0999 GRB_0 H'0999 H'1FFF H'0999 Time H'0999 H'1FFF H'0999 FTIOB0 FTIOD0 Figure 16.48 Buffer Operation (3) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) Rev. 1.00 Oct. 03, 2008 Page 579 of 962 REJ09B0465-0100 Section 16 Timer RD TRDCNT values TRDCNT_0 GRA_0 TRDCNT_1 H'0999 GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values) H'0000 GRB_0 GRD_0 H'0999 H'0000 H'0999 Time GRB_0 H'0999 H'0000 H'0999 FTIOC0 FTIOD0 Figure 16.49 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 =1, CMD0 = 0) Rev. 1.00 Oct. 03, 2008 Page 580 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.10 Timer RD Output Timing The outputs of channels 0 and 1 can be disabled or inverted by the settings of TRDOER1 and TRDOCR and the external level. (1) Output Disable/Enable Timing of Timer RD by TRDOER1 Setting the master enable bit in TRDOER1 to 1 disables the output of timer RD. By setting the PCR and PDR of the corresponding I/O port beforehand, any value can be output. Figure 16.50 shows the timing to enable or disable the output of timer RD by TRDOER1. T1 T2 Address bus TRDOER1 address TRDOER1 0 1 Timer RD output pin Timer output I/O port Timer RD output I/O port Figure 16.50 Example of Output Disable Timing of Timer RD by Writing to TRDOER1 Rev. 1.00 Oct. 03, 2008 Page 581 of 962 REJ09B0465-0100 Section 16 Timer RD (2) Output Disable Timing of Timer RD by External Trigger When PH5/TRDOI_0 (or PH6/TRDOI_1) is set as a TRDOI input pin, and low level is input to TRDOI, the master enable bit in TRDOER1 is set to 1 and the output of timer RD will be disabled. TRDOI 0 1 TRDOER1 Timer RD output pin Timer RD output Timer RD output I/O port I/O port Figure 16.51 Example of Output Disable Timing of Timer RD by External Trigger (3) Output Inverse Timing by TRDFCR The output level can be inverted by inverting the OLS1 and OLS0 bits in TRDFCR in reset synchronous PWM mode or complementary PWM mode. Figure 16.52 shows the timing. T1 T2 Address bus TRDFCR address TRDFCR Timer RD output pin Inverted Figure 16.52 Example of Output Inverse Timing of Timer RD by Writing to TRDFCR Rev. 1.00 Oct. 03, 2008 Page 582 of 962 REJ09B0465-0100 Section 16 Timer RD (4) Output Inverse Timing by POCR The output level can be inverted by inverting the POLD, POLC, and POLB bits in POCR in PWM mode. Figure 16.53 shows the timing. T1 T2 Address bus POCR address POCR Timer RD output pin Inverted Figure 16.53 Example of Output Inverse Timing of Timer RD by Writing to POCR Rev. 1.00 Oct. 03, 2008 Page 583 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.11 Digital Filtering Function for Input Capture Inputs Input signals on the FTIOA to FTIOD pins can be input via the digital filters. The digital filter includes three latches connected in series and a match detector circuit. The latches operate on the sampling clock specified by bits DFCK1 and DFCK0 in TRDDF and stores an input signal on the FTIOA to FTIOD pins. When outputs of the three latches match, the match detector circuit outputs the signal level of the input. Otherwise, the output remains unchanged. That is, when a pulse width is equal to or greater than three sampling clock cycles, the pulse is input as a signal. When a pulse width is less than three sampling clock cycles, the pulse is considered as a noise to be removed. TPSC2 to TPSC0 DFCK1 and DFCK2 FTIOA0 (TCLK) 40 /32 /8 /4 /2 /32 /8 Sampling clock DFA to DFD IOA1, IOA0, IOD1, and IOD0 C FTIOA to FTIOD D Latch , 40M C D Latch Q Q D C Q Latch D C Q Latch D C Q Latch Match detector circuit Selecter Edge detecting circuit Cycle of a clock specified by TPSC2 to TPSC0 or DFCK1 and DFCK0 Sampling clock FTIOA to FTIOD input signals Digital-filtered signal Signal propagation delay: 5 sampling clocks Signal change is not output unless signal levels match three times. Figure 16.54 Block Diagram of Digital Filter Rev. 1.00 Oct. 03, 2008 Page 584 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.12 Function of Changing Output Pins for GR With the settings of bits IOC3 and IOD3 in TRDIORC, pins for outputs of compare match signals for GRC and GRD can be changed from the FTIOC and FTIOD pins to the FTIOA and FTIOB pins. This means that the compare match A signal ORed with the compare match C signal can be output on the FTIOA pin. The compare match B ORed with the compare match D signal can be output on the FTIOB pin. Figure 16.55 is a block diagram of this function. The setting for channel 0 is independent of that for channel 1. Channel 0 Compare match signal FTIOA0 Output control Compare match signal FTIOC0 Output control Compare match signal FTIOB0 Output control Compare match signal FTIOD0 Output control Comparator GRB_0 Comparator TRDCNT_0 GRA_0 Comparator GRC_0 Comparator GRD_0 Channel 1 Compare match signal FTIOA1 Output control Compare match signal FTIOC1 Output control Compare match signal FTIOB1 Output control Compare match signal FTIOD1 Output control Comparator GRB_1 Comparator TRDCNT_1 GRA_1 Comparator GRC_1 Comparator GRD_1 Figure 16.55 Block Diagram of Output Pins for GR Rev. 1.00 Oct. 03, 2008 Page 585 of 962 REJ09B0465-0100 Section 16 Timer RD Figure 16.56 is an example when non-overlapped pulses are output on pins FTIOA0 and FTIOB0. In this example, TRDCNT_0 functions as a periodic counter which is cleared on compare match A0 (bits CCLR2 to CCLR0 in TRDCR_0 are set to B'001), an output signal is toggled on compare match A (bits IOA2 to IOA0 in TRDIORA_1 are set to B'011), the output signal on the FTIOA pin is toggled on compare match C (GRC_0) (bits IOC3 to IOC0 in TRDIORC_1 are set to B'0X11), an output signal is toggled on compare match B (GRB_0) (bits IOB2 to IOB0 in TRDIORA_1 are set to B'011), and the output signal on the FTIOB pin is toggled on compare match D (GRD_0) (bits IOD3 to IOD0 in TRDIORC_1 are set to B'0X11). The cycle of the pulse is arbitrary. Similarly, figure 16.57 is an example when non-overlapped pulses are output using TRDCNT_1. TRDCNT value H'FFFF GRA_0 GRC_0 GRB_0 GRD_0 H'0000 FTIOA0 Counter cleared on GRA_0 compare match Time FTIOB0 Figure 16.56 Example of Non-Overlapped Pulses Output on Pins FTIOA0 and FTIOB0 (TRDCNT_0 Used) TRDCNT value H'FFFF GRA_1 GRC_1 GRB_1 GRD_1 H'0000 FTIOA1 FTIOB1 Counter cleared on GRA_1 compare match Time Figure 16.57 Example of Non-Overlapped Pulses Output on Pins FTIOA1 and FTIOB1 (TRDCNT_1 Used) Rev. 1.00 Oct. 03, 2008 Page 586 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.13 A/D Conversion Start Trigger Setting Function Timer RD can generate the A/D conversion start trigger signal by setting the timer RD A/D conversion start trigger control register (TRDADCR) or bits ADEG and ADTRG in the timer RD function control register (TRDFCR). Figures 16.58 and 16.59 show examples of the A/D conversion trigger signal generation in complementary PWM mode. GRA GRB GRC GRD H'0000 ADTRG Figure 16.58 Example of A/D Conversion Trigger Signal Generation in Complementary PWM Mode (Trigger Asserted When TRDCNT_0 Matches GRA_0: ADEG = 0, ADTRG = 1) GRA GRB GRC GRD H'0000 ADTRG Figure 16.59 Example of A/D Conversion Trigger Signal Generation in Complementary PWM Mode (Trigger Asserted When TRDCNT_1 Underflows: ADEG = 1, ADTRG = 1) Rev. 1.00 Oct. 03, 2008 Page 587 of 962 REJ09B0465-0100 Section 16 Timer RD Figure 16.60 shows an example where the A/D conversion start trigger signal is generated by compare match. In this case, the TRDADCR register must be set. GRA GRB GRC H'0000 Setting of A/D conversion start trigger ADTRG Figure 16.60 Example of A/D Conversion Trigger Signal Generation by Compare Match Figure 16.61 shows the timing for generating the A/D conversion start trigger by compare match. CK TRDCNT input TRDCNT N N+1 GRX N Compare match signal A/D conversion start trigger signal Figure 16.61 Timing of A/D Conversion Start Trigger Generation Rev. 1.00 Oct. 03, 2008 Page 588 of 962 REJ09B0465-0100 Section 16 Timer RD 16.3.14 Operation by Event Clear Using the event link controller (ELC), timer RD unit 0 can be made to operate in the following ways in relation to events occurring in other modules. Each channel 0 and 1 can be specified independently. (1) Staring Counter Operation The start of counting operations by timer RD can be selected by ELOPA and ELOPB of the ELC. When the event specified by ELSR3 and ELSR4 occur, the STR[1:0] bits in TRDSTR are set to 1, which stars counting by timer RD. However, if the specified event occurs when the STR bit has already been set to 1, the event is not effective. (2) Counting Event The counting of events by timer RD can be selected by ELOPA and ELOPB of the ELC. When the event specified in ELSR3 and ELSR4 occurs, event counter operation proceeds with that event as the source to drive counting, regardless of the setting of the TPSC[2:0] bits in TRDCR1. When the value of the counter is read, the value read out is the actual number of input events. (3) Input Capture Input capture operation of timer RD can be selected by ELOPA and ELOPB of the ELC. When the event specified in ELSR3 and ELSR4 occurs, GRD captures the value of TRDCNT. When input capture operation initiated by an event link is in use, set the IOD[3:0] bits = b'1101 in TRDIORC of timer RD, set the STR bit in TRDSTR to 1, and then start the counter. Since input on the FTIOD pin becomes valid at the same time, fix the input to the FTIOD pin or take other measures such as not allocating the FTIOD pin to the port in the PMC, etc. Rev. 1.00 Oct. 03, 2008 Page 589 of 962 REJ09B0465-0100 Section 16 Timer RD 16.4 Interrupt Sources There are three kinds of timer RD interrupt sources; input capture/compare match, overflow, and underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while the corresponding interrupt enable bit is set to 1. 16.4.1 (1) Status Flag Set Timing IMF Flag Set Timing The IMF flag is set to 1 by the compare match signal that is generated when the GR matches with the TRDCNT. The compare match signal is generated at the last state of matching (timing to update the counter value when the GR and TRDCNT match). Therefore, when the TRDCNT and GR matches, the compare match signal will not be generated until the TRDCNT input clock is generated. Figure 16.62 shows the timing to set the IMF flag. TRDCNT input clock TRDCNT N N+1 GR N Compare match signal IMF Figure 16.62 IMF Flag Set Timing when Compare Match Occurs Rev. 1.00 Oct. 03, 2008 Page 590 of 962 REJ09B0465-0100 Section 16 Timer RD (2) IMF Flag Set Timing at Input Capture When an input capture signal is generated, the IMF flag is set to 1 and the value of TRDCNT is simultaneously transferred to corresponding GR. Figure 16.63 shows the timing. Input capture signal IMF TRDCNT N GR N Figure 16.63 IMF Flag Set Timing at Input Capture (3) Overflow Flag (OVF) Set Timing The overflow flag is set to 1 when the TRDCNT overflows. Figure 16.64 shows the timing. TRDCNT H'FFFF H'0000 Overflow signal OVF Figure 16.64 OVF Flag Set Timing Rev. 1.00 Oct. 03, 2008 Page 591 of 962 REJ09B0465-0100 Section 16 Timer RD 16.4.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 16.65 shows the timing in this case. Address WTRDSR (internal write signal) TRDSR address IMF, OVF Figure 16.65 Status Flag Clearing Timing 16.5 (1) Usage Notes Input Pulse Width of Input Clock Signal and Input Capture Signal When the digital filtering function for input is not in use, the pulse width of the input clock signal and the input capture signal must be at least three system clock () cycles when the TPSC2 to TPSC0 bits in TRDCR = B'0XX or B'10X, and at least 3 x 40 cycles for B'110; shorter pulses will not be detected correctly. Rev. 1.00 Oct. 03, 2008 Page 592 of 962 REJ09B0465-0100 Section 16 Timer RD (2) Conflict between TRDCNT Write and Clear Operations If a counter clear signal is generated in the T2 state of a TRDCNT write cycle, TRDCNT clearing has priority and the TRDCNT write is not performed. Figure 16.66 shows the timing in this case. TRDCNT write cycle T1 T2 TRDCNT address WTRDCNT (internal write signal) Counter clear signal TRDCNT N H'0000 Clearing has priority. Figure 16.66 Conflict between TRDCNT Write and Clear Operations (3) Conflict between TRDCNT Write and Increment Operations If TRDCNT is incremented in the T2 state of a TRDCNT write cycle, writing has priority. Figure 16.67 shows the timing in this case. TRDCNT write cycle T1 T2 TRDCNT address WTRDCNT (internal write signal) TRDCNT input clock TRDCNT N TRDCNT write data M Figure 16.67 Conflict between TRDCNT Write and Increment Operations Rev. 1.00 Oct. 03, 2008 Page 593 of 962 REJ09B0465-0100 Section 16 Timer RD (4) Conflict between GR Write and Compare Match If a compare match occurs in the T2 state of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure 16.68 shows the timing in this case. GR write cycle T1 T2 GR address WGR (internal write signal) TRDCNT N N+1 GR N GR write data M Compare match signal Disabled Figure 16.68 Conflict between GR Write and Compare Match Rev. 1.00 Oct. 03, 2008 Page 594 of 962 REJ09B0465-0100 Section 16 Timer RD (5) Conflict between TRDCNT Write and Overflow/Underflow If overflow/underflow occurs in the T2 state of a TRDCNT write cycle, TRDCNT write has priority without an increment operation. At this time, the OVF flag is set to 1. Figure 16.69 shows the timing in this case. TRDCNT write cycle T1 T2 TRDCNT address WTRDCNT (internal write signal) TRDCNT input clock Overflow signal TRDCNT H'FFFF TRDCNT write data M OVF Figure 16.69 Conflict between TRDCNT Write and Overflow Rev. 1.00 Oct. 03, 2008 Page 595 of 962 REJ09B0465-0100 Section 16 Timer RD (6) Conflict between GR Read and Input Capture If an input capture signal is generated in the T2 state of a GR read cycle, the data that is read will be transferred before input capture transfer. Figure 16.70 shows the timing in this case. GR read cycle T1 T2 GR address Internal read signal Input capture signal GR X M Internal data bus X Figure 16.70 Conflict between GR Read and Input Capture Rev. 1.00 Oct. 03, 2008 Page 596 of 962 REJ09B0465-0100 Section 16 Timer RD (7) Conflict between Count Clearing and Increment Operations by Input Capture If an input capture and increment signals are simultaneously generated, count clearing by the input capture operation has priority without an increment operation. The TRDCNT contents before clearing counter are transferred to GR. Figure 16.71 shows the timing in this case. Input capture signal Counter clear signal TRDCNT input clock TRDCNT N H'0000 GR N Clearing has priority. Figure 16.71 Conflict between Count Clearing and Increment Operations by Input Capture Rev. 1.00 Oct. 03, 2008 Page 597 of 962 REJ09B0465-0100 Section 16 Timer RD (8) Conflict between GR Write and Input Capture If an input capture signal is generated in the T2 state of a GR write cycle, the input capture operation has priority and the write to GR is not performed. Figure 16.72 shows the timing in this case. GR write cycle T1 T2 Address bus GR address WGR (internal write signal) Input capture signal TRDCNT N GR M GR write data Figure 16.72 Conflict between GR Write and Input Capture Rev. 1.00 Oct. 03, 2008 Page 598 of 962 REJ09B0465-0100 Section 16 Timer RD (9) Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode When bits CMD1 and CMD0 in TRDFCR are set, note the following: * Write bits CMD1 and CMD0 while TRDCNT_1 and TRDCNT_0 are halted. * Changing the settings of reset synchronous PWM mode to complementary PWM mode or vice versa is disabled. Set reset synchronous PWM mode or complementary PWM mode after the normal operation (bits CMD1 and CMD0 are cleared to 0) has been set. (10) Note on Writing to the TOA0 to TOD0 Bits and the TOA1 to TOD1 Bits in TRDOCR The TOA0 to TOD0 bits and the TOA1 to TOD1 bits in TRDOCR decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, the values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output and the values read from the TOA0 to TOD0 and TOA1 to TOD1 bits may differ. Moreover, when the writing to TRDOCR and the generation of the compare match A0 to D0 and A1 to D1 occur at the same timing, the writing to TRDOCR has the priority. Thus, output change due to the compare match is not reflected to the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pins. Therefore, when bit manipulation instruction is used to write to TRDOCR, the values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output may result in an unexpected result. When TRDOCR is to be written to while compare match is operating, stop the counter once before accessing to TRDOCR, read the port 6 state to reflect the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, to TOA0 to TOD0 and TOA1 to TOD1, and then restart the counter. Figure 16.73 shows an example when the compare match and the bit manipulation instruction to TRDOCR occur at the same timing. Rev. 1.00 Oct. 03, 2008 Page 599 of 962 REJ09B0465-0100 Section 16 Timer RD TRDOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B0. When BCLR#2, @TRDOCR is executed to clear the TOC0 bit (the FTIOC0 signal is low) and compare match B0 occurs at the same timing as shown below, the H'02 writing to TRDOCR has priority and compare match B0 does not drive the FTIOB0 signal low; the FTIOB0 signal remains high. Bit TRDOCR Set value 7 TOD1 0 6 TOC1 0 5 TOB1 0 4 TOA1 0 3 TOD0 0 2 TOC0 1 1 TOB0 1 0 TOA0 0 BCLR#2, @TRDOCR (1) TRDOCR read operation: Read H'06 (2) Modify operation: Modify H'06 to H'02 (3) Write operation to TRDOCR: Write H'02 TRDOCR write signal Compare match signal B0 FTIOB0 pin Expected output Remains high because the 1 writing to TOB has priority Figure 16.73 When Compare Match and Bit Manipulation Instruction to TRDOCR Occur at the Same Timing Rev. 1.00 Oct. 03, 2008 Page 600 of 962 REJ09B0465-0100 Section 16 Timer RD (11) Restrictions on Access to Registers when Internal 40 Clock is Selected as Counter Clock When the internal 40 clock is selected as the counter clock (the TPSC[2:0] bits in TRDCR = 110), if any register of timer RD is to be read immediately after writing to another register in a given module, proceed with reading after having executed one NOP instruction. Timer RD unit 0 and 1 are considered to be separate modules, but channels 0 and 1 (or channels 2 and 3) of the same unit are considered to be in the same module. Write to TRDSTR. Execute NOP. Read TRDCNT. Figure 16.74 Example of Flow for Reading Immediately after Writing to a Register Rev. 1.00 Oct. 03, 2008 Page 601 of 962 REJ09B0465-0100 Section 16 Timer RD Rev. 1.00 Oct. 03, 2008 Page 602 of 962 REJ09B0465-0100 Section 17 Timer RE Section 17 Timer RE Timer RE is a timer that provides a realtime clock function to count time ranging from a second to a week and a compare-match function. Figure 17.1 shows a block diagram of the timer RE. 17.1 Features * Realtime clock mode Counts seconds, minutes, hours, and day-of-week Start/stop function Reset function Readable/writable counter of seconds, minutes, hours, and day-of-week with BCD codes Periodic (seconds, minutes, hours, days, and weeks) interrupts * Output-compare mode 8-bit counter with a compare-match function Selection of clock source Compare-match interrupt Rev. 1.00 Oct. 03, 2008 Page 603 of 962 REJ09B0465-0100 Section 17 Timer RE TREO pin PSC divider sub TRECSR TRESEC Clock count control circuit TREHR TREWK TRECR1 TREIFR TRECR2 Interrupt control circuit Interrupt request Figure 17.1 Block Diagram of Timer RE Table 17.1 shows the timer RE input/output pin. Table 17.1 Pin Configuration Pin Name TREO I/O Output Function Clock or compare-match output Rev. 1.00 Oct. 03, 2008 Page 604 of 962 REJ09B0465-0100 Bus interface TREMIN Section 17 Timer RE 17.2 Register Descriptions The timer RE has the following registers. * * * * * * * * Timer RE second data register/counter data register (TRESEC) Timer RE minute data register (TREMIN) Timer RE hour data register (TREHR) Timer RE day-of-week data register (TREWK) Timer RE control register 1 (TRECR1) Timer RE control register 2 (TRECR2) Timer RE clock source select register (TRECSR) Timer RE interrupt flag register (TREIRF) Rev. 1.00 Oct. 03, 2008 Page 605 of 962 REJ09B0465-0100 Section 17 Timer RE 17.2.1 Timer RE Second Data Register/Counter Data Register (TRESEC) Address: H'FFFFA8 Bit: b7 BSY b6 SC12 b5 SC11 b4 SC10 b3 SC03 b2 SC02 b1 SC01 b0 SC00 Value after reset: * Realtime clock mode Bit Symbol Bit Name 7 BSY Description R/W Timer RE busy This bit is set to 1 when the timer RE is updating (calculating) R the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. Counting ten's Counts on 0 to 5 for 60-second counting. position of seconds Counting one's Counts on 0 to 9 once per second. When a carry is position of generated, 1 is added to the ten's position. seconds R/W R/W R/W R/W R/W R/W R/W 6 5 4 3 2 1 0 SC12 SC11 SC10 SC03 SC02 SC01 SC00 * Output-compare mode Bit Symbol 7 6 5 4 3 2 1 0 BSY SC12 SC11 SC10 SC03 SC02 SC01 SC00 Bit Name Description Used as an 8-bit register for reading the counter data. R/W R The counter value is retained when counting is stopped. R/W This register is initialized to H'00 with a compare-match. R/W R/W R/W R/W R/W R/W TRESEC counts the BCD-coded second value in realtime clock mode. TRESEC is incremented from decimal 00 to 59. TRESEC is used as an 8-bit register for reading the counter data in outputcompare mode. Rev. 1.00 Oct. 03, 2008 Page 606 of 962 REJ09B0465-0100 Section 17 Timer RE 17.2.2 Timer RE Minute Data Register/Compare Data Register (TREMIN) Address: H'FFFFA9 Bit: b7 BSY b6 MN12 b5 MN11 b4 MN10 b3 MN03 b2 MN02 b1 MN01 b0 MN00 Value after reset: * Realtime clock mode Bit Symbol Bit Name 7 BSY Description R/W Timer RE busy This bit is set to 1 when the timer RE is updating (calculating) R the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. Counting ten's Counts on 0 to 5 for 60-minute counting. position of minutes Counting one's Counts on 0 to 9 once per minute. When a carry is position of generated, 1 is added to the ten's position. minutes R/W R/W R/W R/W R/W R/W R/W 6 5 4 3 2 1 0 MN12 MN11 MN10 MN03 MN02 MN01 MN00 * Output-compare mode Bit Symbol 7 6 5 4 3 2 1 0 BSY MN12 MN11 MN10 MN03 MN02 MN01 MN00 Bit Name Description Used as an 8-bit register for storing the compare data. The setting range is H'01 to H'FF. R/W R R/W This register can be written to only when counting is R/W stopped (when TSTART and TCSTF in TRECR1 are 0). R/W R/W R/W R/W R/W TREMIN counts the BCD-coded minute value on the carry generated once per minute by the TRESEC counting in realtime clock mode. TREMIN is incremented from decimal 00 to 59. TREMIN is used as an 8-bit register for storing the compare data in output-compare mode. Rev. 1.00 Oct. 03, 2008 Page 607 of 962 REJ09B0465-0100 Section 17 Timer RE 17.2.3 Timer RE Hour Data Register (TREHR) Address: H'FFFFAA Bit: b7 BSY b6 b5 HR11 b4 HR10 b3 HR03 b2 HR02 b1 HR01 b0 HR00 Value after reset: 0 Bit Symbol Bit Name 7 BSY Description R/W Timer RE busy This bit is set to 1 when the timer RE is updating (calculating) R the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. Reserved Counting ten's position of hours This bit is read as 0. The write value should be 0. Counts on 0 to 2 for ten's position of hours R/W R/W 6 5 4 3 2 1 0 HR11 HR10 HR03 HR02 HR01 HR00 Counting one's Counts on 0 to 9 once per hour. When a carry is generated, 1 R/W position of is added to the ten's position. R/W hours R/W R/W TREHR is used in realtime clock mode and counts the BCD-coded hour value on the carry generated once per hour by TREMIN. TREHR is incremented either from decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in TRECR1. This register is not used in output-compare mode. Rev. 1.00 Oct. 03, 2008 Page 608 of 962 REJ09B0465-0100 Section 17 Timer RE 17.2.4 Timer RE Day-of-Week Data Register (TREWK) Address: H'FFFFAB Bit: b7 BSY b6 b5 b4 b3 b2 b1 WK[2:0] b0 Value after reset: 0 0 0 0 Bit 7 Symbol Bit Name BSY Description R/W Timer RE busy This bit is set to 1 when the timer RE is updating R (calculating) the values of second, minute, hour, and dayof-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. Reserved These bits are read as 0. The write value should be 0. 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Setting prohibited R/W 6 to 3 2 to 0 WK[2:0] Day-of-week counting TREWK is used in realtime clock mode and counts the BCD-coded day-of-week value on the carry generated once per day by TREHR. Bits WK[2:0] indicate the day of the week with a binary code, ranging from decimal 0 to 6. This register is not used in output-compare mode. Rev. 1.00 Oct. 03, 2008 Page 609 of 962 REJ09B0465-0100 Section 17 Timer RE 17.2.5 Timer RE Control Register 1 (TRECR1) Address: H'FFFFAC Bit: b7 TSTART b6 H12_H24 b5 PM b4 TRERST 0 b3 INT 0 b2 TOENA 0 b1 TCSTF b0 Value after reset: 0 * Realtime clock mode Bit Symbol 7 6 TSTART H12_H24*1 Bit Name Description R/W R/W R/W 0: Stops timer counter operation Counter operation start 1: Starts timer counter operation Operating mode 0: The timer RE operates in 12-hour mode. TREHR counts on 0 to 11. 1: The timer RE operates in 24-hour mode. TREHR counts on 0 to 23. 5 PM*1 a.m./p.m. 0: Indicates a.m. when the timer RE is in the 12-hour mode. 1: Indicates p.m. when the timer RE is in the 12-hour mode. 0: Normal operation 1: Resets all the registers and control circuits, except TRECSR and the TOENA and TRESET bits in this register. Clear this bit to 0 after having been set to 1. 0: Generates a second, minute, hour, or day-of-week periodic interrupt during timer RE busy period. 1: Generates a second, minute, hour, or day-of-week periodic interrupt immediately after completing timer RE busy period.*2 R/W R R/W 4 TRESET Reset R/W 3 INT*1 Interrupt generation timing R/W 2 1 0 TOENA TCSTF TREO pin 0: Disables timer RE divided clock output. output enable 1: Enables timer RE divided clock output. Operation status flag Reserved 0: Indicates that timer RE operation has been stopped. 1: Indicates that timer RE operation is in progress. This bit is read as 0. The write value should be 0. Note: 1. Bits H12_H24, PM, and INT should be set when the timer RE operation is stopped. 2. This bit should be set to 1 in realtime clock mode and cleared to 0 in output compare mode. Rev. 1.00 Oct. 03, 2008 Page 610 of 962 REJ09B0465-0100 Section 17 Timer RE TRECR1 controls start/stop and reset of the counter. For the definition of time expression, see figure 17.2. Noon 24-hour count 12-hour count 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 0 13 1 14 2 15 3 16 4 17 5 PM TREWK 0 (Morning) 1 (Afternoon) 000 (Sunday) Date changes. 24-hour count 12-hour count 18 6 19 7 20 8 21 9 22 10 23 11 0 0 1 1 2 2 0 (Morning) 3 3 ... ... ... ... PM TREWK 1 (Afternoon) 000 (Sunday) 001 (Monday) Figure 17.2 Definition of Time Expression Rev. 1.00 Oct. 03, 2008 Page 611 of 962 REJ09B0465-0100 Section 17 Timer RE * Output-compare mode Bit Symbol 7 6 5 4 TSTART H12_H24 PM TRESET Bit Name Counter operation start Description 0: Stops timer counter operation. 1: Starts timer counter operation. R/W R/W R/W 0 should be written to this bit in output-compare mode. 0: Normal operation 1: Resets all the registers and control circuits, except TRECSR and the TOENA and TRESET bits in this register. Clear this bit to 0 after having been set to 1. 0 should be written to this bit in output-compare mode. R/W R/W Operating mode 0 should be written to this bit in output-compare mode. a.m./p.m. Reset 3 INT Interrupt generation timing TREO pin output enable R/W 2 1 0 TOENA TCSTF 0: Disables timer RE divided clock output. 1: Enables timer RE divided clock output. R/W R Operation status 0: Indicates that timer RE operation has been stopped. flag 1: Indicates that timer RE operation is in progress. Reserved This bit is read as 0. The write value should be 0. Note: After writing 1 to TSTART, the timer RE should not be accessed before reading 1 from TCSTF, with the exception of reading TCSTF. Similarly, after writing 0 to TSTART, the timer RE should not be accessed before reading 0 from TCSTF, with the exception of reading TCSTF. Rev. 1.00 Oct. 03, 2008 Page 612 of 962 REJ09B0465-0100 Section 17 Timer RE 17.2.6 Timer RE Control Register 2 (TRECR2) Address: H'FFFFAD Bit: b7 b6 b5 COMIE 0 b4 WKIE 0 b3 DYIE 0 b2 HRIE 0 b1 MNIE 0 b0 SEIE 0 Value after reset: 0 0 Bit 7, 6 5 Symbol Bit Name COMIE Reserved Compare-match interrupt enable Description R/W These bits are read as 0. The write value should be 0. 0: Disables a compare-match interrupt 1: Enables a compare-match interrupt This bit should be 0 in realtime clock mode. 0: Disables a week periodic interrupt 1: Enables a week periodic interrupt This bit should be 0 in output-compare mode. 0: Disables a day periodic interrupt 1: Enables a day periodic interrupt This bit should be 0 in output-compare mode. 0: Disables an hour periodic interrupt 1: Enables an hour periodic interrupt This bit should be 0 in output-compare mode. 0: Disables a minute periodic interrupt 1: Enables a minute periodic interrupt This bit should be 0 in output-compare mode. 0: Disables a second periodic interrupt 1: Enables a second periodic interrupt This bit should be 0 in output-compare mode. R/W R/W R/W R/W R/W R/W 4 WKIE Week periodic interrupt enable Day periodic interrupt enable Hour periodic interrupt enable Minute periodic interrupt enable Second periodic interrupt enable 3 DYIE 2 HRIE 1 MNIE 0 SEIE Notes: 1. When using interrupts, this register should be set last after other registers are set. 2. The COMIE bit should be set when counting operation is stopped. 3. Bits WKIE, DYIE, HRIE, MNIE, and SEIE should be set when timer RE operation is stopped. TRECR2 controls timer RE periodic interrupts of weeks, days, hours, minutes, and seconds in realtime clock mode. Enabling interrupts of weeks, days, hours, minutes, and seconds sets the interrupt request flag to 1 in the timer RE interrupt flag register (TREIFR) when an interrupt occurs. It also controls a compare-match interrupt when output-compare mode is used. Rev. 1.00 Oct. 03, 2008 Page 613 of 962 REJ09B0465-0100 Section 17 Timer RE 17.2.7 Timer RE Interrupt Flag Register (TREIFR) Address: H'FFFFAE Bit: b7 b6 b5 COMF 0 b4 WKF 0 b3 DYF 0 b2 HRF 0 b1 MNF 0 b0 SECE 0 Value after reset: 0 0 Bit Symbol Bit Name Reserved Comparematch interrupt request flag Description These bits are read as 0. The write value should be 0. [Setting condition] * When the counter value matches the value set in TREMIN in output-compare mode. When 1 is read from the bit and then 0 is written to the bit. R/W R/W 7, 6 5 COMF [Clearing condition] * 4 WKF Week periodic [Setting condition] R/W interrupt * When bits WK[2:0] in TREWK reach B'000 in realtime request flag clock mode. [Clearing condition] * When 1 is read from the bit and then 0 is written to the bit. When the DTC is activated with a week periodic interrupt and the DISEL bit in the MRB register of the DTC is 1. 3 DYF Day periodic interrupt request flag [Setting condition] * Each time TREWK is updated in realtime clock mode. (Occurs every day) When 1 is read from the bit and then 0 is written to the bit. When the DTC is activated with a day periodic interrupt and the DISEL bit in the MRB register of the DTC is 1. R/W [Clearing conditions] * * Rev. 1.00 Oct. 03, 2008 Page 614 of 962 REJ09B0465-0100 Section 17 Timer RE Bit 2 Symbol HRF Bit Name Hour periodic interrupt request flag Description [Setting condition] * Each time TREHR is updated in realtime clock mode. (Occurs every hour) When 1 is read from the bit and then 0 is written to the bit. When the DTC is activated with an hour periodic interrupt and the DISEL bit in the MRB register of the DTC is 1. R/W R/W [Clearing conditions] * * 1 MNF Minute periodic interrupt request flag [Setting condition] * Each time TREMIN is updated in realtime clock mode. (Occurs every minute) When 1 is read from the bit and then 0 is written to the bit. When the DTC is activated with a minute periodic interrupt and the DISEL bit in the MRB register of the DTC is 1. R/W [Clearing conditions] * * 0 SECF Second periodic interrupt request flag [Setting condition] * Each time TRESEC is updated in realtime clock mode. (Occurs every second) When 1 is read from the bit and then 0 is written to the bit. When the DTC is activated with a second periodic interrupt and the DISEL bit in the MRB register of the DTC is 1. R/W [Clearing conditions] * * Rev. 1.00 Oct. 03, 2008 Page 615 of 962 REJ09B0465-0100 Section 17 Timer RE 17.2.8 Timer RE Clock Source Select Register (TRECSR) Address: H'FFFFAF Bit: b7 b6 b5 RCS[6:4] b4 b3 RCS3 b2 RCS2 0 b1 RCS[1:0] 0 b0 Value after reset: 0 0 0 0 1 0 Bit 7 6 to 4 Symbol RCS[6:4]* 2 Bit Name Reserved Clock output select Description This bit is read as 0. The write value should be 0. 000: /2 001: /4 010: /8 011: Compare-match output (Only valid in outputcompare mode) 100: /sub (32.768 kHz) 101: 1 Hz (Only valid in realtime clock mode) 11x: Setting prohibited R/W R/W 3 2 RCS3 RCS2 Mode select 4-bit counter select 0: Output-compare mode 1: Realtime clock mode (Only valid in output-compare mode) 0: Does not use the 4-bit counter. 1: Uses the 4-bit counter. 00: /2 01: /4 10: /8 11: /sub R/W R/W 1, 0 RCS[1:0] *1*3 Clock source select R/W [Legend] X: Don't care Notes: 1. RCS[1:0] should be set when realtime clock mode is used or when counter operation is stopped. 2. RCS[6:4] should be set when the TOENA bit in TRECR1 is 0. 3. In output compare mode, when the CPU is in a sub clock mode, do not select the sub clock as the clock source for the timer. Rev. 1.00 Oct. 03, 2008 Page 616 of 962 REJ09B0465-0100 Section 17 Timer RE TRECSR selects clock output, operating mode, and clock source. * RCS6 to RCS4 (clock output select) Selects a clock output from the TREO pin when the TOENA bit in TRECR1 is set to 1. * RCS1 and RCS0 (clock source select) Selects a clock source for output-compare mode. For realtime clock mode, the subclock sub (32.768 kHz) is selected regardless of the setting of these bits. Rev. 1.00 Oct. 03, 2008 Page 617 of 962 REJ09B0465-0100 Section 17 Timer RE 17.3 17.3.1 Operation of Realtime Clock Mode Initial Settings of Registers after Power-On The timer RE registers that contain second, minute, hour, and day-of-week data are not initialized by a reset by the RES pin, LVD, or watchdog timer. Therefore, all registers must be set to their initial values after power-on. Once the register settings are made, the timer RE provides an accurate time as long as power is supplied regardless of the RES pin, VLD, or watchdog timer reset. 17.3.2 Initial Setting Procedure Figure 17.3 shows the procedure for the initial setting of the timer RE to be used in realtime clock mode. To set the timer RE again, also follow this procedure. Rev. 1.00 Oct. 03, 2008 Page 618 of 962 REJ09B0465-0100 Section 17 Timer RE TSTART in TRECR1=0 Timer RE operation is stopped. TCSTF in TRECR1=0? TRERST in TRECR1=1 Timer RE registers and control circuit are reset. TRERST in TRECR1=0 Set TRECSR, TRESEC, TREMIN, TREHR, TREWK, TRECR1, H12_H24, PM, and INT. Clock output and clock source are selected and second, minute, hour, day-of-week, operating mode, a.m/p.m, and interrupt source are set. Set TRECR2. TSTART in TRECR1=1 An interrupt source is selected. Timer RE operation is started. TCSTF in TRECR1=1? Figure 17.3 Initial Setting Procedure Rev. 1.00 Oct. 03, 2008 Page 619 of 962 REJ09B0465-0100 Section 17 Timer RE 17.3.3 Data Reading Procedure in Realtime Clock Mode When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 17.4 shows an example in which correct data is not obtained. In this example, since only TRESEC is read after data update, about 1-minute inconsistency occurs. The following three methods can be used to avoid reading in this timing: 1. Check the setting of the BSY bit, and when the BSY bit changes from 1 to 0, read from the second, minute, hour, and day-of-week registers. When about 62.5 ms is passed after the BSY bit is set to 1, the registers are updated, and the BSY bit is cleared to 0. 2. Making use of interrupts, read from the second, minute, hour, and day-of week registers after the SECF flag in TREIFR is set to 1 and the BSY bit is confirmed to be 0. 3. Read from the second, minute, hour, and day-of week registers twice in a row, and if there is no change in the read data, the read data is used. Before update TREWK = H'03, TREHR = H'13, TREMIN = H'46, TRESEC = H'59 Rev. 1.00 Oct. 03, 2008 Page 620 of 962 REJ09B0465-0100 Processing flow BSY bit = 0 (1) Day-of-week data register read (2) Hour data register read (3) Minute data register read H'03 H'13 H'46 BSY bit -> 1 (under data update) After update BSY bit -> 0 TREWK = H'03, TREHR = H'13, TREMIN = H'47, TRESEC = H'00 (4) Second data register read H'00 Figure 17.4 Example: Reading of Inaccurate Time Data Section 17 Timer RE 17.3.4 Operation in Realtime Clock Mode Figure 17.5 shows an example of realtime clock mode operation. 1s Approx. 62.5ms BSY bit Approx. 62.5ms SC12 to SC00 in TRESEC 58 59 00 MIN12 to MIN00 in TREMIN 03 04 HR11 to HR00 in TREHR (Not change) "1" PM in TRECR "0" (Not change) WK2 to WK0 in TREWK (Not change) SECF in TREIFR "1" "0" Set to 0 by accepting an interrupt request or by a program. MNF in TREIFR "1" "0" BSY: Bit in TRESEC, TREMIN, TREHR, and TREWK Figure 17.5 Example of Realtime Clock Mode Operation Rev. 1.00 Oct. 03, 2008 Page 621 of 962 REJ09B0465-0100 Section 17 Timer RE 17.4 Operation of Output Compare Mode Writing 0 to the RCS3 bit in TRECSR sets the timer RE in output compare mode and causes it to operate as a counter provided with an 8-bit compare match function. Four count sources can be selected. When used in output compare mode, the timer RE should be initialized in reference to figure 17.3. The count source selected by the RCS1 and RCS0 bits is divided into two and counted with an 8bit counter. Setting 1 to the RCS2 bit in TRECSR causes the count source divided into two to be counted with a 4-bit counter, and the 8-bit counter counts overflows of the 4-bit counter. TREMIN sets a compare value. By reading TRESEC, it is possible to read values from the 8-bit counter. In this mode, TREHR or TREWK is not used. Setting bits RCS6 to RCS4 in TRECSR to B'011 and setting the TOENA bit in TRECR1 to 1 produces toggle output from the TREO pin each time the value of the 8-bit counter matches the value of TREMIN (initial value: low output). Also, by setting the COMIE bit in TRECR2 to 1, it is possible to generate a compare match interrupt request. The counter, using the TSTART bit in TRECR1, controls the start/stop of counter operation. Figure 17.6 shows a block diagram of output compare mode; figure. 17.7 shows an operation example. Rev. 1.00 Oct. 03, 2008 Page 622 of 962 REJ09B0465-0100 Section 17 Timer RE /2 /4 /8 sub Output control circuit TREO pin 1/4 RCS[1:0] 1/2 4-bit counter RCS2 Comparison circuit 8-bit counter Match signal Interrupt request /32 Interrupt control circuit TRESEC TREMIN Internal data bus [Legend] TRESEC: Timer RE second data register/counter data register TREMIN: Timer RE minute data register/compare data register RCS2 to RCS0: Bits 2 to 0 in TRECSR Figure 17.6 Block Diagram of Output Compare Mode Rev. 1.00 Oct. 03, 2008 Page 623 of 962 REJ09B0465-0100 Section 17 Timer RE 8-bit counter content Value set in TREMIN Start counting. Match Match Match H'00 Time Set to 1 by a program. TSTART in TRECR1 "1" "0" Two cycles of the maximum count source "1" "0" Set to 0 by a program. TCSTF in TRECR1 COMF in TREIFR "1" "0" "H" "L" Output polarity is inverted on a compare match . Conditions for the above operation: TOENA in TRECR1 = 1 (clock output enabled) RCS[6:4] in TRECSR = B'011 (compare output) TREO output Figure 17.7 Example of Output Compare Mode Operation Rev. 1.00 Oct. 03, 2008 Page 624 of 962 REJ09B0465-0100 Section 17 Timer RE 17.5 Interrupt Sources There are six kinds of timer RE interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts in realtime clock mode, and compare-match interrupts in output compare mode. Table 17.2 shows the interrupt sources. When using an interrupt, initiate the timer RE last after other registers are set. Independent vector addresses are allocated to each timer RE interrupt source. Table 17.2 Interrupt Sources Interrupt Name Compare-match interrupt Week periodic interrupt Day periodic interrupt Hour periodic interrupt Minute periodic interrupt Second periodic interrupt Interrupt Source Occurs when the count value matches the compare data. Occurs every week when the day-of-week data register value becomes 0. Interrupt Enable Bit COMIE WKIE Occurs every day when the day-of-week data DYIE register value is incremented. Occurs every hour when the hour date register value is incremented. Occurs every minute when the minute data register value is incremented. Occurs every second when the second data register value is incremented. HRIE MNIE SCIE Rev. 1.00 Oct. 03, 2008 Page 625 of 962 REJ09B0465-0100 Section 17 Timer RE 17.6 (1) Usage Notes Starting and Stopping Counting Process The timer RE includes a TSTART bit that directs the start or stop of the counting process, and a TCSTF bit that indicates that the counting process has started or stopped. Setting the TSTART bit to 1 causes the timer RE to start counting and assigns 1 to the TCSTF bit. From the time the TSTART bit is set to 1 and to the time the TCSTF bit turns 1, a maximum of 2 cycles of count sources are required. During this time period, the timer RE related registers*, with the exception of the TCSTF bit, should not be accessed. Similarly, clearing the TSTART bit to 0 causes the timer RE to stop counting, and assigns 0 to the TCSTF bit. From the time the TSTART bit is set to 0 and to the time the TCSTF bit turns 0, the timer RE related registers*, with the exception of the TCSTF bit, should not be accessed. Note: Timer RE related registers: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and TRECSR (2) Register Settings of Timer RE The following registers and bits should be written when the timer RE is stopped. The condition "timer RE stopped" refers to the condition in which both the TSTART and TCSTF bits in TRECR1 are 0. Set TRECR2 at the end of setting the above registers and bits (before the timer RE counting process is started). * Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 * Bits H12_H24 bit, PM, and INT in TRECR1 * Bits RCS0 to RCS3 in TRECSR (3) Sampling Circuit for Noise Canceler in Subclock Signal In realtime clock mode, always enable the sampling circuit with the SUBNC[1:0] bits in SYSCCR. For details of the SUBNC[1:0] bits, see section 5.2.2, System Clock Control Register (SYSCCR). (4) Restrictions on Clock Selection in Output Compare Mode In output compare mode, do not select the subclock as the clock source for the timer if the CPU is in sub mode. Rev. 1.00 Oct. 03, 2008 Page 626 of 962 REJ09B0465-0100 Section 18 Timer RG Section 18 Timer RG Timer RG is a 16-bit timer with output compare and input capture functions. Timer RG can count using a number of internal or external clocks and output pulses with a desired duty cycle using the compare match function between the timer counter and two general registers. Timer RG is also able to decode the phase difference between two external clocks and increment. Timer RG therefore provides an ideal solution for many systems with a requirement to decide position based on a rotary encoder or tachometer as well as a wide range of other applications. 18.1 Features * Selection of seven counter clock sources Internal clocks: , /2, /4, /8, /32 and 40 External clocks: TCLKA, TCLKB * Timer mode Waveform output by compare match (Selection of 0 output, 1 output, or toggle output) Input capture function (Rising edge, falling edge, or both edges) * PWM mode Generates pulses with a desired period and duty cycle. * Phase counting mode Detects phase difference between two external clock inputs and increments/decrements the TCNT. * Fast access via internal 16-bit bus Performs high-speed accesses to the timer counter and general registers using the 16-bit bus interface. * Four interrupt sources TRGCNT overflow, TRGCNT underflow, compare match, and input capture Rev. 1.00 Oct. 03, 2008 Page 627 of 962 REJ09B0465-0100 Section 18 Timer RG Table 18.1 Functions of Timer RG Input/Output Pins Item Counter clock General registers (multiplexed registers with output compare/input capture) Buffer register Counter clearing function Counter TGIOA TGIOB Internal clocks: , /2, /4, /8, /32, and 40 External clock: TCLKA, TCLKB GRA GRB BRA Compare match/ input capture Yes Yes Yes Yes Yes Yes Yes Compare match/ input capture BRB Compare match/ input capture Yes Yes Yes Yes Yes Yes Yes Compare match/ input capture Initial output value setting function Buffer operation Compare match output 0 output 1 output Toggle output Input capture function PWM mode Phase counting mode Interrupt sources Overflow Underflow Write to TRGMDR. Execute NOP. Read TRGCNT. Figure 18.1 Timer RG Block Diagram Rev. 1.00 Oct. 03, 2008 Page 628 of 962 REJ09B0465-0100 Section 18 Timer RG Table 18.2 summarizes the timer RG pins. Table 18.2 Pin Configuration Pin Name TCLKA TCLKB TGIOA I/O Input Input I/O Function External clock A input pin (Phase A input pin in phase counting mode) External clock B input pin (Phase B input pin in phase counting mode) GRA output compare output pin/ GRA input capture input pin/ PWM output pin in PWM mode GRB output compare output pin/ GRB input capture input pin TGIOAB I/O Rev. 1.00 Oct. 03, 2008 Page 629 of 962 REJ09B0465-0100 Section 18 Timer RG 18.2 Register Descriptions Timer RG has the following registers. * * * * * * * * * * * Timer RG mode register (TRGMDR) Timer RG counter control register (TRGCNTCR) Timer RG control register (TRGCR) Timer RG I/O control register (TRGIOR) Timer RG status register (TRGSR) Timer RG interrupt enable register (TRGIER) Timer RG counter (TRGCNT) General register A (GRA) General register B (GRB) GRA buffer register (BRA) GRB buffer register (BRB) Rev. 1.00 Oct. 03, 2008 Page 630 of 962 REJ09B0465-0100 Section 18 Timer RG 18.2.1 Timer RG Mode Register (TRGMDR) Address: H'FF0646 Bit: b7 STR b6 b5 DFCK[1:0] 0 b4 b3 DFB b2 DFA 0 b1 MDF 0 b0 PWM 0 Value after reset: 0 1 0 0 Bit Symbol 7 6 5, 4 STR DFCK[1:0] Bit Name Counter start Reserved Digital filter clock select Description 0: TRGCNT stops counting. 1: TRGCNT performs counting. This bit is read as 1. The write value should be 1. 00: /32 (initial value) 01: /8 10: 11: /32Clock specified by bits CKS2 to CKS0 in TRGCR R/W R/W R/W 3 DFB TGIOB pin 0: Disables the digital filter for the TGIOB pin. digital filter 1: Enables the digital filter for the TGIOB pin. function select TGIOB pin 0: Disables the digital filter for the TGIOA pin. digital filter 1: Enables the digital filter for the TGIOA pin. function select Phase 0: Increments the counter.*1 counting mode 1: Phase counting mode select PWM mode select 0: Usual mode*2 1: PWM mode R/W 2 DFA R/W 1 MDF R/W 0 PWM R/W Note: 1. Select counting up in PWM mode. 2. Select normal mode here when the MDF bit is set for phase counting mode. * STR bit (Counter start) Clearing this bit to 0 stops counting by TRGCNT. Counting by TRGCNT proceeds while this bit is set to 1. This bit is set to 1 if the specified event occurs when operation of timer RG has been selected in ELOPC of the event link controller. Rev. 1.00 Oct. 03, 2008 Page 631 of 962 REJ09B0465-0100 Section 18 Timer RG * MDF bit (Phase counting mode select) When this bit is 0, the counter counts the clock pulses specified with the TPSC2 to TPSC0 bits in TRGCR. When this bit is 1, the counter counts the phases produced by TCLKA and TCLKB as specified in TRGCNTCR. 18.2.2 Timer RG Counter Control Register (TRGCNTCR) Address: H'FF0647 Bit: b7 CNTEN7 Value after reset: 0 b6 CNTEN6 0 b5 CNTEN5 0 b4 CNTEN4 0 b3 CNTEN3 0 b2 CNTEN2 0 b1 CNTEN1 0 b0 CNTEN0 0 Bit Symbol Bit Name 7 6 5 4 3 2 1 0 Description R/W R/W CNTEN7 Count enable 0: Not affected by the TCLKB rising edge when TCLKA is low. bit 7 1: Incremented at the TCLKB rising edge when TCLKA is low. CNTEN6 Count enable 0: Not affected by the TCLKA rising edge when TCLKB is high. R/W bit 6 1: Incremented at the TCLKA rising edge when TCLKB is high. CNTEN5 Count enable 0: Not affected by the TCLKB falling edge when TCLKA is high. R/W bit 5 1: Incremented at the TCLKB falling edge when TCLKA is high. CNTEN4 Count enable 0: Not affected by the TCLKA falling edge when TCLKB is low. R/W bit 4 1: Incremented at the TCLKA falling edge when TCLKB is low. CNTEN3 Count enable 0: Not affected by the TCLKA falling edge when TCLKB is high. R/W bit 3 1: Incremented at the TCLKA falling edge when TCLKB is high. CNTEN2 Count enable 0: Not affected by the TCLKB falling edge when TCLKA is low. R/W bit 2 1: Incremented at the TCLKB falling edge when TCLKA is low. CNTEN1 Count enable 0: Not affected by the TCLKA rising edge when TCLKB is low. bit 1 1: Incremented at the TCLKA rising edge when TCLKB is low. R/W CNTEN0 Count enable 0: Not affected by the TCLKB rising edge when TCLKA is high. R/W bit 0 1: Incremented at the TCLKB rising edge when TCLKA is high. Rev. 1.00 Oct. 03, 2008 Page 632 of 962 REJ09B0465-0100 Section 18 Timer RG 18.2.3 Timer RG Control Register (TRGCR) Address: H'FF0648 Bit: b7 b6 b5 b4 b3 b2 b1 TPSC[2:0] b0 CCLR[1:0] 0 0 0 CKEG[1:0] 0 0 Value after reset: 1 0 0 Bit 7 6, 5 Symbol CCLR[1:0] Bit Name Reserved Counter clear source select Description This bit is read as 1. The write value should be 1. 00: Disables clearing TRGCNT. 01: Clears TRGCNT with a GRA compare match/input capture. 1X: Clears TRGCNT with a GRB compare match/input capture. R/W R/W 4, 3 CKEG[1:0] External clock detection edge select 00: Incremented at the rising edges. 01: Incremented at the falling edges. 1x: Incremented at the rising and falling edges. R/W 2 to 0 TPSC[2:0]* TRGCNT count 000: TRGCNT counts the internal clock clock select 001: TRGCNT counts the internal clock /2 010: TRGCNT counts the internal clock /4 011: TRGCNT counts the internal clock /8 100: TRGCNT counts the internal clock /32 101: TRGCNT counts the TCLKA pin input 110: TRGCNT counts the internal clock /40 111: TRGCNT counts the TCLKB pin input R/W [Legend] X: Don't care. Note: * If the internal /40 clock is selected, the high-speed on-chip oscillator must be operating. As long as the internal 40 clock is selected, do not stop the high-speed onchip oscillator. When the counter clock is switched over, the counter should be halted. When the internal 40 clock is selected, restrictions on access to registers are applied. For details, see section 18.4, Usage Note. (1) Restrictions on Access to Registers when Internal 40 Clock is Selected as Counter Clock. * CKEG1 bit and CLEG0 bit (external clock detection edge select) Selects an edge of the external clock to be detected. When phase counting mode is used, the phase counting operation is performed regardless of the CKEG[1:0] setting. * TPSC2 bit to TPSC0 bit (TRGCNT count clock select) The settings are invalid in phase counting mode. Rev. 1.00 Oct. 03, 2008 Page 633 of 962 REJ09B0465-0100 Section 18 Timer RG 18.2.4 Timer RG I/O Control Register (TRGIOR) Address: Bit: H'FF0649 b7 BUFB b6 IOB2 0 0 b5 IOB[1:0] 0 b4 b3 BUFA 0 b2 IOA2 0 0 b1 IOA[1:0] 0 b0 Value after reset: 0 Bit 7 6 5, 4 Symbol BUFB IOB2 IOB[1:0] Bit Name BRB function select GRB function select GRB I/O function select Description 0: BRB does not function as the GRB buffer register. 1: BRB functions as the GRB buffer register. 0: GRB is used as a compare match register. 1: GRB is used as an input capture register. When IOB2 = 0, 00: Disables pin output at a compare match. 01: Outputs 0 to the TGIOB pin at a GRB compare match. 10: Outputs 1 to the TGIOB pin at a GRB compare match. 11: Toggles the output to the TGIOB pin at a GRB compare match. When IOB2 = 1, 00: Input capture to GRB at the rising edge of the TGIOB pin. 01: Input capture to GRB at the falling edge of the TGIOB pin. 1X: Input capture to GRB at the rising and falling edges of the TGIOB pin. R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 634 of 962 REJ09B0465-0100 Section 18 Timer RG Bit 3 2 1, 0 Symbol BUFA IOA2 IOA[1:0] Bit Name BRA function select GRA function select GRA I/O function select Description 0: BRA does not function as the GRA buffer register. 1: BRA functions as the GRA buffer. 0: GRA is used as a compare match register. 1: GRA is used as an input capture register. When IOA2 = 0, 00: Disables pin output at a compare match. 01: Outputs 0 to the TGIOA pin at a GRA compare match. 10: Outputs 1 to the TGIOA pin at a GRA compare match. 11: Toggles the output to the TGIOA pin at a GRA compare match. When IOA2 = 1, 00: Input capture to GRA at the rising edge of the TGIOA pin. 01: Input capture to GRA at the falling edge of the TGIOA pin. 1X: Input capture to GRA at the rising and falling edges of the TGIOA pin. R/W R/W R/W R/W [Legend] X: Don't care. Rev. 1.00 Oct. 03, 2008 Page 635 of 962 REJ09B0465-0100 Section 18 Timer RG 18.2.5 Timer RG Status Register (TRGSR) Address: H'FF064A Bit: b7 b6 b5 b4 DIRF 0 b3 OVF 0 b2 UDF 0 b1 IMFB 0 b0 IMFA 0 Value after reset: 1 1 1 Bit Symbol Bit Name Reserved Count direction flag Overflow flag Description These bits are read as 1. The write value should be 1. 0: TRGCNT is decremented. 1: TRGCNT is incremented. [Setting condition] * * When TRGCNT overflows from H'FFFF to H'0000 When OVF is read when OVF = 1, then 0 is written to. [Clearing condition] R/W R R/W 7 to 5 4 3 DIRF OVF 2 UDF Underflow flag [Setting condition] * * When TRGCNT underflows from H'0000 to H'FFFF When UDF is read when UDF = 1, then 0 is written to. [Clearing condition] UDF is valid when phase counting mode is used (MDF in TRGMDR is 1). R/W 1 IMFB Input capture/ [Setting conditions] compare * TRGCNT = GRB when GRB functions as an output match flag B compare register * The TRGCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register When the DTC is activated by a IMFB interrupt, and the DISEL bit in MRB of the DTC is 0. When IMFB is read when IMBF = 1, then 0 is written to. R/W [Clearing condition] * * Rev. 1.00 Oct. 03, 2008 Page 636 of 962 REJ09B0465-0100 Section 18 Timer RG Bit 0 Symbol IMFA Bit Name Description R/W R/W Input capture/ [Setting conditions] compare * TRGCNT = GRA when GRA functions as an output match flag A compare register * The TRGCNT value is transferred to GRA by an input capture signal when GRA functions as an input capture register When the DTC is activated by an IMFA interrupt, and the DISEL bit in MRB of the DTC is 0. When IMFA is read when IMAF = 1, then 0 is written to. [Clearing condition] * * 18.2.6 Timer RG Interrupt Enable Register (TRGIER) TRGIER is a register that controls interrupt requests of timer RG. Address: H'FF064B Bit: b7 b6 b5 b4 b3 OVIE 0 b2 UDIE 0 b1 IMIEB 0 b0 IMIEA 0 Value after reset: 1 1 1 1 Bit Symbol Bit Name Reserved Overflow interrupt enable Underflow interrupt enable Input capture/ compare match B enable Input capture/ compare match A enable Description These bits are read as 1. The write value should always be 1. 0: Interrupt by the OVF flag is disabled. 1: Interrupt by the OVF flag is enabled. 0: Interrupt by the UDF flag is disabled. 1: Interrupt by the UDF flag is enabled. 0: Interrupt by the IMFB flag is disabled. 1: Interrupt by the IMFB flag is enabled. 0: Interrupt by the IMFA flag is disabled. 1: Interrupt by the IMFA flag is enabled. R/W R/W R/W R/W 7 to 4 3 2 1 OVIE UDIE IMIEB 0 IMIEA R/W Rev. 1.00 Oct. 03, 2008 Page 637 of 962 REJ09B0465-0100 Section 18 Timer RG 18.2.7 Timer RG Counter (TRGCNT) Address: H'FF0640 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGCNT is a 16-bit readable/writable register that performs count operation with an input clock. The input clock is selected by bits TPSC2 to TPSC0 in TRGCR. TRGCNT is incremented or decremented in phase counting mode and is only incremented in other modes. TRGCNT can be cleared to H'0000 by a compare match with the relevant GRA or GRB or by an input capture to GRA or GRB (counter clearing function). When TRGCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TRGSR is set to 1. When TRGCNT underflows (changes from H'0000 to H'FFFF), the UDF flag in TRGSR is set to 1. TRGCNT must always be read from or written to in units of 16 bits; 8-bit accesses are not allowed. TRGCNT is initialized to H'0000 by a reset. Rev. 1.00 Oct. 03, 2008 Page 638 of 962 REJ09B0465-0100 Section 18 Timer RG 18.2.8 General Registers A and B (GRA, GRB), GRA and GRB Buffer Registers (BRA, BRB) GRA Address: H'FF0642 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GRB Address: H'FF0644 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BRA Address: H'FF064C Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BRB Address: H'FF064E Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Each of GRA and GRB is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected with TRGIOR. When a general register is used as an output-compare register, its value is constantly compared with the TRGCNT value. When the two values match (a compare match), the corresponding flag (the IMFA or IMFB bit) in TRGSR is set to 1. A compare match output can be selected in TRGIOR. When a general register is used as an input-capture register, an external input-capture signal is detected and the current TRGCNT value is stored in the general register. The corresponding flag (the IMFA or IMFB bit) in TRGSR is set to 1. The edge of the input-capture signal is selected in TRGIOR. The setting of TRGIOR is ignored in PWM mode. Rev. 1.00 Oct. 03, 2008 Page 639 of 962 REJ09B0465-0100 Section 18 Timer RG BRA and BRB can be used as buffer registers of GRA and GRB, respectively, by setting BUFA and BUFB in TRGIOR. For example, when GRA is set as an output-compare register and BRA is set as the buffer register for GRA, the value in TRGCNT is sent to GRA whenever compare match A is generated. When GRA is set as an input-capture register and BRA is set as the buffer register for GRA, the value in TRGCNT is transferred to GRA and the value in GRA is transferred to the buffer register BRA whenever an input capture is generated. General registers and buffer registers must be written or read in 16-bit units. General registers are set as output compare registers and initialized to H'FFFF by a reset. Rev. 1.00 Oct. 03, 2008 Page 640 of 962 REJ09B0465-0100 Section 18 Timer RG 18.3 Operation Timer RG has the following operating modes. * Timer mode (the waveform output function by a compare match, and the input-capture function) * PWM mode * Phase counting mode The TGIOA and TGIOB pins indicate the functions by each register setting. * TGIOA pin Register Name PMR PCR TRGMDR TRGIOR PCR PWM X X X 0 1 0 1 0 0 X X IOA2 to IOA0 Function XXX 001, 01X 1XX XXX XXX PWM mode waveform output Timer mode waveform output (output compare function) Timer mode (input capture function) General output port General input port Bit Name PMR Setting values 1 [Legend] X: Don't care. Note: In timer mode (input capture function), do not select the relevant I/O pin to be an output in the port control register. Rev. 1.00 Oct. 03, 2008 Page 641 of 962 REJ09B0465-0100 Section 18 Timer RG * TGIOB pin Register Name Bit Name Setting values PMR PCR TRGMDR TRGIOR PMR PCR PWM 1 X X 0 1 0 X X X X IOB2 to IOB0 001, 01X 1XX XXX XXX Function Timer mode waveform output (output compare function) Timer mode (input capture function) General output port General input port [Legend] X: Don't care. Note: In timer mode (input capture function), do not select the relevant I/O pin to be an output in the port control register. 18.3.1 Timer Mode TRGCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each of GRA and GRB can be used as an input capture register or output compare register. (1) Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. (a) Example of setting procedure for waveform output by compare match Figure 18.2 shows an example of the setting procedure for waveform output by a compare match. Rev. 1.00 Oct. 03, 2008 Page 642 of 962 REJ09B0465-0100 Section 18 Timer RG Output selection Select waveform output mode [1] [1] Select 0 output, 1 output, or toggle output for compare match output by means of TRGIOR. When waveform output mode is selected, the port functions for compare-match output (TGIOA, TGIOB). [2] Set the timing for compare match generation in GRA/GRB. [3] Set the STR bit in TRGMDR to 1 to start the TRGCNT count operation. Set output timing [2] Start counting [3] Figure 18.2 Example of Setting Procedure for Waveform Output by Compare Match Table 18.3 Initial Output Values until the First Compare Match Occurs Pin TGIOA TGIOB Note: * 0 is Output by Compare Match 1 1 1 is Output by Compare Match 0 0 Output is Toggled by Compare Match 0* 0* When the initial toggled output immediately after release from the reset state is selected. In case where switching was from another output, the output value is that which preceded the switch. Rev. 1.00 Oct. 03, 2008 Page 643 of 962 REJ09B0465-0100 Section 18 Timer RG (b) Examples of waveform output operation Figure 18.3 shows an example of 0 output/1 output. In this example, TRGCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TRGCNT value H'FFFF GRB GRA H'0000 No change TGIOB TGIOA No change No change No change 1 output 0 output Time Figure 18.3 Example of 0 Output/1 Output Operation Figure 18.4 shows an example of toggle output. In this example TRGCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TRGCNT value Counter cleared by GRB compare match H'FFFF GRB GRA H'0000 Time Toggle output Toggle output TGICBO TGIOA Figure 18.4 Example of Toggle Output Operation Rev. 1.00 Oct. 03, 2008 Page 644 of 962 REJ09B0465-0100 Section 18 Timer RG (c) Output compare output timing A compare match signal is generated in the final state in which TRGCNT and GR match (the point at which the count value matched by TRGCNT is updated). When a compare match signal is generated, the output value set in TRGIOR is output at the output compare output pin (TGIOA, TGIOB). After a match between TRGCNT and GR, the compare match signal is not generated until the TRGCNT input clock is generated. Figure 18.5 shows output compare output timing. TRGCNT input clock N N+1 TRGCNT GRA , GRB N Compare match signal TGIOA, TGIOB Figure 18.5 Output Compare Output Timing (2) Input Capture Function The TRGCNT value can be transferred to GR on detection of the input-capture/output-compare pin (TGIOA, TGIOB) input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. The pulse width and cycle period can be measured using the input capture function. Rev. 1.00 Oct. 03, 2008 Page 645 of 962 REJ09B0465-0100 Section 18 Timer RG (a) Example of setting procedure for input capture operation Figure 18.6 shows an example of the setting procedure for input capture operation. Input selection Select input-capture input [1] [1] Designate GR as an input capture register by means of TRGIOR, and select the input capture signal input edge (rising edge, falling edge, or both edges). [2] Set the STR bit in TRGMDR to 1 to start the TRGCNT count operation. Start counting [2] Figure 18.6 Example of Setting Procedure for Input Capture Operation Rev. 1.00 Oct. 03, 2008 Page 646 of 962 REJ09B0465-0100 Section 18 Timer RG (b) Example of input capture operation Figure 18.7 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TGIOA pin input capture input edge, falling edge has been selected as the TGIOB pin input capture input edge, and counter clearing by GRB input capture has been designated for TRGCNT. TRGCNT value H'0180 H'0160 H'0005 H'0000 TGIOB Time TGIOA GRA H'0005 H'0160 GRB H'0180 Figure 18.7 Example of Input Capture Operation (c) Input capture signal timing Rising edge, falling edge, or both edges can be selected as the detection edge for input capture with TRGIOR. Figure 18.8 shows input capture signal timing when the falling edge has been selected. The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. Rev. 1.00 Oct. 03, 2008 Page 647 of 962 REJ09B0465-0100 Section 18 Timer RG Input-capture input Input capture signal TRGCNT N-1 N N+1 N+2 GRA, GRB N Figure 18.8 Input Capture Input Signal Timing 18.3.2 PWM Mode In PWM mode, the PWM waveform is output from the TGIOA output pin by using GRA and GRB as a pair. When an output pin is set for PWM mode, the TRGIOR output setting is ignored. The high level output timing for PWM waveform is set in GRA and the low level output timing in GRB. Designating GRA or GRB compare match as the TRGCNT counter clearing source enables outputting a PWM waveform in the range of 0% to 100% duty cycle from the TGIOA pin. The correspondence between PWM output pins and registers is shown in table 18.4. When the same value is set in GRA and GRB, the output value does not change even if a compare match occurs. Table 18.4 PWM Output Pins and Registers Output Pin TGIOA TGIOB Output 1 GRA Output 0 GRB Functions as general I/O port Rev. 1.00 Oct. 03, 2008 Page 648 of 962 REJ09B0465-0100 Section 18 Timer RG (1) Example of PWM Mode Setting Procedure Figure 18.9 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] Select counter clearing source [2] [1] Select the counter clock with bits TPSC2 to TPSC0 in TRGCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TRGCR. [2] Use bits CCLR1 and CCLR0 in TRGCR to select the counter clearing source. [3] Set the 1-output timing for the output PWM waveform with GRA. [4] Set the 0-output timing for the output PWM waveform with GRB. [5] Select the PWM mode with the PWM bit in TRGMDR. When PWM mode is set, GRA and GRB are used as output compare registers for setting 1-output/0-output for PWM output waveform, regardless of the TRGIOR setting. At this time, the TGIOA pin is automatically designated as a PWM output pin and the TGIOB pin is used as a general I/O for the relevant port. [6] Set the STR bit in TRGMDR to 1 to start the count operation. Set GRA [3] Set GRB [4] Set PWM mode [5] Start counting [6] Figure 18.9 Example of PWM Mode Setting Procedure (2) Examples of PWM Mode Operation Figure 18.10 shows examples of PWM mode operation. When PWM mode is set, the TGIOA pin is automatically set as an output pin. The TGIOA pin outputs 1 on a GRA compare match and outputs 0 on a GRB compare match. The TGIOB pin always functions as an I/O pin for the relevant port. In the examples shown in the figure, GRA and GRB compare matches are set as the TRGCNT clearing source. The initial value of TGIOA differs according to the counter clearing source. The correspondence between counter clearing sources and initial values is shown in table 18.5. Rev. 1.00 Oct. 03, 2008 Page 649 of 962 REJ09B0465-0100 Section 18 Timer RG Table 18.5 Correspondence between Counter Clearing Sources and TGIOA Initial Values Counter Clearing Source GRA compare match GRB compare match TGIOA Initial Value 1 0 TRGCNT value GRA Counter cleared on compare match A GRB H'0000 Time TGIOA (a) Counter cleared by GRA TRGCNT value GRB Counter cleared on compare match B GRA H'0000 Time TGIOA (b) Counter cleared by GRB Figure 18.10 Example of PWM Mode Operation (1) Rev. 1.00 Oct. 03, 2008 Page 650 of 962 REJ09B0465-0100 Section 18 Timer RG Figure 18.11 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. When GRB compare match is set as the counter clearing source and the set value in GRA is greater than the value in GRB, the duty cycle of the PWM waveform is 0%. When GRA compare match is set as the counter clearing source and the set value in GRB is greater than the value in GRA, the duty cycle is 100%. Rev. 1.00 Oct. 03, 2008 Page 651 of 962 REJ09B0465-0100 Section 18 Timer RG TRGCNT value GRB Counter cleared on compare match B GRA H'0000 Time TGIOA GRA write (a) 0% duty cycle GRA write TRGCNT value GRA Counter cleared on compare match A GRB H'0000 Time TGIOA GRB write (b) 100% duty cycle GRB write Figure 18.11 Example of PWM Mode Operation (2) Rev. 1.00 Oct. 03, 2008 Page 652 of 962 REJ09B0465-0100 Section 18 Timer RG 18.3.3 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs (TCLKA and TCLKB pins) is detected and TRGCNT is incremented/decremented accordingly. When phase counting mode is set, the TCLKA and TCLK pins function as external clock input pins and TRGCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TRGCR. (1) Example of Phase Counting Mode Setting Procedure Figure 18.12 shows an example of the phase counting mode setting procedure. Phase counting mode [1] Select phase counting mode with the MDF bit in TRGMDR. [2] Select phase counting condition by setting TRGCNTCR. Select phase counting mode [1] [3] Set the STR bit in TRGMDR to 1 to start the count operation. Set phase counting condition [2] Start counting [2] Figure 18.12 Example of Phase Counting Mode Setting Procedure Rev. 1.00 Oct. 03, 2008 Page 653 of 962 REJ09B0465-0100 Section 18 Timer RG (2) Examples of Phase Counting Mode Operation Figures 18.13 to 18.16 show examples of phase counting mode operation, and tables 18.6 to 18.9 summarize the TRGCNT increment/decrement conditions. Table 18.6 Increment/Decrement Conditions in Phase Counting Mode Operation Example 1 (TRGCNTCR = H'FF) TRGCNTCR CNTEN7 CNTEN6 CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 [Legend] : Rising edge : Falling edge Set Value 1 1 1 1 1 1 1 1 High level Low level Low level High level Low level High level Decrement TCLKA Low level High level TCLKB Operation Increment TCLKB TCLKA Increment Decrement Figure 18.13 Phase Counting Mode Operation Example 1 (TRGCNTCR = H'FF) Rev. 1.00 Oct. 03, 2008 Page 654 of 962 REJ09B0465-0100 Section 18 Timer RG Table 18.7 Increment/Decrement Conditions in Phase Counting Mode Operation Example 2 (TRGCNTCR = H'24) TRGCNTCR CNTEN7 CNTEN6 CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 [Legend] : Rising edge : Falling edge Set Value 0 0 1 0 0 1 0 0 High level Low level Low level High level Low level High level Decrement Don't care TCLKA Low level High level Increment Don't care TCLKB Operation Don't care TCLKB TCLKA Increment Decrement Figure 18.14 Phase Counting Mode Operation Example 2 (TRGCNTCR = H'24) Rev. 1.00 Oct. 03, 2008 Page 655 of 962 REJ09B0465-0100 Section 18 Timer RG Table 18.8 Increment/Decrement Conditions in Phase Counting Mode Operation Example 3 (TRGCNTCR = H'28) TRGCNTCR CNTEN7 CNTEN6 CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 [Legend] : Rising edge : Falling edge Set Value 0 0 1 0 1 0 0 0 High level Low level Low level High level Low level High level TCLKA Low level High level Increment Don't care Decrement Don't care TCLKB Operation Don't care TCLKB TCLKA Increment Decrement Figure 18.15 Phase Counting Mode Operation Example 3 (TRGCNTCR = H'28) Rev. 1.00 Oct. 03, 2008 Page 656 of 962 REJ09B0465-0100 Section 18 Timer RG Table 18.9 Increment/Decrement Conditions in Phase Counting Mode Operation Example 4 (TRGCNTCR = H'5A) TRGCNTCR CNTEN7 CNTEN6 CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 [Legend] : Rising edge : Falling edge Set Value 0 1 0 1 1 0 1 0 High level Low level Low level High level Low level High level TCLKA Low level High level TCLKB Operation Don't care Increment Don't care Increment Decrement Don't care Decrement Don't care TCLKB TCLKA Increment Decrement Figure 18.16 Phase Counting Mode Operation Example 4 (TRGCNTCR = H'5A) Rev. 1.00 Oct. 03, 2008 Page 657 of 962 REJ09B0465-0100 Section 18 Timer RG (3) Note on Phase Counting Mode In phase counting mode, the phase difference and overlap between TCLKA and TCLKB must be at least 1.5 x cycle of the system clock when bits TPSC2 to TPSC0 in TRGCR = B'0XX or B'100, and the pulse width must be at least 3 x cycle. If B'110 is selected as the value, the phase difference and overlap must be at least 1.5 x 40 cycles and the pulse width at least 3 x 40 cycles. Figure 18.17 shows the input clock conditions in phase counting mode. Phase difference TCLKA Phase difference Pulse width Pulse width TCLKB Overlap Overlap Phase difference and overlap: 1.5 states or more Pulse width: 2.5 states or more Figure 18.17 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Note: When CNTEN7 to CNTEN0 in TRGCNTCR are cleared, the counting is not performed even if an increment/decrement condition matches. 18.3.4 Buffer Operation Buffer operation differs depending on whether GR has been designated as an input capture register or a compare match register. Table 18.10 shows the register combinations used in buffer operation. Table 18.10 Register Combinations in Buffer Operation General Register GRA GRB Buffer Register BRA BRB Rev. 1.00 Oct. 03, 2008 Page 658 of 962 REJ09B0465-0100 Section 18 Timer RG (1) When GR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the general register. This operation is illustrated in figure 18.18. Compare match signal Buffer register General register Comparator TRGCNT Figure 18.18 Compare Match Buffer Operation (2) When TGR is an input capture register When input capture occurs, the value in TRGCNT is transferred to GR and the value previously held in the general register is transferred to the buffer register. This operation is illustrated in figure 18.19. Input capture signal General register Buffer register TRGCNT Figure 18.19 Input Capture Buffer Operation Rev. 1.00 Oct. 03, 2008 Page 659 of 962 REJ09B0465-0100 Section 18 Timer RG Figures 18.20 and 18.21 show the timings in buffer operation. Input capture signal TRGCNT N N+1 GRA GRB M N N+1 BRA BRB M N Figure 18.20 Buffer Operation Timing (Compare Match) Compare match signal TRGCNT N N+1 BRA BRB M GRA GRB N M Figure 18.21 Buffer Operation Timing (Input Capture) Rev. 1.00 Oct. 03, 2008 Page 660 of 962 REJ09B0465-0100 Section 18 Timer RG 18.3.5 Operation through an Event Link Using the event link controller (ELC), timer RG can be made to operate in the following ways in relation to events occurring in other modules. (1) Staring Counter Operation The start of counting operations by timer RG can be selected by ELOPC of the ELC. When the event specified by ELSR8 occur, the STR bit in TRGMDR is set to 1, which starts counting by timer RG. However, if the specified event occurs when the STR bit has already been set to 1, the event is not effective. (2) Counting Event The counting of events by timer RG can be selected by ELOPC of the ELC. When the event specified in ELSR8 occurs, event counter operation proceeds with that event as the source to drive counting, regardless of the setting of TPSC[2:0] bits in TRGCR. When the value of the counter is read, the value read out is the actual number of input events. (3) Input Capture Input capture operation of timer RG can be selected by ELOPC of the ELC. When the event specified in ELSR8 occurs, GRB captures the value of TRGCNT. When input capture operation initiated by an event link is in use, set IOB[2:0] = b'101 in the TRGIOR register of timer RG, set the STR bit in TRGMDR, and then start the counter. Since input on the TGIOB pin becomes valid at the same time, fix the input to the TGIOB pin or take other measures such as not allocating the TGIOB pin to the port in the PMC, etc. Rev. 1.00 Oct. 03, 2008 Page 661 of 962 REJ09B0465-0100 Section 18 Timer RG 18.3.6 Digital Filtering Function for Input Capture Inputs Input signals on the TGIOA and TGIOB pins can be input via the digital filters. The digital filter includes three latches connected in series and a matching detecting circuit. The input signals on the TGIOA and TGIOB pins are operated on the sampling clock specified by the DFCK1 and DFCK0 bits in TRGMDR. When outputs of the three latches match, the matching detecting circuit outputs the signal level of the input. Otherwise, the output remains unchanged. That is, when a pulse width is equal to or greater than three sampling clock cycles, the pulse is input as a signal. When a pulse width is less than three sampling clock cycles, the pulse is considered as a noise to be removed. TPSC2 to TPSC0 DFCK1 and DFCK0 TCLKB TCLKA 40 /32 /8 /4 /2 TGIOA and TGIOB input signals C D Latch , 40 C D Latch Q Q /32 /8 Sampling clock DFA and DFB IOA[1:0] and IOB[1:0] C D Latch Q D C Q Latch D C Q Latch Matching detecting circuit Selecter Edge detecting circuit Cycle of a clock specified by TPSC2 to TPSC0 or DFCK1 and DFCK0 Sampling clock TGIOA and TGIOB input signal Digital-filtered signal Signal propagation delay: 5 sampling clocks Signal change is not output unless signal levels match three times. Figure 18.22 Block Diagram of Digital Filter Rev. 1.00 Oct. 03, 2008 Page 662 of 962 REJ09B0465-0100 Section 18 Timer RG 18.4 18.4.1 Usage Note Restrictions on Access to Registers when Internal 40 Clock is Selected as Counter Clock When the internal 40 clock is selected as the counter clock (the TPSC[2:0] bits in TRGCR = 110), if any register of timer RG is to be read immediately after writing to another register in a given module, proceed with reading after having executed one NOP instruction. Write to TRGMDR. Execute NOP. Read TRGCNT. Figure 18.23 Example of Flow for Reading Immediately after Writing to a Register Rev. 1.00 Oct. 03, 2008 Page 663 of 962 REJ09B0465-0100 Section 18 Timer RG Rev. 1.00 Oct. 03, 2008 Page 664 of 962 REJ09B0465-0100 Section 19 Watchdog Timer (WDT) Section 19 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 19.1. Low-speed OCO Prescaler Prescaler TCWD Subclock Prescaler TCSRWD TMWD TICRWD TIFRWD Internal reset signal WDT interrupt Figure 19.1 Block Diagram of Watchdog Timer Rev. 1.00 Oct. 03, 2008 Page 665 of 962 REJ09B0465-0100 Internal data bus Section 19 Watchdog Timer (WDT) 19.1 Features * Selectable from fifteen clock sources Eight clocks generated by dividing : /64, /128, /256, /512, /1024, /2048, /4096, and /8192 Five clocks generated by dividing low-speed OCO clock: loco/8, loco/32, loco/128, loco/512, and loco/1024 Two clocks generated by dividing subclock: sub/4 and sub/256 When the low-speed OCO clock or subclock is selected, the WDT operates as the watchdog timer in any operating mode. * Reset signal generated on counter overflow An overflow period of 1 to 256 times the selected clock can be set. * The watchdog timer is enabled in the initial state. The watchdog timer starts operating after a reset is released. * Periodic timer function The timer counter can also be used as a periodic timer. Interrupts can be generated with a specific count value. Rev. 1.00 Oct. 03, 2008 Page 666 of 962 REJ09B0465-0100 Section 19 Watchdog Timer (WDT) 19.2 Register Descriptions The watchdog timer has the following registers. * * * * * Timer control/status register WD (TCSRWD) Timer counter WD (TCWD) Timer mode register WD (TMWD) Timer interrupt control/status register WD (TICRWD) Timer interrupt flag register WD (TIFRWD) Timer Control/Status Register WD (TCSRWD) Address: H'FFFF9A Bit: b7 B6WI Value after reset: 1 b6 TCWE 0 b5 B4WI 1 b4 TCSRWE 0 b3 TMWLOCK 0 b2 TMWI 1 b1 19.2.1 b0 1 1 Bit 7 Symbol B6WI Bit Name Bit 6 write inhibit Description 0: Writing to the TCWE bit (bit 6 in this register) is enabled. 1: Writing to the TCWE bit (bit 6 in this register) is disabled. This bit is always read as 1. R/W R/W 6 TCWE Timer counter 0: Writing to the TCWD register is disabled. WD write 1: Writing to the TCWD register is enabled. enable Before writing data to this bit, the B6WI bit must be cleared to 0. Bit 4 write inhibit 0: Writing to the TCSRWE bit (bit 4) is enabled. 1: Writing to the TCSRWE bit (bit 4) is disabled. This bit is always read as 1. R/W 5 B4WI R/W 4 TCSRWE Timer 0: Writing to TMWLOCK and TMWI (bits 3 and 2 in this R/W control/status register) is disabled. register WD 1: 0: Writing to TMWLOCK and TMWI (bits 3 and 2 in this write enable register) is enabled. Before writing data to this bit, the B4WI bit must be cleared to 0. Rev. 1.00 Oct. 03, 2008 Page 667 of 962 REJ09B0465-0100 Section 19 Watchdog Timer (WDT) Bit 3 Symbol Bit Name Description This register is write-protected when this bit is 1. Once this bit is set to 1, this bit can be cleared only by a reset. 0: Writing to the TMWD register is enabled. 1: Writing to the TMWD register is disabled. [Setting condition] * * When 1 is written to this bit Resetting [Clearing condition] R/W R/W TMWLOCK Timer mode register WD lockdown 2 TMWI Timer mode 0: Writing to the TMWD register is enabled. register write 1: Writing to the TMWD register is disabled. inhibit [Setting conditions] * * * This bit is automatically set to 1 after TMWD is written to. When 1 is written to this bit. When 0 is written to TMWI while TMWI is 1 R/W [Clearing condition] 1, 0 Reserved These bits are read as 1. The write value should always be 1. Note: TCSRWD must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value. 19.2.2 Timer Counter WD (TCWD) Address: H'FFFF98 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 0 0 0 0 0 0 0 0 TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated. TCWD is initialized to H'00. TCWD can also be used as a periodic timer. It issues an interrupt request to the CPU when the upper two bits in TCWD are B'01, B'10, or B'11 according to the TICRWD setting. Rev. 1.00 Oct. 03, 2008 Page 668 of 962 REJ09B0465-0100 Section 19 Watchdog Timer (WDT) 19.2.3 Timer Mode Register WD (TMWD) Address: H'FFFF99 Bit: b7 b6 b5 b4 b3 b2 CKS[3:0] b1 b0 Value after reset: 1 1 1 1 0 0 0 0 Bit 7 to 4 3 to 0 Symbol CKS[3:0] Bit Name Reserved Clock select Description These bits are read as 1. The write value should always be 1. 0001: Internal clock: counts on loco/32 0010: Internal clock: counts on loco/128 0011: Internal clock: counts on loco/512 0100: Internal clock: counts on loco/1024 0101: Internal clock: counts on sub/4 0110: Internal clock: counts on sub/256 0111: Clock input prohibited. 1000: Internal clock: counts on /64 1001: Internal clock: counts on /128 1010: Internal clock: counts on /256 1011: Internal clock: counts on /512 1100: Internal clock: counts on /1024 1101: Internal clock: counts on /2048 1110: Internal clock: counts on /4096 1111: Internal clock: counts on 8192 R/W 0000: Internal clock: counts on loco/8 (initial value) R/W * CK3[3:0] bits (clock select) The method by which this register is written differs from other registers. The register must be written by using the MOV instruction twice in succession. First, write the data to be loaded to TMWD in a first operation, then write a bit reversal value of the data to be loaded in a second operation. When correct operation is executed, CKS[3:0] bits are rewritten after the second write. If the first data and the second reversal data do not match, all bits are not modified. Set CK3[3:0] bits to B'0111 (clock input prohibited) to stop WDT operation. Rev. 1.00 Oct. 03, 2008 Page 669 of 962 REJ09B0465-0100 Section 19 Watchdog Timer (WDT) 19.2.4 Timer Interrupt Control Register WD (TICRWD) Address: H'FFFF9B Bit: b7 b6 b5 IWIE 0 b4 b3 b2 b1 b0 INTSEL[1:0] Value after reset: 1 1 1 1 1 1 1 Bit 7, 6 Symbol Bit Name Description R/W R/W INTSEL[1:0] WDT periodic 00: Setting prohibited interrupt 01: An interrupt is generated when the upper two bits condition in TCWD is B'01. select 10: An interrupt is generated when the upper two bits in TCWD is B'10. 11: An interrupt is generated when the upper two bits in TCWD is B'11. (Initial value) 5 IWIE WDT periodic 0: Periodic interrupt request is disabled. interrupt 1: Periodic interrupt request is enabled. enable Reserved These bits are read as 1. The write value should always be 1. R/W 4 to 0 Rev. 1.00 Oct. 03, 2008 Page 670 of 962 REJ09B0465-0100 Section 19 Watchdog Timer (WDT) 19.2.5 Timer Interrupt Flag Register WD (TIFRWD) Address: H'FFFF9C Bit: b7 IWF b6 b5 b4 b3 b2 b1 b0 Value after reset: 0 1 1 1 1 1 1 1 Bit 7 Symbol IWF Bit Name WDT periodic interrupt request flag Description 0: No periodic interrupt request 1: Periodic interrupt request is generated. [Setting condition] * When the upper two bits in the timer counter WD agree with the value set by the INTSEL[1:0] bits in TICRWD. [Clearing condition] * When 0 is written to IWF after reading IWF = 1. R/W R/W 6 to 0 Reserved These bits are read as 1. The write value should always be 1. Rev. 1.00 Oct. 03, 2008 Page 671 of 962 REJ09B0465-0100 Section 19 Watchdog Timer (WDT) 19.3 19.3.1 Operation Watchdog Timer Overflow Reset The watchdog timer is provided with an 8-bit counter. After a reset is released, TCWD starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is generated. Since TCWD is a writable counter, it starts counting from the value set in TCWD. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. When the watchdog timer is not used, write 0 simultaneously to TMWLOCK and TMWI in TCSRWD while the TCSRWE bit is 1 and set CKS[3:0] in TMWD to B'0111 (clock input prohibited). Figure 19.2 shows an example of watchdog timer operation. Example: With 30-ms overflow period when = 4 MHz (selects /8192 for clock source) 4 x 106 8192 Therefore, 256 - 15 = 241 (H'F1) is set in TCW. x 30 x 10-3 = 14.6 H'FF TCWD overflow H'F1 TCWD count value H'00 H'F1 written to TCWD H'F1 written to TCWD Reset generated Internal reset signal Figure 19.2 Watchdog Timer Operation Example Rev. 1.00 Oct. 03, 2008 Page 672 of 962 REJ09B0465-0100 Section 19 Watchdog Timer (WDT) 19.3.2 Watchdog Timer Setting Flow The watchdog timer should be set using the procedure shown in figure 19.3. Reset released Clear B4WI to 0 and set TCSRWE to 1 in TCSRWD. After reset is released, the WDT starts counting with loco/8. [1][2]Set TMWD to write-enable. [3][4]The clock source is changed. In this flowchart, the clock is changed to loco/32. In [3], the set value is continuously written to with the MOV instruction. In [4], the bit-set value is bit-inverted and written. [5][6]When the watchdog timer is not used, clock input is set to be disabled. In [5], the set value is continuously written to with the MOV instruction. In [6], the bitset value is bit-inverted and written. [7] [3] Set TMWDto H'F7 [5] [8] After TMWD is written to, the TMWI bit in TCSRWD is automatically set to 1. To lock down TMWD, set the TMWLOCK bit in TCSRWD to 1. [1] Clear TMWI in TCSRWD to 0. [2] Is WDT used? Y N Is clock source changed? Y Set TMWD to H'F1 N Set TMWD to H'FE [4] Set TMWD to H'F8 [6] Set TMWI in TCSRWD to 1. [7] Is TMD locked down? Y TMWLOCK in TCSRWD 1. N [8] End Figure 19.3 Watchdog Timer Setting Flow Rev. 1.00 Oct. 03, 2008 Page 673 of 962 REJ09B0465-0100 Section 19 Watchdog Timer (WDT) 19.3.3 Watchdog Timer Periodic Interrupt When the INTSEL[1:0] bits in TICRWD are set and the timer WD counter reaches the set value, the IWF bit in TIRWD is set to 1. At this time, if the IWIE bit in TICRWD is 1, an interrupt request is generated. Figure 19.4 shows the interrupt generation timing when INTSEL is B'01. TCWD H'3F H'40 Interrupt request flag setting signal IWF Figure 19.4 Periodic Interrupt Generation Timing (INTSEL = B'01) Rev. 1.00 Oct. 03, 2008 Page 674 of 962 REJ09B0465-0100 Section 19 Watchdog Timer (WDT) 19.4 19.4.1 Usage Notes Notes on System Design While the watchdog timer is a useful function that restores the LSI to normal condition if the system runs erratically for some reason, the watchdog timer may fail to be reset properly in situations such as the perpetuation of an endless loop in a specific programming routine in which a counter setting operation is executed. Also, there is a possibility of the watchdog timer not being reset properly despite an erratic system condition if an interrupt is enabled and a counter value is set within the interrupt processing. These notes should be taken into consideration in the system design phases. 19.4.2 Notes on Stopping the Watchdog Timer or Switching the Count Clock The MSTWDT bit in MSTCR1 is set to 1 after release from a reset, but the watchdog timer will operate since loco/8 is selected as the counter clock. (and, since the WDT is in module standby mode, access to the registers is disabled). To stop the watchdog timer or switch the count clock, proceed after releasing the WDT from module standby by clearing the MSTWDT bit in MSTCR1 to 0. Rev. 1.00 Oct. 03, 2008 Page 675 of 962 REJ09B0465-0100 Section 19 Watchdog Timer (WDT) Rev. 1.00 Oct. 03, 2008 Page 676 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Section 20 Serial Communication Interface 3 (SCI3, IrDA) This LSI includes a serial communication interface 3 (SCI3), which has three independent channels. The SCI3 can handle both asynchronous and clocked synchronous serial communication. In asynchronous mode, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). Table 20.1 shows the SCI3 channel configuration and figure 20.1 shows a block diagram of the SCI3. Since pin functions are identical for each of the three channels (SCI3, SCI3_2, and SCI3_3), separate explanations are not given in this section. 20.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception. * On-chip baud rate generator allows any bit rate to be selected * External clock or on-chip baud rate generator can be selected as a transfer clock source. * Six interrupt sources Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. The DTC can be activated by the transmit-data-empty interrupt and receive-data-full interrupt sources. Asynchronous mode * * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RXD pin level directly in the case of a framing error Rev. 1.00 Oct. 03, 2008 Page 677 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Clocked synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors Rev. 1.00 Oct. 03, 2008 Page 678 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Table 20.1 Channel Configuration Channel Channel 1 Abbreviation Pin SCI3* 1 Register SMR BRR SCR3 TDR SSR RDR RSR TSR SPMR Register Address H'FF0550 H'FF0551 H'FF0552 H'FF0553 H'FF0554 H'FF0555 H'FF0556 H'FF0558 H'FF0559 H'FF055A H'FF055B H'FF055C H'FF055D H'FF055E H'FF05DE H'FF0560 H'FF0561 H'FF0562 H'FF0563 H'FF0564 H'FF0565 H'FF0566 Noise Canceler Available SCK3 RXD TXD Channel 2 SCI3_2* 2 SCK3_2 RXD_2/IrRxD TXD_2/IrTxD SMR_2 BRR_2 SCR3_2 TDR_2 SSR_2 RDR_2 RSR_2 TSR_2 SPMR IrCR Available Channel 3 SCI3_3 SCK3_3 RXD_3 TXD_3 SMR_3 BRR_3 SCR3_3 TDR_3 SSR_3 RDR_3 RSR_3 TSR_3 SPMR_3 Available Notes: 1. Channel 1 of the SCI3 is used in on-board programming mode by boot mode. 2. SCI3_2 provides IrDA (Infrared Data Association) communication waveform transmission/reception according IrDA standard version 1.0. Rev. 1.00 Oct. 03, 2008 Page 679 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) SCK3 External clock Baud rate generator Internal clock (/64, /16, /4, ) BRC Clock BRR Transmit/receive control circuit SCR3 SSR TXD TSR TDR RXD SPMR RSR RDR Interrupt request (TEI, TXI, RXI, ERI) (1) SCI3 and SCI3_3 SCK3 External clock Baud rate generator Internal clock (/64, /16, /4, ) BRC Clock BRR SMR SCR3 SSR Internal data bus Transmit/receive control circuit TSR TDR RSR TxD_2/IrTxD RXD_2/IrRxD SPMR IrCR RDR Internal data bus SMR Interrupt request (TEI, TXI, RXI, ERI) (2) SCI3_2 Figure 20.1 Block Diagram of SCI3 Rev. 1.00 Oct. 03, 2008 Page 680 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Table 20.2 shows the SCI3 pin configuration. Table 20.2 Pin Configuration Channel 1 Pin Name SCK3 RXD TXD 2 SCK3_2 RXD_2/IrRxD TXD_2/IrTxD 3 SCK3_3 RXD_3 TXD_3 I/O I/O Input Output I/O Input Output I/O Input Output Function Clock input/output for channel 1 Receive data input for channel 1 Transmit data output for channel 1 Clock input/output for channel 2 Receive data input for channel 2/IrDA receive data input Transmit data output for channel 2/IrDA transmit data output Clock input/output for channel 3 Receive data input for channel 3 Transmit data output for channel 3 Rev. 1.00 Oct. 03, 2008 Page 681 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2 Register Descriptions The SCI3 has the following registers. Channel 1 * Receive shift register (RSR) * Receive data register (RDR) * Transmit shift register (TSR) * Transmit data register (TDR) * Serial mode register (SMR) * Serial control register (SCR3) * Serial status register (SSR) * Bit rate register (BRR) * Sampling mode register (SPMR) Channel 2 * Receive shift register (RSR) * Receive data register (RDR) * Transmit shift register (TSR) * Transmit data register (TDR) * Serial mode register (SMR) * Serial control register (SCR3) * Serial status register (SSR) * Bit rate register (BRR) * Sampling mode register (SPMR) * IrDA control register (IrCR) Channel 3 * Receive shift register (RSR) * Receive data register (RDR) * Transmit shift register (TSR) * Transmit data register (TDR) * Serial mode register (SMR) * Serial control register (SCR3) * Serial status register (SSR) * Bit rate register (BRR) * Sampling mode register (SPMR) Rev. 1.00 Oct. 03, 2008 Page 682 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2.1 Receive Shift Register (RSR) Address: Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 20.2.2 Receive Data Register (RDR) Address: H'FF0555, H'FF055D, H'FF0565 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 0 0 0 0 0 0 0 0 RDR is an 8-bit register that stores received data. When the SCI3 has received one frame of data, it transfers the received data from RSR to RDR, where it is stored. After this, RSR is receiveenabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. 20.2.3 Transmit Shift Register (TSR) Address: Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first transfers transmit data from TDR to TSR automatically, then sends the data that starts from the LSB to the TXD pin. TSR cannot be directly accessed by the CPU. Rev. 1.00 Oct. 03, 2008 Page 683 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2.4 Transmit Data Register (TDR) Address: H'FF0553, H'FF055B, H'FF0563 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous transmission. If the next transmit data has already been written to TDR during transmission of one-frame data, the SCI3 transfers the written data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF. 20.2.5 Serial Mode Register (SMR) Address: H'FF0550, H'FF0558, H'FF0560 Bit: b7 COM Value after reset: 0 b6 CHR 0 b5 PE 0 b4 PM 0 b3 STOP 0 b2 MP 0 0 b1 CKS[1:0] 0 b0 Bit 7 6 Symbol COM CHR Bit Name Description R/W R/W R/W Communication mode 0: Asynchronous mode 1: Clocked synchronous mode Character length (Enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. 5 PE Parity enable (Enabled only in asynchronous mode) 0: Parity bit addition and parity check are disabled. 1: The parity bit is added in transmission and the parity bit is checked in reception. R/W Rev. 1.00 Oct. 03, 2008 Page 684 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Bit 4 Symbol PM Bit Name Parity mode Description (Enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. R/W R/W 3 STOP Stop bit length (Enabled only in asynchronous mode) 0: 1 stop bit 1: 2 stop bits R/W 2 MP Multiprocessor mode 0: The multiprocessor communication function is R/W disabled. 1: The multiprocessor communication function is enabled*2 1 0 CKS1 CKS0 Clock select 0 and 1 00: clock (n = 0) 01: /4 clock (n = 1) 10: /14 clock (n = 2) 11: /64 clock (n = 3) R/W Notes: 1. The SMR value is retained when (module) standby mode is entered. 2. In clocked synchronous mode, clear this bit to 0. * STOP bit (stop bit length) Selects the stop bit length in transmission. For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character. * MP bit (multiprocessor mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and PM bit settings are invalid in multiprocessor mode. * CKS1 bit and CKS0 bit (clock select 1, 0) These bits select the clock source for the baud rate generator. For the relationship between the bit rate register setting and the baud rate, see section 20.2.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 20.2.8, Bit Rate Register (BRR)). Rev. 1.00 Oct. 03, 2008 Page 685 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2.6 Serial Control Register 3 (SCR3) Address: H'FF0552, H'FF055A, H'FF0562 Bit: b7 TIE b6 RIE 0 b5 TE 0 b4 RE 0 b3 MPIE 0 b2 TEIE 0 0 b1 CKE[1:0] 0 b0 Value after reset: 0 Bit 7 6 5 4 3 Symbol TIE RIE TE RE MPIE Bit Name Transmit interrupt enable Description 0: The TXI interrupt request is disabled. 1: The TXI interrupt request is enabled. R/W R/W R/W R/W R/W R/W Receive interrupt 0: RXI and ERI interrupt requests are disabled. enable 1: RXI and ERI interrupt requests are enabled. Transmit enable 0: Transmission is disabled. 1: Transmission is enabled. Receive enable Multiprocessor interrupt enable 0: Reception is disabled. 1: Reception is enabled. (Enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 20.5, Multiprocessor Communication Function. 2 TEIE Transmit end interrupt enable 0: The TEI interrupt request is disabled. 1: The TEI interrupt request is enabled. R/W Rev. 1.00 Oct. 03, 2008 Page 686 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Bit 1, 0 Symbol CKE1 CKE0 Bit Name Description R/W R/W Clock enable 0 Selects the clock source. and 1 Asynchronous mode: 00: On-chip baud rate generator 01: On-chip baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK3 pin. 10: External clock A clock with a frequency 16 times the bit rate should be input from the SCK3 pin. 11:Reserved Clocked synchronous mode: 00: On-chip clock (The SCK3 pin functions as clock output.) 01: Reserved 10: External clock (The SCK3 pin functions as clock input.) 11: Reserved Notes: 1. The TE and RE bits are reset and the other bits are retained when (module) standby mode is entered. 2. For details on interrupt requests, see section 20.8, Interrupt Requests. Rev. 1.00 Oct. 03, 2008 Page 687 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2.7 Serial Status Register (SSR) Address: H'FF0554, H'FF055C, H'FF0564 Bit: b7 TDRE b6 RDRF 0 b5 OER 0 b4 FER 0 b3 PER 0 b2 TEND 1 b1 MPBR 0 b0 MPBT 0 Value after reset: 1 Bit 7 Symbol Bit Name TDRE Description R/W R/W Transmit [Setting conditions] data register * When the TE bit in SCR3 is 0 empty flag * When data is transferred from TDR to TSR [Clearing conditions] * * * When the CPU writes 0 after reading TDRE = 1. When the CPU writes transmit data to TDR. When the DTC transfers data to TDR with a TXI interrupt request and the DTC settings satisfy the flag clearing conditions. 6 RDRF Receive [Setting condition] data register * When reception ends normally and receive data is full flag transferred from RSR to RDR [Clearing conditions] * * * When the CPU writes 0 after reading RDRF = 1. When the CPU reads data from RDR. When the DTC transfers data from RDR with an RXI interrupt request and the DTC settings satisfy the flag clearing conditions. * R/W 5 OER Overrun error flag [Setting condition] * * When an overrun error occurs in reception When the CPU writes 0 after reading OER = 1. [Clearing condition] R/W Rev. 1.00 Oct. 03, 2008 Page 688 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Bit 4 Symbol Bit Name FER Description R/W R/W Framing error [Setting condition] flag * When a framing error occurs in reception [Clearing condition] * When the CPU writes 0 after reading FER = 1. 3 PER Parity error flag [Setting condition] * * When a parity error is detected during reception When the CPU writes 0 after reading PER = 1. [Clearing condition] R/W 2 TEND Transmit end flag [Setting conditions] * * When the TE bit in SCR3 is 0 When TDRE = 1 at transmission of the last bit of a transmit character When 0 is written to TDRE after reading TDRE = 1 When the transmit data is written to TDR R/W [Clearing conditions] * * 1 MPBR Multiprocessor Stores the multiprocessor bit in the receive character data. bit receive When the RE bit in SCR3 is cleared to 0, its state is retained. Multiprocessor Specifies the multiprocessor bit value to be added to the bit transfer transmit character data. R/W 0 Note: MPBT * R/W The DTC clears the peripheral module flags when all of the following three conditions are satisfied: 1. The DISEL bit is 0. 2. The value in the transfer counter (count register CRA in normal and repeat modes or count register CRB in block mode) is not 0. 3. A chain transfer is not used. Rev. 1.00 Oct. 03, 2008 Page 689 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2.8 Bit Rate Register (BRR) Address: H'FF0551, H'FF0559, H'FF0561 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 20.3 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 SMR in asynchronous mode. Table 20.4 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 20.3 and 20.4 are values in active (highspeed) mode. Table 20.5 shows of the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 20.5 are values in active (high-speed) mode. The N setting in BRR and error for other operating frequencies and bit rates can be obtained by the following formulas: Note: The BRR value is retained in (module) standby mode. [Asynchronous Mode] N= 64 x 22n-1 x B x 106 -1 x 106 Error (%) = (N + 1) x B x 64 x 22n-1 -1 x 100 [Clocked Synchronous Mode] N= 8 x 22n-1 x B x 106 -1 [Legend] B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n: CSK1 and CSK0 settings in SMR (0 n 3) Rev. 1.00 Oct. 03, 2008 Page 690 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Table 20.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency (MHz) 4 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 0.00 8.51 n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 Operating Frequency (MHz) 6.144 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 7.3728 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 Rev. 1.00 Oct. 03, 2008 Page 691 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Operating Frequency (MHz) 10 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.888 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 Operating Frequency (MHz) 14.7456 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 114 233 114 233 114 58 28 17 14 18 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.96 1.02 0.00 -2.34 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 [Legend] : A setting is available but error occurs. Rev. 1.00 Oct. 03, 2008 Page 692 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Table 20.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 230400 250000 307200 312500 n 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 (MHz) 12 12.288 14 14.7456 16 17.2032 18 20 Maximum Bit Rate (bit/s) 375000 384000 437500 460800 500000 537600 562500 625000 n 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 Rev. 1.00 Oct. 03, 2008 Page 693 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Table 20.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M 2.5M 5M [Legend] Blank: No setting is available. : A setting is available but error occurs. *: Continuous transfer is not possible. 2 2 1 1 0 0 0 0 0 0 0 0 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0* 1 1 0 0 0 0 0 0 0 249 124 249 99 49 24 9 4 0* 3 3 2 2 1 1 0 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 1 1 0 0 0 0 0 0 224 179 89 44 17 8 4 2 1 1 0 0 0 0 0 0 0 0 124 249 124 199 99 49 19 9 4 1 0* 4 n N n 8 N n 10 N n 16 N n 18 N n 20 N Rev. 1.00 Oct. 03, 2008 Page 694 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2.9 Sampling Mode Register (SPMR) Address: H'FF0556, H'FF055E, H'FF0566 Bit: b7 b6 b5 b4 b3 b2 NFEN 0 b1 b0 Value after reset: 1 1 1 1 1 1 1 Bit 7 to 3 2 Symbol NFEN Bit Name Reserved Description R/W These bits are read as 1. The write value should be 1. R/W Noise cancellation 0: The noise cancellation function is invalid for function select the RXD pin input. 1: The noise cancellation function is valid for the RXD pin input (when the COM bit in SMR is 0). 1, 0 Reserved These bits are read as 1. The write value should be 1. Note: The SPMR value is retained in (module) standby mode. * NFEN bit (noise cancellation function select) Performs noise cancellation for the RXD pin input when the COM bit in SMR is 0 and NFEN bit is 1. 20.2.10 IrDA Control Register (IrCR) Address: H'FF05DE Bit: b7 IrE Value after reset: 0 0 b6 b5 IrCK[2:0] 0 0 b4 b3 IrTXINV 0 b2 IrRXINV 0 b1 b0 1 1 Rev. 1.00 Oct. 03, 2008 Page 695 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Bit 7 Symbol IrE Bit Name IrDA enable Description 0: The TXD_2/IrTXD and RXD_2/IrRXD pins function as the TXD_2 and RXD_2 pins. 1: The TXD_2/IrTXD and RXD_2/IrRXD pins function as the IrTXD and IrRXD pins. R/W R/W 6 to 4 IrCK[2:0] IrDA clock select 000: Bit rate x 3/16 2 to 0 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 R/W 3 IrTXINV IrTX data polarity 0: Transmit data is output from IrTXD as is. inversion 1: Transmit data is inverted to be output from IrTXD. IrRX data polarity 0: IrRXD input is used for receive data as is. inversion 1: IrRXD input is inverted to be used for receive data. Reserved R/W 2 IrRXINV R/W 1, 0 These bits are read as 1. The write value should be 1. Note: The IrCR value is retained in (module) standby mode. * IrE bit (IrDA enable) Selects the SCI3_2 I/O pin function between the usual serial function and IrDA function. * IrCK[2:0] bit (IrDA clock select 2 to 0) Sets the high pulse width for IrTXD output pulse encoding when the IrDA function is * IrTXINV bit (IrTX data polarity inversion) Sets to invert the logic level of the IrTXD output. When inversion is specified, the high pulse width set with IrCR[2:0] is handled as low pulse width. * IrRXINV bit (IrRX data polarity inversion) Sets to invert the logic level of the IrRXD input. When inversion is specified, the high pulse width set with IrCR[2:0] is handled as low pulse width. Rev. 1.00 Oct. 03, 2008 Page 696 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.3 Operation in Asynchronous Mode Figure 20.2 shows the general format for asynchronous communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex. Both the transmitter and the receiver also have a doublebuffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. LSB Serial Start data bit Transmit/receive data MSB Parity bit Stop bit 1 Mark state 1 bit 7 or 8 bits 1 bit or none 1 or 2 bits One unit of transfer data (character or frame) Figure 20.2 Data Format in Asynchronous Communication 20.3.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3's transfer clock, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the clock frequency should be 16 times the bit rate used. When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 20.3. Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 character (frame) Figure 20.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 1.00 Oct. 03, 2008 Page 697 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.3.2 SCI3 Initialization Figure 20.4 shows a sample flowchart to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Rev. 1.00 Oct. 03, 2008 Page 698 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) [1] Start initialization Clear TE and RE bits in SCR3 to 0. Set TXD, RXD, and SCK3 pins by PMC. Set CKE1 and CKE0 bits in SCR3. [1] Set data transfer format in SMR. [2] Set value in BRR. Wait [3] No 1-bit interval elapsed? [2] Yes [3] Set TE and RE bits in SCR3 to 1, and set RIE, TIE, TEIE, and MPIE bits. Set PMR bit corresponding to TXD and RXD pins to 1. [4] [4] With the PMC, select which of the TXD, RXD, and SCK3 pins are to be used. Set the clock selection in SCR3. Be sure to clear the other bits in SCR3 to 0. When clock output is selected in asynchronous mode, after the CKE1 and CKE0 settings have been made, output of the clock signal begins immediately upon setting of the PMR bits that correspond to pins selected by SCK3. When clock output is selected with reception in clock-synchronous mode, and CKE1, CKE0, and RE are set to 1, output of the clock signal begins immediately upon setting of the PMR bits that correspond to pins selected by SCK3. Set the data transfer format in SMR. Write the value corresponding to the bit rate to BRR. Not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR3 to 1. For transmission, enable use of the TXD output pin by setting the PMR bit for the pin selected as TXD by the PMC to 1. For reception, enable use of the RXD input pin by setting the PMR bit for the pin selected as RXD by the PMC to 1. Also set the RIE, TIE, TEIE, and MPIE bits, according to the required interrupts. In asynchronous mode, SCI3 is in the mark state (active) for transmission and in the space state (idle) while waiting for the start bit during reception. After the TE bit has been set to 1 in the case of transmission, transmission is enabled after the output of a frame with all bits 1. Figure 20.4 Sample Flowchart for Initializing SCI3 Rev. 1.00 Oct. 03, 2008 Page 699 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.3.3 Data Transmission Figure 20.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. The SCI3 checks the TDRE flag at the timing for sending the stop bit. 4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then transmission of the next frame is started. 5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. 6. Figure 20.6 shows a sample flowchart for transmission in asynchronous mode. Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 Mark state 1 TDRE TEND TXI interrupt LSI operation request generated User processing TDRE flag cleared to 0 Data written to TDR TXI interrupt request generated TEI interrupt request generated Figure 20.5 Example of Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Oct. 03, 2008 Page 700 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Start transmission [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR [2] Yes Is data transmission continued? No Read TEND flag in SSR [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue data transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. If data is transferred to TDR by the DTC with a transmit data empty interrupt (TXI) request, the TDRE flag is automatically checked and cleared. [3] To output a break at the end of data transmission, clear PMR corresponding to TxD to 0, after setting PCR to 1 and PDR to 0, then clear the TE bit in SCR3 to 0. No TEND = 1 Yes No Break output? Yes Clear PDR to 0, set PCR to 1, and clear PMR to 0 [3] Clear TE bit in SCR3 to 0 Figure 20.6 Sample Flowchart for Transmitting Data (Asynchronous Mode) Rev. 1.00 Oct. 03, 2008 Page 701 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.3.4 Data Reception Figure 20.7 shows an example of operation for reception in asynchronous mode. In reception, the SCI3 operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed. Start bit Serial data 1 0 D0 D1 1 frame Receive data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 1 frame D7 Parity Stop bit bit 0/1 0 Mark state (idle state) 1 RDRF FER LSI operation User processing RXI request RDRF cleared to 0 RDR data read 0 stop bit detected ERI request in response to framing error Framing error processing Figure 20.7 Example of Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Oct. 03, 2008 Page 702 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Table 20.6 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 20.8 shows a sample flowchart for data reception. Table 20.6 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains the state it had before data reception. Rev. 1.00 Oct. 03, 2008 Page 703 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Receive error processing (Continued on next page) Read RDRF flag in SSR No RDRF = 1 Yes [2] Read receive data in RDR Yes Is data reception continued? (A) No Clear RE bit in SCR3 to 0 [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically. [3] To continue data reception, before the stop bit for the current frame is received, read the RDRF flag and read RDR. The RDRF flag is cleared automatically by te RDR read. If RDR data is transferred by the DTC which was activated by an RXI interrupt, the RDRF flag is cleared automatically. [4] If a receive error occurs, read the OER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the RxD pin. Figure 20.8 Sample Flowchart for Data Reception (Asynchronous Mode) (1) Rev. 1.00 Oct. 03, 2008 Page 704 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) [4] Receive error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 20.8 Sample Flowchart for Data Reception (Asynchronous Mode) (2) Rev. 1.00 Oct. 03, 2008 Page 705 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.4 Operation in Clocked Synchronous Mode Figure 20.9 shows the format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In transmission, data is output from one falling edge of the synchronization clock to the next. In reception, data is received in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling fullduplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. 8 bits * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care One unit of transfer data (character or frame) * Figure 20.9 Data Format in Clocked Synchronous Communication 20.4.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock, the synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 20.4.2 SCI3 Initialization Before transmitting and receiving data, the SCI3 should be initialized as described in a sample flowchart in figure 20.4. Rev. 1.00 Oct. 03, 2008 Page 706 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.4.3 Data Transmission Figure 20.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. 3. The SCI3 outputs eight synchronization clock pulses when clock output mode has been specified. Data is output in synchronization with the input clock when use of an external clock has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD pin. 4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the MSB. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt request is generated. 7. The SCK3 pin is fixed high at the end of transmission. Figure 20.11 shows a sample flowchart for data transmission. Transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission. Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame TDRE TEND LSI TXI interrupt operation request generated User processing TDRE flag cleared to 0 Data written to TDR 1 frame TXI interrupt request generated TEI interrupt request generated Figure 20.10 Example of Transmission in Clocked Synchronous Mode Rev. 1.00 Oct. 03, 2008 Page 707 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 Yes [2] Write transmit data to TDR Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. If data is transferred to TDR by the DTC with a transmit data empty interrupt (TXI) request, the TDRE flag is automatically checked and cleared. To continue data transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. [2] Is data transmission continued? No Yes Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR3 to 0 Figure 20.11 Sample Flowchart for Data Transmission (Clocked Synchronous Mode) Rev. 1.00 Oct. 03, 2008 Page 708 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.4.4 Data Reception (Clocked Synchronous Mode) Figure 20.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronization clock input or output and starts receiving data. 2. The SCI3 stores the receive data in RSR. 3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. 4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is generated. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame RDRF OER LSI operation User processing RXI interrupt request generated RDRF flag cleared to 0 RDR data read 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Overrun error processing RDR data has not been read (RDRF = 1) Figure 20.12 Example of Reception in Clocked Synchronous Mode Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 20.13 shows a sample flowchart for data reception. Rev. 1.00 Oct. 03, 2008 Page 709 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Start reception [1] Read OER flag in SSR [1] [2] Yes OER = 1 [4] No Overrun error processing (Continued below) [3] Read RDRF flag in SSR [2] Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. If RDR data is transferred by the DTC with a receive data full interrupt (RXI) request, the RDRF flag is cleared automatically. To continue data reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag and reading RDR should be finished. When data is read from RDR, the RDRF flag is automatically cleared to 0. If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Reception cannot be resumed if the OER flag is set to 1. No RDRF = 1 Yes [4] Read receive data in RDR Yes Is data reception continued? No Clear RE bit in SCR3 to 0 [4] Overrun error processing Overrun error processing Clear OER flag in SSR to 0 Figure 20.13 Sample Flowchart for Data Reception (Clocked Synchronous Mode) Rev. 1.00 Oct. 03, 2008 Page 710 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.4.5 Simultaneous Data Transmission and Reception Figure 20.14 shows a sample flowchart for simultaneous transmit and receive operations. The following procedure should be used for simultaneous data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Rev. 1.00 Oct. 03, 2008 Page 711 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Start transmission/reception [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR [1] [2] [3] Read OER flag in SSR Yes [4] Overrun error processing OER = 1? No Read RDRF flag in SSR No RDRF = 1? Yes Read receive data in RDR [2] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. To continue data transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When data is read from RDR, the RDRF flag is automatically cleared to 0. If data is transferred to TDR by the DTC with a transmit data empty interrupt (TXI) request, the TDRE flag is automatically checked and cleared. If RDR data is transferred by the DTC with a receive data full iterrupt (RXI) request, the RDRF flag is automatically cleared. [4] [3] Yes Is data transfer continued? No Clear TE and RE bits in SCR to 0 If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Transmission/reception cannot be resumed if the OER flag is set to 1. For overrun error processing, see figure 20.13. Figure 20.14 Sample Flowchart of Simultaneous Transmit and Receive Operations (Clocked Synchronous Mode) Rev. 1.00 Oct. 03, 2008 Page 712 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 20.15 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and OER, to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 1.00 Oct. 03, 2008 Page 713 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) ID transmission cycle = Receiving station specification Legend MPB: Multiprocessor bit Receiving station C (ID = 03) H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Receiving station D (ID = 04) Figure 20.15 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 20.5.1 Multiprocessor Data Transmission Figure 20.16 shows a sample flowchart for multiprocessor data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode. Rev. 1.00 Oct. 03, 2008 Page 714 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Start transmission [1] [1] Read TDRE flag in SSR Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue data transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. If data is transferred to TDR by the DTC with a transmit data empty interrupt (TXI) request, the TDRE flag is automatically checked and cleared. To output a break in serial transmission, set the port PCR to 1, clear PDR and PMR to 0, then clear the TE bit in SCR3 to 0. No TDRE = 1 [2] Yes Set MPBT bit in SSR Write transmit data to TDR Yes [2] Is data transmission continued? No [3] Read TEND flag in SSR No TEND = 1 Yes No [3] Break output? Yes Clear PDR to 0, set PCR to 1 and clear PMR to 0 Clear TE bit in SCR3 to 0 Figure 20.16 Sample Flowchart for Multiprocessor Data Transmission Rev. 1.00 Oct. 03, 2008 Page 715 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.5.2 Multiprocessor Data Reception Figure 20.17 shows a sample flowchart for multiprocessor data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 20.18 shows an example of SCI3 operation for multiprocessor data reception. Rev. 1.00 Oct. 03, 2008 Page 716 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Start reception [1] [2] [1] [2] Yes [3] Set MPIE bit in SCR3 to 1 Read OER and FER flags in SSR FER+OER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read OER and FER flags in SSR Yes FER+OER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR Yes Is data reception continued? No [A] Clear RE bit in SCR3 to 0 Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again. When data is read from RDR, the RDRF flag is automatically cleared to 0. Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. If a receive error occurs, read the OER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. [5] Receive error processing (Continued on next page) Figure 20.17 Sample Flowchart for Multiprocessor Data Reception (1) Rev. 1.00 Oct. 03, 2008 Page 717 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) [5] Receive error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing [A] Clear OER, and FER flags in SSR to 0 Figure 20.17 Sample Flowchart for Multiprocessor Data Reception (2) Rev. 1.00 Oct. 03, 2008 Page 718 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Start bit Serial data 1 0 D0 Receive data (ID1) D1 1 frame D7 MPB 1 Stop Start bit bit 1 0 D0 Receive data (Data1) D1 1 frame D7 MPB 0 Stop bit 1 Mark state (idle state) 1 MPIE RDRF RDR value LSI operation User processing RXI interrupt request MPIE cleared to 0 RDRF flag cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again ID1 RXI interrupt request is not generated, and RDR retains its state (a) When data does not match this receiver's ID Start bit Serial data 1 0 D0 Receive data (ID2) D1 1 frame D7 MPB 1 Stop Start bit bit 1 0 D0 Receive data (Data2) D1 1 frame D7 MPB 0 Stop bit 1 Mark state (idle state) 1 MPIE RDRF RDR value LSI operation User processing ID1 ID2 Data2 RXI interrupt request MPIE cleared to 0 RDRF flag cleared to 0 RDR data read RXI interrupt request When data is this station's ID, reception is continued RDRF flag cleared to 0 RDR data read MPIE set to 1 again (b) When data matches this receiver's ID Figure 20.18 Example of Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 1.00 Oct. 03, 2008 Page 719 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.6 IrDA Operation The SCI3_2 provides the IrDA function. If the IrDA function is enabled using the IrE bit in IrCR, the TxD_2 and RxD_2 pins in SCI2_3 are allowed to encode and decode the waveform based on the IrDA Specifications version 1.0 (function as the IrTxD and IrRxD pins)*. Connecting these pins to the infrared data transceiver achieves infrared data communications based on the system defined by the IrDA Specifications version 1.0. In the system defined by the IrDA Specifications version 1.0, communication is started at a transfer rate of 9600 bps, which can be modified later as required. Since the IrDA interface provided by this LSI does not incorporate the capability of automatic modification of the transfer rate, the transfer rate must be modified through programming. Figure 20.19 is the IrDA block diagram. IrDA TXD_2/IrTxD RXD_2/IrRxD Phase inversion Phase inversion Pulse encoder Pulse decoder TxD RxD SCI3_2 IrCR Figure 20.19 IrDA Block Diagram IrDA operation should be set according to the following procedures. (1) Set the corresponding pin in the MCR register or PMR register. (2) Set the IrCR register. (3) Set the register related to SCI3_2. Rev. 1.00 Oct. 03, 2008 Page 720 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.6.1 Transmission During transmission, the output signals from the SCI3_2 (UART frames) are converted to IR frames using the IrDA interface (see figure 20.20). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in IrCR. The high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) x bit rate or (3/16 x bit rate) +1.08 s at maximum. For example, when the frequency of system clock is 20 MHz, a high-level pulse width of 1.6 s can be specified because it is the smallest value in the range greater than 1.41 s. For serial data of level 1, no pulses are output. UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1 0 Transmission Reception IR frame Start bit 0 1 0 1 0 Data Stop bit 0 1 1 0 1 Bit cycle Pulse width is 1.6 ms to 3/16 bit cycle. Figure 20.20 IrDA Transmission and Reception 20.6.2 Reception During reception, IR frames are converted to UART frames using the IrDA interface before inputting to SCI3_2. 0 is output when the high level pulse is detected while 1 is output when no pulse is detected during one bit period. Note that a pulse shorter than the minimum pulse width of 1.41 s is regarded as a 0 signal. Rev. 1.00 Oct. 03, 2008 Page 721 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.6.3 High-Level Pulse Width Selection Table 20.7 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 20.7 Settings of Bits IrCKS2 to IrCKS0 Operating Frequency 2400 (MHz) 78.13 4.9152 5 6 6.144 7.3728 8 9.3804 10 12 12.288 14 14.7456 16 16.9344 17.2032 18 19.6608 20 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 Bit Rate (bps) (Above)/Bit Period x 3/16 (Below) 9600 19.53 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 19200 9.77 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 38400 4.88 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 57600 3.26 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 115200 1.63 011 011 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 Rev. 1.00 Oct. 03, 2008 Page 722 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.7 Noise Canceler Figure 20.21 shows a block diagram of the noise canceler circuit. When the noise canceler function is enabled, the RXD input signal is routed through the noise canceler before being provided internally. The noise canceler consists of three cascaded latches and a match detector. The RXD input signal is sampled at the basic clock frequency, 16 times the transfer rate, and when the outputs of three latches agree, the level is passed to the next circuit. If they do not agree, the previous value is held. In other words, if the input level changes and the level remains the same for three or more clock cycles after the change, it is recognized as a signal. However, if the level remains the same for less than three clock cycles, it is recognized as a noise, not as a signal. Sampling clock C RXD input signal D Latch Q D C Q Latch D C Q Latch Match detector circuit SPMR (NFEN) Internal RXD signal in figure 20.1 Internal basic clock cycle Sampling clock Figure 20.21 Block Diagram of Noise Canceler Rev. 1.00 Oct. 03, 2008 Page 723 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.8 Interrupt Requests The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 20.8 shows the interrupt sources. Table 20.8 SCI3 Interrupt Requests Interrupt Requests Abbreviation Interrupt Sources Setting RDRF in SSR Setting TDRE in SSR Setting TEND in SSR Setting OER, FER, and PER in SSR DTC Activation Possible Possible Impossible Impossible Receive Data Full RXI Transmit Data Empty TXI Transmission End TEI Receive Error ERI When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. The DTC can be activated to perform data transfers with the TXI interrupt request. The TDRE flag is automatically cleared to 0 by the DTC data transfer. When the RDRF flag in SSR is set to 1, a RXI interrupt request is generated. When any of the ORER, PER and FER flags is set to 1, an ERI interrupt request is generated. The DTC can be activated to perform data transfers with the RXI interrupt request. The RDRE flag is automatically cleared to 0 by the DTC data transfer. The TEI interrupt is generated if the TEND flag is set to 1 when the TEIE bit is 1. If the TEI and TXI interrupts are generated at the same time, the TXI interrupt is accepted first. Therefore, if the TDRE and TEND flags are to be simultaneously cleared in a TXI interrupt routine, branching to a TEI interrupt routine cannot be performed. The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if the transmit data has not been sent. It is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that correspond to these interrupt requests to 1, after transferring the transmit data to TDR. Rev. 1.00 Oct. 03, 2008 Page 724 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.9 20.9.1 Usage Notes Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RXD pin value directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 20.9.2 Mark State and Break Sending When the PMR bit corresponding to the pin selected by the PMC is 0, the TXD pin is used as an I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be used to set the TXD pin to mark state (high level) or send a break during data transmission. To maintain the communication line at mark state until the PMR bit is set to 1, set both PCR and PDR to 1. As the PMR bit is cleared to 0 at this point, the TXD pin becomes an I/O port, and 1 is output from the TXD pin. To send a break during transmission, first set PCR to 1 and clear PDR to 0, and then clear the PMR bit to 0. When the PMR bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TXD pin becomes an I/O port, and 0 is output from the TXD pin. 20.9.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Rev. 1.00 Oct. 03, 2008 Page 725 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.9.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 20.22. Thus, the reception margin in asynchronous mode is given by formula (1) below. M= {( 0.5 1 2N )D - 0.5 N - (L - 0.5) F } x 100 (%)... Formula 1 ... Formula (1) [Legend] N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. 16 clocks 8 clocks 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0 Start bit D0 D1 Figure 20.22 Receive Data Sampling Timing in Asynchronous Mode Rev. 1.00 Oct. 03, 2008 Page 726 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.9.5 Relation between Writes to TDR and TDRE Flag Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the DRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data TDR. 20.9.6 Restrictions on Using DTC When the external clock source is used as a synchronization clock, update TDR by the DTC or CPU and wait for at least five clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI3 may malfunction (see figure 20.23). When using the DTC to read RDR, be sure to set the receive end interrupt (RXI) for the relevant SCI3 as the DTC activation source. SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When an external clock is supplied, t must be more than four clock cycles. Figure 20.23 Example of DTC Transmission in Clock Synchronous Mode Rev. 1.00 Oct. 03, 2008 Page 727 of 962 REJ09B0465-0100 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Rev. 1.00 Oct. 03, 2008 Page 728 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Section 21 I2C Bus Interface 2 (IIC2) The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 21.1 shows a block diagram of the I2C bus interface 2. Figure 21.2 shows an example of I/O pin connections to external circuits. Either the IIC2 or SSU incorporated in this LSI can be used at a time. Accordingly, when the IIC2 function is used, the SSU function is not available. 21.1 Features * Selectable for I2C bus format or clock synchronous serial format * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. I2C Bus Format: Start and stop conditions generated automatically in master mode Selectable for acknowledge output levels when receiving Automatic loading of acknowledge bit when transmitting Bit synchronization/wait function stored In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed. * Six interrupt sources Transmit data empty (including slave-address match), transmit end, receive data full (including slave-address match), arbitration lost, NACK detection, and stop condition detection. The DTC can be activated by the transmit-data-empty and receive-data-full interrupts. * Direct bus drive possible Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive function is selected. Clock Synchronous Format: * Four interrupt sources Transmit-data-empty, transmit-end, receive-data-full, and overrun error. The DTC can be activated by the transmit-data-empty and receive-data-full interrupt sources. Rev. 1.00 Oct. 03, 2008 Page 729 of 962 REJ09B0465-0100 * * * * Section 21 I C Bus Interface 2 (IIC2) 2 Transfer clock generation circuit SCL Output control Transmission/ reception control circuit ICCR1 ICCR2 ICMR Noise canceler ICDRT SAR SDA Output control ICDRS Noise canceler Address comparator ICDRR Bus state decision circuit Arbitration decision circuit ICIER Interrupt generator ICSR Figure 21.1 Block Diagram of I2C Bus Interface 2 Rev. 1.00 Oct. 03, 2008 Page 730 of 962 REJ09B0465-0100 Internal data bus Interrupt request Section 21 I C Bus Interface 2 (IIC2) 2 Vcc Vcc SCL in SCL out SCL SCL SDA in SDA out SDA SDA SCL SDA (Master) SCL in SCL out SCL in SCL out SDA in SDA out (Slave 1) SDA in SDA out (Slave 2) Figure 21.2 External Circuit Connections of I/O Pins Table 21.1 summarizes the pin configuration used by the I2C bus interface 2. Table 21.1 Pin Configuration Pin Name SCL SDA I/O I/O I/O Function IIC serial clock input/output IIC serial data input/output Rev. 1.00 Oct. 03, 2008 Page 731 of 962 REJ09B0465-0100 SCL SDA Section 21 I C Bus Interface 2 (IIC2) 2 21.2 Register Descriptions The IIC2 has the following registers. * * * * * * * * * * IIC2/SSU select register (ICSUSR) I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) I2C bus slave address register (SAR) I2C bus transmit data register (ICDRT) I2C bus receive data register (ICDRR) I2C bus shift register (ICDRS) Rev. 1.00 Oct. 03, 2008 Page 732 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.2.1 IIC2/SSU Select Register (ICSUSR) Address: H'FF000B Bit: b7 b6 b5 b4 b3 b2 b1 b0 SELICSU 0 0 0 0 0 0 0 Value after reset: 0 Bit Symbol Bit Name Reserved Description These bits are read as 0. The write value should be 0. R/W R/W 7 to 1 0 SELICSU IIC2/SSU 0: IIC2 function is selected.* module function 1: SSU function is selected. select Note: To select the IIC2 function, this bit should be set to 0 without fail. 21.2.2 I2C Bus Control Register 1 (ICCR1) Address: H'FF05C8 Bit: b7 ICE b6 RCVD 0 b5 MST 0 b4 TRS 0 0 0 b3 b2 CKS[3:0] 0 0 b1 b0 Value after reset: 0 Bit 7 Symbol ICE Bit Name I C bus interface 2 enable Reception disable Master/slave select Transmit/ receive select Transfer clock select 3 to 0 2 Description 0: This module is stopped. (SCL and SDA pins are set to port function.) 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) 0: Enables next reception 1: Disables next reception 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode R/W R/W 6 5 4 RCVD MST TRS R/W R/W R/W 3 to 0 CKS[3:0] These bits should be set according to the necessary R/W transfer rate (see table 21.2) in master mode. Rev. 1.00 Oct. 03, 2008 Page 733 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 * RCVD bit (reception disable) Selects to enable or disable the next operation when TRS is 0 and ICDRR is read. * MST bit (master/slave select) and TRS bit (transmit/receive select) In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be performed between transfer frames. After data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to SAR and the eighth bit is 1, TRS is automatically set to 1. If an overrun error occurs in master mode with the clock synchronous serial format, MST is cleared to 0 and slave receive mode is entered. Operating modes are described above according to MST and TRS combination. When clock synchronous serial format is selected and MST is 1, clock is output. * CKS[3:0] bits (transfer clock select 3 to 0) These bits should be set according to the necessary transfer rate (see table 21.2) in master mode. In slave mode, these bits are used for reservation of the data setup time in transmit mode. The time is 10 tcyc when CKS3 = 0 and 20 tcyc when CKS3 = 1. Rev. 1.00 Oct. 03, 2008 Page 734 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Table 21.2 Transfer Rate Bit 3 CKS3 0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 = 5 MHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz Transfer Rate = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz = 16 MHz 571 kHz 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz = 20 MHz 714 kHz 500 kHz 417 kHz 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz Rev. 1.00 Oct. 03, 2008 Page 735 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.2.3 I2C Bus Control Register 2 (ICCR2) Address: H'FF05C9 Bit: b7 BBSY b6 SCP 1 b5 SDAO 1 b4 SDAOP 1 b3 SCLO 1 b2 b1 IICRST 0 b0 1 1 Value after reset: 0 Bit 7 Symbol BBSY* 1 Bit Name Bus busy Description 2 R/W This bit enables to confirm whether the I C bus is R/W occupied or released and to issue start/stop conditions in master mode. With the clock synchronous serial format, this bit has no meaning. 2 With the I C bus format, this bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also re-transmitting a start condition. Write 0 in BBSY and 0 in SCP to issue a stop condition. To issue start/stop conditions, use the MOV instruction. 6 SCP Start/stop The SCP bit controls the issue of start/stop R/W condition issue conditions in master mode. To issue a start disable condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. SDA output value control This bit is used with SDAOP (bit 4) when modifying R/W output level of SDA. This bit should not be manipulated during transfer. 0: When reading, SDA pin outputs low. When writing, SDA pin is changed to output low. 1: When reading, SDA pin outputs high. When writing, SDA pin is changed to output Hi-Z (outputs high by external pull-up resistance). 5 SDAO Rev. 1.00 Oct. 03, 2008 Page 736 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Bit 4 Symbol SDAOP Bit Name SDAO write protect Description This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. This bit monitors SCL output level. When reading and SCLO is 1, SCL pin outputs high. When reading and SCLO is 0, SCL pin outputs low. This bit is read as 1. The write value should be 1. 2 R/W R/W 3 SCLO SCL output level monitor Reserved 2 R 2 1 IICRST* R/W IIC control part This bit resets the control part except for I C reset registers. If this bit is set to 1 when hang-up occurs 2 because of communication failure during I C 2 operation, I C control part can be reset without setting ports and initializing registers. Reserved This bit is read as 1. The write value should be 1. 0 Note: 1. In standby mode, the BBSY bit in ICCR2 is reset. 2. Clear IICRST to 0 by software since this bit is not cleared automatically. Rev. 1.00 Oct. 03, 2008 Page 737 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.2.4 I2C Bus Mode Register (ICMR) Address: H'FF05CA Bit: b7 MLS b6 WAIT 0 b5 b4 b3 BCWP 1 0 b2 b1 BC[2:0] 0 0 b0 0 1 Value after reset: 0 Bit 7 6 Symbol MLS WAIT Bit Name Description R/W R/W R/W MSB-first/LSB- 0: Transfer in MSB-first* first select 1: Transfer in LSB-first Wait insertion 0: Data and acknowledge bits are transferred consecutively with no wait inserted. 1: After the fall of the clock for the final data bit, low period is extended for two transfer clocks. 5 4 3 BCWP Reserved Reserved BC write protect This bit is read as 0. The write value should be 0. This bit is read as 1. The write value should be 1. 0: When writing, modifying BC2 to BC0 values is valid. 1: When writing, modifying BC2 to BC0 values is invalid. R/W 2 to 0 BC[2:0] 2 Bit counter 2 to I C Bus Format 0 000: 9 bits Clock Synchronous Serial Format R/W 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits Note: * Set this bit to 0 when the I2C bus format is used. Rev. 1.00 Oct. 03, 2008 Page 738 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 * WAIT bit (wait insertion) In master mode with the I2C bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The setting of this bit is invalid in slave mode with the I2C bus format or with the clock synchronous serial format. * BCWP bit (BC write protect) Controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction. In clock synchronous serial mode, BC should not be modified. * BC[2:0] bits (bit counter 2 to 0) Specifies the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. With the I2C bus format, the data is transferred with one additional acknowledge bit. Bit BC2 to BC0 should be set during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL pin is low. The value automatically returns to 000 at the end of a data transfer, including the acknowledge bit. With the clock synchronous serial format, these bits should not be modified. 21.2.5 I2C Bus Interrupt Enable Register (ICIER) Address: H'FF05CB Bit: b7 TIE b6 TEIE 0 b5 RIE 0 b4 NAKIE 0 b3 STIE 0 b2 ACKE 0 b1 ACKBR 0 b0 ACKBT 0 Value after reset: 0 Bit 7 Symbol TIE Bit Name Description R/W R/W Transmit 0: Transmit data empty interrupt request (TXI) is interrupt enable disabled. 1: Transmit data empty interrupt request (TXI) is enabled. 6 TEIE Transmit end 0: Transmit end interrupt request (TEI) is disabled. interrupt enable 1: Transmit end interrupt request (TEI) is enabled. R/W Rev. 1.00 Oct. 03, 2008 Page 739 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Bit 5 Symbol RIE Bit Name Description R/W R/W Receive 0: Receive data full interrupt request (RXI) is interrupt enable disabled. 1: Receive data full interrupt request (RXI) is enabled. 4 NAKIE NACK receive 0: NACK receive interrupt request (NAKI) and interrupt enable overrun error interrupt request (ERI) with the clock synchronous format are disabled. 1: NACK receive interrupt request (NAKI) and overrun error interrupt request (ERI) with the clock synchronous format are enabled. R/W 3 STIE Stop condition 0: Stop condition detection interrupt request (STPI) R/W detection is disabled. interrupt enable 1: Stop condition detection interrupt request (STPI) is enabled. Acknowledge bit judgment select Receive acknowledge Transmit acknowledge 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is stopped. 0: Receive acknowledge = 0 1: Receive acknowledge = 1 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing. R/W R R/W 2 ACKE 1 0 ACKBR ACKBT * TIE bit (transmit interrupt enable) When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). * TEIE bit (transmit end interrupt enable) This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. * RIE bit (receive interrupt enable) This bit enables or disables the receive data full interrupt request (RXI) when a receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. Rev. 1.00 Oct. 03, 2008 Page 740 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 * NAKIE bit (NACK receive interrupt enable) This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clock synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. * STIE bit (stop condition detection interrupt enable) This bet should be set to 1 while the STOP bit in ICSR is 0. * ACKBR bit (receive acknowledge) In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. * ACKBT bit (transmit acknowledge) In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 21.2.6 I2C Bus Status Register (ICSR) Address: H'FF05CC Bit: b7 TDRE b6 TEND 0 b5 RDRF 0 b4 NACKF 0 b3 STOP 0 b2 AL_OVE 0 b1 AAS 0 b0 ADZ 0 Value after reset: 0 Bit 7 Symbol TDRE Bit Name Transmit data empty flag Description [Setting conditions] * When data is transferred from ICDRT to ICDRS and ICDRT becomes empty * When TRS is set * When a start condition (including re-transfer) has been issued * When transmit mode is entered from receive mode in slave mode [Clearing conditions] * When 0 is written in TDRE after reading TDRE = 1 * When data is written to ICDRT with an instruction * When the DTC transfers data to ICDRT by a TXI interrupt request, and the DTC settings satisfy the flag clearing conditions. R/W R/W Rev. 1.00 Oct. 03, 2008 Page 741 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Bit 6 Symbol TEND Bit Name Description * * 2 R/W R/W Transmit end flag [Setting conditions] When the ninth clock of SCL rises with the I C bus format while the TDRE flag is 1 When the final bit of transmit frame is sent with the clock synchronous serial format When 0 is written in TEND after reading TEND = 1 When data is written to ICDRT with an instruction [Clearing conditions] * * 5 RDRF Receive data register full flag * [Setting condition] When a receive data is transferred from ICDRS to ICDRR When 0 is written in RDRF after reading RDRF = 1 When ICDRR is read with an instruction When the DTC transfers data to ICDRR by an RXI interrupt request, and the DTC settings satisfy the flag clearing conditions. R/W [Clearing conditions] * * * 4 NACKF No acknowledge [Setting condition] R/W detection flag * When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] * When 0 is written in NACKF after reading NACKF =1 R/W When a stop condition is detected after frame transfer end When 0 is written in STOP after reading STOP = 1 3 STOP Stop condition detection flag [Setting conditions] * [Clearing condition] * Rev. 1.00 Oct. 03, 2008 Page 742 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Bit 2 Symbol AL_OVE Bit Name Description R/W R/W Arbitration lost [Setting conditions] flag/overrun error * If the internal SDA and SDA pin disagree at the flag rise of SCL in master transmit mode * * When the SDA pin outputs high in master mode while a start condition is detected When the final bit is received with the clock synchronous format while RDRF = 1 When 0 is written in AL/OVE after reading AL/OVE =1 [Clearing condition] * 1 AAS Slave address recognition flag [Setting conditions] * * When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode. When 0 is written in AAS after reading AAS = 1 R/W [Clearing condition] * 0 ADZ General call address recognition flag This bit is enabled in slave receive mode with I2C bus R/W format. [Setting condition] * When the general call address is detected in slave receive mode When 0 is written in ADZ after reading ADZ = 1 [Clearing condition] * Notes: In standby mode, ICSR is reset. * The DTC clears the peripheral module flags when all of the following three conditions are satisfied. 1. When the DISEL bit is 0. 2. When the transfer counter is not 0. (DTC transfer count register A (CRA) in normal mode and repeat mode, or DTC transfer count register B (CRB) in block mode) 3. When chain transfer is not used. Rev. 1.00 Oct. 03, 2008 Page 743 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 * AL_OVE bit (arbitration lost flag/overrun error flag) This flag indicates that arbitration was lost in master mode with the I2C bus format and that the final bit has been received while RDRF = 1 with the clock synchronous format. When two or more master devices attempt to seize the bus at nearly the same time, if the I2C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. * AAS bit (slave address recognition flag) In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. Rev. 1.00 Oct. 03, 2008 Page 744 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.2.7 Slave Address Register (SAR) Address: H'FF05CD Bit: b7 SVA6 b6 SVA5 0 b5 SVA4 0 b4 SVA3 0 b3 SVA2 0 b2 SVA1 0 b1 SVA0 0 b0 FS 0 Value after reset: 0 Bit Symbol Bit Name Slave address 6 to 0 Format select Description These bits set a unique address in bits SVA6 to SVA0, differing form the addresses of other slave devices connected to the I2C bus. 0: I2C bus format is selected. 1: Clock synchronous serial format is selected. R/W R/W 7 to 1 SVA6 to SVA0 0 FS R/W SAR selects the format and sets the slave address. When SAR is in slave mode with the I2C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, SAR operates as the slave device. 21.2.8 I2C Bus Transmit Data Register (ICDRT) Address: H'FF05CE Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of ICDRT is H'FF. ICDRT is reset in standby mode. Rev. 1.00 Oct. 03, 2008 Page 745 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.2.9 I2C Bus Receive Data Register (ICDRR) Address: H'FF05CF Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is H'FF. ICDRR is reset in standby mode. 21.2.10 I2C Bus Shift Register (ICDRS) Address: Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the CPU. ICDRS is reset in standby mode. Rev. 1.00 Oct. 03, 2008 Page 746 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.3 Operation The I2C bus interface 2 can communicate either in I2C bus mode or clock synchronous serial mode by setting FS in SAR. 21.3.1 I2C Bus Format Figure 21.3 shows the I2C bus formats. Figure 21.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits. (a) I2C bus format (FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1) (b) I2C bus format (Start condition retransmission, FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1) Figure 21.3 I2C Bus Formats SDA SCL S 1-7 SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A P Figure 21.4 I2C Bus Timing [Legend] S: SLA: Start condition. The master device drives SDA from high to low while SCL is high. Slave address Rev. 1.00 Oct. 03, 2008 Page 747 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. Acknowledge. The receive device drives SDA to low. A: DATA: Transfer data P: 21.3.2 Stop condition. The master device drives SDA from low to high while SCL is high. Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, see figures 21.5 and 21.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Read the BBSY flag in ICCR2 to confirm that the bus is released. Set the MST and TRS bits in ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV instruction. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0, and data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode. Rev. 1.00 Oct. 03, 2008 Page 748 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 SCL (Master output) SDA (Master output) 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W 9 1 Bit 7 2 Bit 6 Slave address SDA (Slave output) TDRE A TEND ICDRT Address + R/W Data 1 Data 2 ICDRS Address + R/W Data 1 User processing [2] Instruction of start condition issuance [4] Write data to ICDRT (second byte) [3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte) Figure 21.5 Master Transmit Mode Operation Timing (1) SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 9 A/A TEND ICDRT Data n ICDRS Data n User [5] Write data to ICDRT processing [6] Issue stop condition. Clear TEND. [7] Set slave receive mode Figure 21.6 Master Transmit Mode Operation Timing (2) Rev. 1.00 Oct. 03, 2008 Page 749 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, see figures 21.7 and 21.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDRR is read (dummy read), reception is started. And the receive clock is output to receive data in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICSR is set to 1 at the rise of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF is cleared to 0. 4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stop condition. 7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode. Rev. 1.00 Oct. 03, 2008 Page 750 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A 9 1 Master receive mode 2 3 4 5 6 7 8 9 A 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 21.7 Master Receive Mode Operation Timing (1) Rev. 1.00 Oct. 03, 2008 Page 751 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 SCL (Master output) SDA (Master output) SDA (Slave output) RDRF 9 A 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCVD ICDRS Data n-1 Data n ICDRR User processing Data n-1 Data n [5] Read ICDRR after setting RCVD [6] Issue stop condition [7] Read ICDRR, and clear RCVD [8] Set slave receive mode Figure 21.8 Master Receive Mode Operation Timing (2) 21.3.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, see figures 21.9 and 21.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1 (Initial setting). Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is released. 5. Clear TDRE. Rev. 1.00 Oct. 03, 2008 Page 752 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Slave receive mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE A 9 Slave transmit mode 1 2 3 4 5 6 7 8 9 A 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TEND TRS ICDRT Data 1 Data 2 Data 3 ICDRS Data 1 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 21.9 Slave Transmit Mode Operation Timing (1) Rev. 1.00 Oct. 03, 2008 Page 753 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Slave receive mode Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE 9 A 1 2 3 4 5 6 7 8 9 A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 21.10 Slave Transmit Mode Operation Timing (2) Rev. 1.00 Oct. 03, 2008 Page 754 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.3.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, see figures 21.11 and 21.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data show the slave address + R/W, it is not used.) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is set to 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, which is returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR. SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) 9 1 2 3 4 5 6 7 8 9 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 A A RDRF ICDRS Data 1 Data 2 ICDRR User processing Data 1 [2] Read ICDRR (dummy read) [2] Read ICDRR Figure 21.11 Slave Receive Mode Operation Timing (1) Rev. 1.00 Oct. 03, 2008 Page 755 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) 9 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 9 A A RDRF ICDRS Data 1 Data 2 ICDRR User processing Data 1 [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR Figure 21.12 Slave Receive Mode Operation Timing (2) 21.3.6 Clock Synchronous Serial Format This module can be operated with the clock synchronous serial format by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. (1) Data Transfer Format Figure 21.13 shows the clock synchronous serial transfer format. The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer: in either the MSB first or LSB first. The output level of SDA can be changed during the transfer wait by the SDAO bit in ICCR2. SCL SDA Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 21.13 Clock Synchronous Serial Transfer Format Rev. 1.00 Oct. 03, 2008 Page 756 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 (2) Transmit Operation In transmit mode, transmit data is output from SDA in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1 and is input when MST is 0. For transmit mode operation timing, see figure 21.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1 (Initial setting). 2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set. 3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous transmission is performed by writing data to ICDRT every time TDRE is set. When changing from transmit mode to receive mode, clear TRS while TDRE is set to 1. SCL SDA (Output) TRS TDRE ICDRT ICDRS 1 2 7 Bit 6 8 Bit 7 1 Bit 0 7 Bit 6 8 Bit 7 1 Bit 0 Bit 0 Bit 1 Data 1 Data 1 Data 2 Data 2 Data 3 Data 3 User processing [3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS [3] Write data to ICDRT [3] Write data to ICDRT Figure 21.14 Transmit Mode Operation Timing Rev. 1.00 Oct. 03, 2008 Page 757 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 (3) Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1 and is input when MST is 0. For receive mode operation timing, see figure 21.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1 (Initial setting). 2. When the transfer clock is output, set MST to 1 to start outputting the receive clock. 3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is continually output. The continuous reception is performed by reading ICDRR every time RDRF is set. When the 8th clock is risen while RDRF is set to 1, the overrun is detected and AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 4. To stop receiving when MST = 1, read ICDRR after setting RCVD in ICCR1 to 1. Then, SCL is fixed high after receiving the next byte data. SCL SDA (Input) MST TRS 1 2 7 Bit 6 8 Bit 7 1 Bit 0 7 Bit 6 8 Bit 7 1 Bit 0 2 Bit 1 Bit 0 Bit 1 RDRF ICDRS ICDRR Data 1 Data 2 Data 3 Data 1 [2] Set MST (when outputting the clock) Data 2 User processing [3] Read ICDRR [3] Read ICDRR Figure 21.15 Receive Mode Operation Timing Rev. 1.00 Oct. 03, 2008 Page 758 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.3.7 Noise Filter Circuit The signal state on the SCL and SDA pins are internally latched via the noise filter circuit. Figure 21.16 shows a block diagram of the noise filter circuit. The noise filter consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock. When both outputs of the latches match, its level is output to other blocks by the match detector circuit. If they do not match, the previous value is held. Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch Match detector circuit Internal SCL or SDA signal System clock cycle Sampling clock Figure 21.16 Block Diagram of Noise Filter Circuit Rev. 1.00 Oct. 03, 2008 Page 759 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.3.8 Example of Use Flowcharts in respective modes that use the I2C bus interface 2 are shown in figures 21.17 to 21.20. Start Initialize Read BBSY in ICCR2 No [1] BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1. Write 1 to BBSY and 0 to SCP. Write transmit data in ICDRT Read TEND in ICSR No [5] TEND=1 ? Yes Read ACKBR in ICIER [6] ACKBR=0 ? Yes Transmit mode? Yes No Mater receive mode [12] Clear the STOP flag. [13] Issue the stop condition. [8] TDRE=1 ? Yes No Last byte? [9] Yes Write transmit data in ICDRT Read TEND in ICSR No [10] TEND=1 ? Yes Clear TEND in ICSR Clear STOP in ICSR Write 0 to BBSY and SCP Read STOP in ICSR No [14] STOP=1 ? Yes Set MST to 1 and TRS to 0 in ICCR1 Clear TDRE in ICSR End [11] [12] [13] [14] Wait for the generation of stop condition. [15] Set slave receive mode. Clear TDRE. No [11] Clear the TEND flag. [8] [9] Wait for ICDRT empty. Set the last byte of transmit data. [3] [2] [3] [4] [4] [5] [6] [7] Issue the start condition. Set the first byte (slave address + R/W) of transmit data. Wait for 1 byte to be transmitted. Test the acknowledge transferred from the specified slave device. Set the second and subsequent bytes (except for the last byte) of transmit data. [1] [2] Test the state of the SCL and SDA lines. Set master transmit mode. [10] Wait for last byte to be transmitted. Write transmit data in ICDRT Read TDRE in ICSR No [7] [15] Figure 21.17 Sample Flowchart for Master Transmit Mode Rev. 1.00 Oct. 03, 2008 Page 760 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Mater receive mode [1] Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR No RDRF=1 ? Yes Last receive - 1? No Read ICDRR Yes [5] [4] [2] Clear TEND, select master receive mode, and then clear TDRE.* Set acknowledge to the transmit device.* Dummy-read ICDDR.* Wait for 1 byte to be received Check whether it is the (last receive - 1). Read the receive data. Set acknowledge of the last byte. Disable continuous reception (RCVD = 1). Read the (last byte - 1) of receive data. Wait for the last byte to be receive. [2] [1] [3] [4] [5] [6] [7] [8] [9] [3] [10] Clear the STOP flag. [6] [11] Issue the stop condition. [12] Wait for the generation of stop condition. Set ACKBT in ICIER to 1 [7] [13] Read the last byte of receive data. [14] Clear RCVD. Set RCVD in ICCR1 to 1 Read ICDRR Read RDRF in ICSR No RDRF=1 ? Yes Clear STOP in ICSR. Write 0 to BBSY and SCP Read STOP in ICSR No [12] [10] [9] [8] [15] Set slave receive mode. [11] STOP=1 ? Yes Read ICDRR [13] [14] Clear RCVD in ICCR1 to 0 Clear MST in ICCR1 to 0 End [15] Note: Do not activate an interrupt during the execution of steps [1] to [3]. Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1] before jumping to step [7]. The step [8] is dummy-read in ICDRR. Figure 21.18 Sample Flowchart for Master Receive Mode Rev. 1.00 Oct. 03, 2008 Page 761 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR No [3] TDRE=1 ? Yes No Last byte? [1] Clear the AAS flag. [1] [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. [2] [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. [6] Clear the TEND flag . [7] Set slave receive mode. [8] Dummy-read ICDRR to release the SCL. [4] [9] Clear the TDRE flag. Yes Write transmit data in ICDRT Read TEND in ICSR No [5] TEND=1 ? Yes Clear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy read ICDRR Clear TDRE in ICSR End [6] [7] [8] [9] Figure 21.19 Sample Flowchart for Slave Transmit Mode Rev. 1.00 Oct. 03, 2008 Page 762 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR [1] [2] Set acknowledge to the transmit device. [2] [3] Dummy-read ICDRR. [3] [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). [4] [6] Read the receive data. [7] Set acknowledge of the last byte. Read RDRF in ICSR No RDRF=1 ? Yes Last receive - 1? Yes [5] [8] Read the (last byte - 1) of receive data. [9] Wait the last byte to be received. No Read ICDRR [6] [10] Read for the last byte of receive data. Set ACKBT in ICIER to 1 [7] Read ICDRR Read RDRF in ICSR No [8] [9] RDRF=1 ? Yes Read ICDRR End [10] Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1] before jumping to step [7]. The step [8] is dummy-read in ICDRR. Figure 21.20 Sample Flowchart for Slave Receive Mode Rev. 1.00 Oct. 03, 2008 Page 763 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.4 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP condition detection, and arbitration lost/overrun error. Table 21.3 shows the contents of each interrupt request. Table 21.3 Interrupt Requests Clock Synchronous I2C Mode Mode O O O O O O O O O x x O Interrupt Request Transmit Data Empty Transmit End Receive Data Full STOP Condition Detection NACK Detection Arbitration Lost/ Overrun Error Abbreviation TXI TEI RXI STPI NAKI Interrupt Condition (TDRE=1) * (TIE=1) (TEND=1) * (TEIE=1) (RDRF=1) * (RIE=1) (STOP=1) * (STIE=1) {(NACKF=1)+(AL=1)} * (NAKIE=1) When an exception processing is executed under interrupt conditions described in table 21.3, interrupt sources should be cleared in the exception processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive data of one byte may be transmitted. The DTC can be activated by a TXI interrupt request to transfer data. The TDRE flag is automatically cleared upon data transfer by the DTC. The DTC can also be activated by an RXI interrupt request to transfer data. The RDRF flag is automatically cleared to 0 upon data transfer by the DTC. Rev. 1.00 Oct. 03, 2008 Page 764 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.5 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be shortened in the two states described below. * When SCL is driven to low by the slave device * When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 21.21 shows the timing of the bit synchronous circuit and table 21.4 shows the time when SCL output changes from low to Hi-Z and then SCL is monitored. SCL monitor timing reference clock SCL VIH Internal SCL Figure 21.21 The Timing of the Bit Synchronous Circuit Table 21.4 Time for Monitoring SCL CKS3 0 CKS2 0 1 1 0 1 Time for Monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc Rev. 1.00 Oct. 03, 2008 Page 765 of 962 REJ09B0465-0100 Section 21 I C Bus Interface 2 (IIC2) 2 21.6 21.6.1 Usage Notes SCL and SDA pins selected by PMC This LSI incorporates the IIC2 and SSU modules, one of which module functions should be selected by the SELICSU bit in ICSUSR. Therefore, when assigning the pin functions using the peripheral function mapping controller (PMC), the SCL and SDA pin functions should be assigned to the P56 and P57 pins when the IIC2 function is selected. If these pin functions are assigned to other pins, correct operation cannot be guaranteed. 21.6.2 Restriction on Use of Bit Manipulation Instructions to Set MST and TRS in MultiMaster Usage When master transmission is selected by consecutively manipulating the MST and TRS bits in multi-master usage, an arbitration loss during execution of the bit-manipulation instruction for TRS leads to the contradictory situation where AL in ICSR is 1 in master transmit mode (MST = 1, TRS = 1). Ways to avoid this effect are listed below. * Use the MOV instruction to set MST and TRS when used in multi-master mode. * When arbitration is lost, confirm that MST = 0 and TRS = 0. If the setting of MST = 0 and TRS = 0 is not confirmed, then set MST = 0 and TRS = 0 again. Rev. 1.00 Oct. 03, 2008 Page 766 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) Section 22 Synchronous Serial Communication Unit (SSU) Note: In this section, the synchronous serial communication unit is abbreviated as SSU for convenience. The synchronous serial communication unit (SSU) can handle clocked synchronous serial data communication. Figure 22.1 shows a block diagram of the SSU. Either the SSU or IIC2 incorporated in this LSI can be used at a time. Accordingly, when the SSU function is used, the IIC2 function is not available. 22.1 Features * Can be operated in clocked synchronous communication mode or four-line bus communication mode (including bidirectional communication mode) * Can be operated as a master or a slave device * Choice of seven internal clocks (/256, /128, /64, /32, /16, /8, /4) and an external clock as a clock source * Clock polarity and phase of SSCK can be selected * Choice of data transfer direction (MSB-first or LSB-first) * Receive error detection: overrun error * Multimaster error detection: conflict error * Five interrupt sources: transmit-end, transmit-data-empty, receive-data-full, overrun error, and conflict error. The DTC can be activated by the transmit-data-empty and receive-data-full interrupts. * The transmitter and receiver with buffer structure allow continuous transmission and reception of serial data. Rev. 1.00 Oct. 03, 2008 Page 767 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) Internal clock SSCK Multiplexer SSMR SSMR2 SSCRL SCS SSER SSSR SSTDR SSO SSI Selector SSTRSR SSRDR Interrupt request (TXI, TEI, RXI, OEI, CEI) Figure 22.1 Block Diagram of SSU Table 22.1 shows the pin configuration of the SSU. Table 22.1 Pin Configuration Pin Name SSCK SSI SSO SCS I/O I/O I/O I/O I/O Function SSU clock input/output SSU data input/output SSU data input/output SSU chip select input/output Rev. 1.00 Oct. 03, 2008 Page 768 of 962 REJ09B0465-0100 Internal data bus Transmission/ reception control circuit SSCRH Section 22 Synchronous Serial Communication Unit (SSU) 22.2 Register Descriptions The SSU has the following registers. * * * * * * * * * * IIC2/SSU select register (ICSUSR) SS control register H (SSCRH) SS control register L (SSCRL) SS mode register (SSMR) SS mode register 2 (SSMR2) SS enable register (SSER) SS status register (SSSR) SS receive data register (SSRDR) SS transmit data register (SSTDR) SS shift register (SSTRSR) 22.2.1 IIC2/SSU Select Register (ICSUSR) Address: H'FF000B Bit: b7 b6 b5 b4 b3 b2 b1 b0 SELICSU 0 Value after reset: 0 0 0 0 0 0 0 Bit Symbol Bit Name Reserved Description These bits are read as 0. The write value should be 0. R/W R/W 7 to 1 0 Note: SELICSU * IIC2/SSU module 0: IIC2 function is selected. function select 1: SSU function is selected.* To select the SSU function, this bit should be set to 1 without fail. Rev. 1.00 Oct. 03, 2008 Page 769 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.2.2 SS Control Register H (SSCRH) Address: H'FF05C8 Bit: b7 b6 RSSTP 0 b5 MSB 0 b4 b3 b2 b1 CKS[2:0] b0 Value after reset: 0 0 0 0 0 0 Bit 7 6 5 4, 3 Symbol RSSTP MSS Bit Name Reserved Receive single stop Master/slave device select Reserved Transfer clock rate select Description This bit is read as 0. The write value should be 0. 0: After receiving 1 byte of data, reception continues. 1: After receiving 1 byte of data, reception ends.* 0: Operates as a slave device 1: Operates as a master device R/W R/W R/W These bits are read as 0. The write value should be 0. 000: /256 001: /128 010: /64 011: /32 100: /16 101: /8 110: /4 111: Reserved R/W 2 to 0 CKS[2:0] Note: * The setting of the RSSTP bit is invalid when the MSS bit is cleared to 0. * MSS bit (master/slave device select) Selects whether this module is used as a master device or a slave device. When this module is used as a master device, transfer clock is output from the SSCK pin. When the CE bit in SSSR is set, this bit is automatically cleared. * CKS[2:0] bits (transfer clock rate select) Sets transfer clock rate (prescaler division ratio) when the internal clock is selected. Rev. 1.00 Oct. 03, 2008 Page 770 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.2.3 SS Control Register L (SSCRL) Address: H'FF05C9 Bit: b7 b6 b5 SOL 1 b4 SOLP 1 b3 b2 b1 SRES 0 b0 Value after reset: 0 1 1 1 1 Bit 7 6 5 Symbol SOL*1 Bit Name Reserved Reserved Serial data output level setting Description This bit is read as 0. The write value should be 0. This bit is read as 1. The write value should be 1. 0: When reading, serial data output level is low. When writing, serial data output level is changed to low. 1: When reading, serial data output level is high. When writing, serial data output level is changed to high. R/W R/W 4 SOLP SOL write protect 0: When writing, output level can be changed according to the value of the SOL bit. 1: When reading, this bit is always read as 1. When writing, modifying to the SOL bit is invalid. 3, 2 1 0 Note: SRES Reserved Software reset Reserved These bits are read as 1. The write value should be 1. 0: Does not reset. 1: The SSU internal sequencer is forcibly reset.* 2 This bit is read as 1. The write value should be 1. 1. When the output level is changed, the SOLP bit (bit4) should be cleared to 0 and the MOV instruction should be used. If this bit is written during data transfer, erroneous operation may occur. Therefore this bit must not be manipulated during transmission. 2. This bit should always be cleared by software as this bit is not cleared automatically. Rev. 1.00 Oct. 03, 2008 Page 771 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) * SOL bit (serial data output level setting) Although the value in the last bit of transmit data is retained in the serial data output after the end of transmission, the output level of serial data can be changed by manipulating this bit before or after transmission. * SOLP bit (SOL write protect) When output level of serial data is changed, the MOV instruction is used to set the SOL bit to 1 and clear this bit to 0 or to clear the SOL bit and this bit to 0. * SRES bit (software reset) When this bit is set to 1, the SSU internal sequencer is forcibly reset. The register value in the SSU is retained. Rev. 1.00 Oct. 03, 2008 Page 772 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.2.4 SS Mode Register (SSMR) Address: H'FF05CA Bit: b7 MLS b6 CPOS 0 b5 CPHS 0 b4 b3 b2 b1 BC[2:0] b0 Value after reset: 0 1 1 0 0 0 Bit 7 6 5 4, 3 Symbol MLS CPOS CPHS Bit Name Description R/W R/W R/W R/W R/W MSB-first/LSB- 0: Transfer by MSB-first first select 1: Transfer by LSB-first Clock polarity select Clock phase select Reserved 0: SSCK clock idling state = high 1: SSCK clock idling state = low 0: Data change at first edge 1: Data latch at first edge This bit is read as 1. The write value should be 1. 2 to 0 BC[2:0] Bit counter 2 to 000: 8 bits 0 001: 1 bit 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits * BC[2:0] bits (bit counter 2 to 0) When read, the remaining number of transfer bits is indicated. Rev. 1.00 Oct. 03, 2008 Page 773 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.2.5 SS Mode Register 2 (SSMR2) Address: H'FF05CD Bit: b7 BIDE b6 SCKS 0 0 b5 CSS[1:0] 0 b4 b3 SCKOS 0 b2 SOOS 0 b1 CSOS 0 b0 SSUMS 0 Value after reset: 0 Bit 7 Symbol BIDE Bit Name Bidirectional mode enable Description 0: Normal mode. Communication is performed by using two pins. 1: Bidirectional mode. Communication is performed by using only one pin. R/W R/W 6 5, 4 SCKS CSS[1:0] SSCK pin select 0: Functions as a port*1 1: Functions as a serial clock pin R/W R/W SCS pin select 00: Functions as a port*1 01: Functions as an SCS input 1X: Functions as an SCS output (however, functions as an SCS input before starting transfer) 3 SCKOS SSCK pin open-drain output select 0: CMOS output 1: NMOS open-drain output* 2 R/W 2 SOOS SSO pin open- 0: CMOS output 2 drain output 1: NMOS open-drain output* select SCS pin opendrain output select 0: CMOS output 1: NMOS open-drain output* 2 R/W 1 CSOS R/W Rev. 1.00 Oct. 03, 2008 Page 774 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) Bit 0 Symbol SSUMS Bit Name SSU mode select Description 0: Clocked synchronous communication mode Data input: SSI pin, Data output: SSO pin 1: Four-line bus communication mode When MSS = 1 in SSCRH and BIDE = 0 in SSMR2: Data input: SSI pin, Data output: SSO pin When MSS = 0 in SSCRH and BIDE = 0 in SSMR2: Data input: SSO pin, Data output: SSI pin When BIDE = 1 in SSMR2: Data input and output: SSO pin R/W R/W [Legend] X: Don't care. Note: 1. To function these pins as ports, clear the PMR bit corresponding to the pin to 0. 2. If the NMOS open-drain output is selected, use the PMC to allocate the pin from port 5. If the pin is allocated from a port other than port 5, only the CMOS output can be selected. * BIDE bit (bidirectional mode enable) Selects whether the serial data input pin and the output pin are both used or only one pin is used. For details, see section 22.3.3, Relationship between Data Input/Output Pin and Shift Register. When the SSUMS bit in SSMR2 is 0, this setting is invalid. * SCKS bit (SSCK pin select) Selects whether the SSCK pin functions as a port or a serial clock pin. * CSS[1:0] bits (SCS pin select) Selects whether the SCS pin functions as a port, an SCS input, or SCS output. When the SSUMS bit in SSMR2 is 0, the SCS pin functions as a port regardless of the setting of this bit. * SOOS bit (SSO pin open-drain output select) Selects whether the serial data output pin is CMOS output or NMOS open-drain output. The serial data output pin is changed according to the register setting value. For details, see section 22.3.3, Relationship between Data Input/Output Pin and Shift Register. * SSUMS bit (SSU mode select) Selects which combination of the serial data input pin and serial data output pin is used. For details, see section 22.3.3, Relationship between Data Input/Output Pin and Shift Register. Rev. 1.00 Oct. 03, 2008 Page 775 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.2.6 SS Enable Register (SSER) Address: H'FF05CB Bit: b7 TIE b6 TEIE 0 b5 RIE 0 b4 TE 0 b3 RE 0 b2 b1 b0 CEIE 0 Value after reset: 0 0 0 Bit 7 6 5 4 3 2, 1 0 Note: Symbol TIE TEIE RIE TE* RE* CEIE * Bit Name Description R/W R/W R/W Transmit interrupt 0: A TXI interrupt request is disabled. enable 1: A TXI interrupt request is enabled. Transmit end interrupt enable 0: A TEI interrupt request is disabled. 1: A TEI interrupt request is enabled. Receive interrupt 0: An RXI and an OEI interrupt requests are disabled. R/W enable 1: An RXI and an OEI interrupt requests are enabled. Transmit enable Receive enable Reserved Conflict error interrupt enable 0: Transmit operation is disabled. 1: Transmit operation is enabled. 0: Receive operation is disabled. 1: Receive operation is enabled. These bits are read as 0. The write value should be 0. 0: A CEI interrupt request is disabled. 1: A CEI interrupt request is enabled. R/W R/W R/W The TE and RE bits are reset in standby mode. Rev. 1.00 Oct. 03, 2008 Page 776 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.2.7 SS Status Register (SSSR) Address: H'FF05CC Bit: b7 TDRE b6 TEND 0 b5 RDRF 0 b4 b3 b2 ORER 0 b1 b0 CE 0 Value after reset: 0 0 0 0 Bit 7 Symbol TDRE Bit Name Transmit data empty flag Description [Setting conditions] * * When the TE bit in SSER is 0 When data transfer is performed from SSTDR to SSTRSR and data can be written in SSTDR When 0 is written to this bit after reading 1 When data is written in SSTDR When the DTC transfers data to SSTDR by a TXI interrupt request, and the DTC settings satisfy the flag clearing conditions.* R/W R/W [Clearing conditions] * * * 6 TEND Transmit end flag [Setting condition] * When the last bit of data is transmitted, the TDRE bit is 1 When 0 is written to this bit after reading 1 When data is written in SSTDR R/W [Clearing conditions] * * 5 RDRF Receive data [Setting condition] R/W register full flag * When serial reception is completed normally and receive data is transferred from SSTRSR to SSRDR [Clearing conditions] * * * When 0 is written to this bit after reading 1 When data is read from SSRDR When the DTC transfers data to SSRDR by an RXI interrupt request, and the DTC settings satisfy the flag clearing conditions.* Rev. 1.00 Oct. 03, 2008 Page 777 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) Bit 4, 3 2 Symbol ORER Bit Name Reserved Description These bits are read as 0. The write value should be 0. * R/W R/W Overrun error flag [Setting condition] When the next serial reception is completed while RDRF = 1 When 0 is written to this bit after reading 1 [Clearing condition] * 1 0 CE Reserved These bits are read as 0. The write value should be 0. * R/W Conflict error flag [Setting conditions] When serial communication is started while SSUMS = 1 in SSMR2 and MSS = 1 in SSCRH, the SCS pin input is low When the SCS pin level changes from low to high during transfer while SSUMS = 1 in SSMR2 and MSS = 0 in SSCRH When 0 is written to this bit after reading 1 * [Clearing condition] * Notes: In standby mode, SSSR is reset. * The DTC clears the peripheral module flags when all of the following three conditions are satisfied. 1. When the DISEL bit is 0. 2. When the transfer counter (DTC transfer count register A (CRA) in normal mode and repeat mode, or DTC transfer count register B (CRB) in block mode) is not 0. 3. When chain transfer is not used. * ORER bit (overrun error flag) Indicates that the RDRF bit is abnormally terminated in reception because an overrun error has occurred. SSRDR retains received data before the overrun error occurs and the received data after the overrun error occurs is lost. When this bit is set to 1, subsequent serial reception cannot be continued. When the MSS bit in SSCRH is 1, this is also applied to serial transmission. Rev. 1.00 Oct. 03, 2008 Page 778 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.2.8 SS Receive Data Register (SSRDR) Address: H'FF05CF Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 SSRDR is an 8-bit register that stores received serial data. When the SSU has received one byte of serial data, it transfers the received serial data from SSTRSR to SSRDR to end receive operation. After this, SSTRSR is receive-enabled. As SSTRSR and SSRDR function as a double buffer in this way, continuous receive operations are possible. SSRDR is a read-only register and cannot be written to by the CPU. SSRDR is initialized to H'FF. In standby mode, SSRDR is initialized. 22.2.9 SS Transmit Data Register (SSTDR) Address: H'FF05CE Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 SSTDR is an 8-bit register that stores serial data for transmission. SSTDR can be read or written to by the CPU at all times. When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has already been written to SSTDR during serial transmission, continuous serial transmission is possible. SSTDR is initialized to HFF. In standby mode, SSTDR is initialized. Rev. 1.00 Oct. 03, 2008 Page 779 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.2.10 SS Shift Register (SSTRSR) Address: Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: SSTRSR is a shift register that transmits and receives serial data. When transmit data is transferred from SSTDR to SSTRSR, bit 0 in SSTDR is transferred to bit 0 in SSTRSR while the MLS bit in SSMR is 0 (LSB-first transfer) and bit 7 in SSTDR is transferred to bit 0 in SSTRSR while the MLS bit in SSMR is 1 (MSB-first transfer). SSTRSR cannot be directly accessed by the CPU. In standby mode, SSTRSR is initialized. 22.3 22.3.1 Operation Transfer Clock Transfer clock can be selected from seven internal clocks and an external clock. When this module is used, the SSCK pin must be selected as a serial clock by setting the SCKS bit in SSMR2 to 1. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is in the output state. If transfer is started, the SSCK pin outputs clocks of the transfer rate set in the CKS2 to CKS0 bits in SSCRH. When the MSS bit is 0, an external clock is selected and the SSCK pin is in the input state. 22.3.2 Relationship between Clock Polarity and Phase, and Data Relationship between clock polarity and phase, and transfer data changes according to a combination of the SSUMS bit in SSMR2 and the CPOS and CPHS bits in SSMR. Figure 22.2 shows the relationship. MSB-first transfer or LSB first transfer can be selected by the setting of the MLS bit in SSMR. When the MLS bit is 0, transfer is started from LSB to MSB. When the MLS bit is 1, transfer is started from MSB to LSB. Rev. 1.00 Oct. 03, 2008 Page 780 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) (1) When CPHS = 0, CPOS =0, and SSUMS = 0: SSCK SSO, SSI Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (2) When CPHS = 0 and SSUMS = 1: SSCK (CPOS = 0) SSCK (CPOS = 1) SSO, SSI SCS (3) When CPHS = 1 and SSUMS = 1: SSCK (CPOS = 0) SSCK (CPOS = 1) SSO, SSI SCS Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 22.2 Relationship between Clock Polarity and Phase, and Data Rev. 1.00 Oct. 03, 2008 Page 781 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.3.3 Relationship between Data Input/Output Pin and Shift Register Relationship of connection between the data input/output pin and SSTRSR changes according to a combination of the MSS bit in SSCRH and the SSUMS bit in SSMR2. It also changes by the BIDE bit in SSMR2. Figure 22.3 shows the relationship. (1) When SSUMS = 0: (2) When SSUMS = 1, BIDE = 0, and MSS = 1: Shift register (SSTRSR) SSO Shift register (SSTRSR) SSO SSI SSI (3) When SSUMS = 1, BIDE = 0, and MSS = 0: (4) When SSUMS = 1 and BIDE = 1: Shift register (SSTRSR) SSO Shift register (SSTRSR) SSO SSI SSI Figure 22.3 Relationship between Data Input/Output Pin and Shift Register Rev. 1.00 Oct. 03, 2008 Page 782 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.3.4 Communication Modes and Pin Functions The SSU switches functions of the input/output pin in each communication mode according to the settings of the MSS bit in SSCRH and the RE and TE bits in SSER. Table 22.2 shows the relationship between communication modes and the input/output pins. In bidirectional communication mode, the TE and RE bits should not be set to 1 at the same time. Table 22.2 Relationship between Communication Modes and Input/Output Pins Communication Mode Clocked Synchronous Communication Mode Register State SSUMS 0 BIDE * MSS 0 TE 0 1 RE 1 0 1 1 0 1 1 0 1 Four-Line Bus Communication Mode 1 0 0 0 1 1 0 1 1 0 1 1 0 1 Four-Line Bus (Bidirectional) Communication Mode 1 1 0 0 1 1 0 1 [Legend] : Can be used as a general I/O port. 1 0 1 0 SSI In In In In Out Out In In Pin State SSO Out Out Out Out In In Out Out In Out In Out SSCK In In In Out Out Out In In In Out Out Out In In Out Out Rev. 1.00 Oct. 03, 2008 Page 783 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.3.5 (1) Operation in Clocked Synchronous Communication Mode Initialization in Clocked Synchronous Communication Mode Figure 22.4 shows the initialization in clocked synchronous communication mode. Before transmitting and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be initialized. Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF and ORER flags, or the contents of SSRDR. Start Clear TE and RE bits in SSER to 0 Clear SSUMS bit in SSMR2 to 0 Clear CPOS and CPHS bits in SSMR to 0 and set MLS and CKS2 to CKS0 bits in SSCRH Set SCKS bit in SSMR2 to 1 and set MSSS bit in SOOS and SSCRH Clear ORER bit in SSSR to 0 Set the TE and RE bits in SSER to 1 and set RIE, TIE and TEIE bits, and RSSTP bit in SSCRH according to transmission/reception/transmission and reception End Figure 22.4 Initialization in Clocked Synchronous Communication Mode Rev. 1.00 Oct. 03, 2008 Page 784 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) (2) Serial Data Transmission Figure 22.5 shows an example of the SSU operation for transmission. In serial transmission, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is set as a slave device, it outputs data in synchronized with the input clock. When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is generated. When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is fixed high. While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before transmission. Figure 22.6 shows a sample flowchart for serial data transmission. SSCK SSO Bit 0 Bit 1 One frame Bit 7 Bit 0 Bit 1 One frame Bit 7 TDRE TEND LSI Operation TXI generated TXI generated TEI generated User processing Write data in SSTDR Write data in SSTDR Figure 22.5 Example of Operation in Data Transmission Rev. 1.00 Oct. 03, 2008 Page 785 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) Start Initialization [1] Read TDRE bit in SSSR No TDRE = 1? Yes Write transmit data in SSTDR [1] After reading SSSR and confirming that the TDRE bit is 1, write transmit data in SSTDR. Then the TDRE bit is automatically cleared to 0. [2] Data transmission continued? Yes [2] Determine whether data transmission is continued. No [3] Read TEND bit in SSSR [3] Read 1 from the TEND bit in SSSR to confirm that data transmission is completed. After the TEND bit is set to 1, clear the TEND bit and TE bit in SSER to 0 and transmit mode is ended. No TEND = 1? Yes Clear TEND bit and TE bit in SSER to 0 End Figure 22.6 Sample Serial Transmission Flowchart Rev. 1.00 Oct. 03, 2008 Page 786 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) (3) Serial Data Reception Figure 22.7 shows an example of the SSU operation for reception. In serial reception, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a slave device, it inputs data in synchronized with the input clock. When the SSU is set as a master device, it outputs a receive clock and starts reception by performing dummy read on SSRDR. After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in SSRDR. If the RIE bit in SSER is set to 1 at this time, a RXI is generated. If SSRDR is read, the RDRF bit is automatically cleared to 0. When the SSU is set as a master device and reception is ended, received data is read after setting the RSSTP bit in SSCRH to 1. Then the SSU outputs eight bits of clocks and operation is stopped. After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if SSRDR is read while the RE bit is set to 1, received clock is output again. When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1, reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before reception. Figure 22.8 shows a sample flowchart for serial data reception. SSCK SSO Bit 0 One frame Bit 7 Bit 0 One frame Bit 7 Bit 0 Bit 7 RDRF RSSTP LSI operation User processing Dummy read on SSRDR RXI generated Read data in SSRDR RXI generated Set RSSTP to 1 Read data in SSRDR RXI generated Figure 22.7 Example of Operation in Data Reception (MSS = 1) Rev. 1.00 Oct. 03, 2008 Page 787 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) Start Initialization [1] Dummy read on SSRDR [1] After setting each register in the SSU, dummy read on SSRDR is performed and reception is started. Yes [2] Determine whether the last one byte of data is received. When the last one byte of data is received, set to stop reception after the data is received. [2] Last reception? No Read ORER [3] ORER = 1? No Read RDRF Yes [4] No RDRF = 1? Yes Read receive data in SSRDR [3][6] When a receive error occurs, clear the ORER flag to 0 after the ORER flag in SSSR is read and an appropriate error processing is performed. When the ORER flag is set to 1, transmission/reception cannot be started again. [4] Confirm that the RDRF bit is 1. If the RDRF bit is 1, receive data in SSRDR is read. If the SSRDR bit is read, the RDRF bit is automatically cleared. [5] Set RSSTP to 1 [5] Before the last one byte of data is received, set the RSSTP bit to 1 and reception is stopped after the data is received. Read ORER Yes ORER = 1? No Read RDRF [7] Confirm that the RDRF bit is 1. To end reception, clear the RE and RSSTP bits to 0 and then read the last receive data. If the SSRDR bit is read before clearing the RE bit, reception is started again. Overrun error processing [6] No [7] RDRF = 1? Yes RE = 0, RSSTP = 0 Read receive data in SSRDR End Figure 22.8 Sample Serial Reception Flowchart (MSS = 1) Rev. 1.00 Oct. 03, 2008 Page 788 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) (4) Serial Data Transmission and Reception Data transmission and reception is a combined operation of data transmission and reception which are described before. Transmission and reception is started by writing data in SSTDR. When the eighth clock rises while the TDRE bit is set to 1 or the ORER bit is set to 1, transmission and reception is stopped. To switch from transmit mode (TE = 1) or receive mode (RE = 1) to transmit and receive mode (TE = RE = 1), the TE and RE bits should be cleared to 0. After confirming that the TEND, RDRF, and ORER bits are cleared to 0, set the TE and RE bits to 1. When the module is released from transmit and receive mode (TE = 1 and RE = 1), setting TE = 0 (and RE = 1) after the SSRDR has been read can cause output of the clock signal. For this reason, start by setting RE = 0 and only set TE = 0 after that (or set both RE = 0 and TE = 0 at the same time). When TE = 0 and RE = 1 is subsequently set, only set RE = 1 after changing SRES from 1 to 0. Figure 22.9 shows a sample flowchart for serial transmit and receive operations. Rev. 1.00 Oct. 03, 2008 Page 789 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) Start Initialization [1] Read TDRE in SSSR No TDRE = 1? Yes Write transmit data in SSTDR [1] After reading SSSR and confirming that the TDRE bit is 1, write transmit data in SSTDR. Then the TDRE bit is automatically cleared to 0. [2] Read RDRF in SSSR No RDRF = 1? Yes Read receive data in SSRDR Yes [2] Confirm that the RDRF bit is 1. If the RDRF bit is 1, receive data in SSRDR is read. If the SSRDR bit is read, the RDRF bit is automatically cleared. [3] Data transmission continued? [3] Determine whether data transmission is continued. No Clear TEND to 0 and clear TE and RE in SSER to 0 [4] [4] To end transmit and receive mode, clear the TEND bit to 0 and clear the TE and RE bits in SSER to 0. End Figure 22.9 Sample Flowchart for Serial Transmit and Receive Operations Rev. 1.00 Oct. 03, 2008 Page 790 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.3.6 Operation in Four-Line Bus Communication Mode Four-line bus communication mode is a mode which communicates with the four-line bus; a clock line, a data input line, a data output line, and a chip select line. This mode includes bidirectional mode in which the data input line and the data output line function as a single pin. The data input line and the data output line are changed according to the settings of the MSS bit in SSCRH and BIDE bit in SSMR2. For details, see section 22.3.3, Relationship between Data Input/Output Pin and Shift Register. In this mode, relationship between clock polarity and phase, and data can be set by the CPOS and CPHS bits in SSMR. For details, see section 22.3.2, Relationship between Clock Polarity and Phase, and Data. When the SSU is set as a master device, the chip select line controls output. When the SSU is set as a slave device, the chip select line controls input. When the SSU is set as a master device, the chip select line controls output of the SCS pin or controls output of a general port by setting the CSS1 bit in SSMR2 to 1. When the SSU is set as a slave device, the chip select line sets the SCS pin as an input pin by setting the CSS1 and CSS0 bits in SSMR2 to 01. In four-line bus communication mode, the MLS bit in SSMR is set to 1 and transfer is performed in MSB-first order. (1) Initialization in Four-Line Bus Communication Mode Figure 22.10 shows the initialization in four-line bus communication mode. Before transmitting and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be initialized. Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. Note that clearing the RE bit to 0 does not change the contents of the RDRF and ORER flags, or the contents of SSRDR. Rev. 1.00 Oct. 03, 2008 Page 791 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) Start Clear TE and RE in SSER to 0 Set SSUMS in SSMR2 to 1 [1] Set MLS in SSMR to 1 and set CPOS and CPHS, and CKS2 to CKS0 inSSCRH [1] The MLS bit is set to 1 for MSB-first transfer. The clock polarity and phase are set in the CPOS and CPHS bits. [2] Set SCKS in SSMR2 to 1 and set BIDE, SOOS, CSS1and CSS0, and MSS in SSCRH [2] In bidirectional mode, the BIDE bit is set to 1 and input/output of the SCS pin is set by the CSS1 and CSS0 bits. Clear ORER in SSSR to 0 Set TE and RE in SSER to 1 and set RIE, TIE and TEIE, and RSSTP in SSCRH according to transmission/ reception/transmission and reception End Figure 22.10 Initialization in Four-Line Bus Communication Mode Rev. 1.00 Oct. 03, 2008 Page 792 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) (2) Serial Data Transmission Figure 22.11 shows an example of the SSU operation for transmission. In serial transmission, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is set as a slave device, the SCS pin is in the low-input state and the SSU outputs data in synchronized with the input clock. When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is generated. When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is fixed high and the SCS pin goes high. When continuous transmission is performed with the SCS pin low, the next data should be written to SSTDR before transmitting the eighth bit of the frame. While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before transmission. The difference between this mode and clocked synchronous communication mode is as follows: when the SSU is set as a master device, the SSO pin is in the high impedance state if the SCS pin is in the high impedance state and when the SSU is set as a slave device, the SSI pin is in the high impedance state if the SCS pin is in the high-input state. The sample flowchart for serial data transmission is the same as that in clocked synchronous communication mode. Rev. 1.00 Oct. 03, 2008 Page 793 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) (1) When CPOS = 0 and CPHS = 0: SCS (output) SSCK (High impedance) SSO Bit 7 Bit 6 One frame Bit 0 Bit 7 Bit 6 One frame Bit 0 TDRE TEND LSI operation TXI generated TXI generated TEI generated User processing Write data in SSTDR Write data in SSTDR (2) When CPOS = 0 and CPHS = 1: SCS (output) SSCK (High impedance) SSO Bit 7 Bit 6 One frame Bit 0 Bit 7 Bit 6 One frame Bit 0 TDRE TEND LSI operation TXI generated TXI generated TEI generated User processing Write data in SSTDR Write data in SSTDR Figure 22.11 Example of Operation in Data Transmission (MSS = 1) Rev. 1.00 Oct. 03, 2008 Page 794 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) (3) Serial Data Reception Figure 22.12 shows an example of the SSU operation for reception. In serial reception, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a slave device, the SCS pin is in the low-input state and inputs data in synchronized with the input clock. When the SSU is set as a master device, it outputs a receive clock and starts reception by performing dummy read on SSRDR. After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in SSRDR. If the RIE bit in SSER is set to 1 at this time, an RXI is generated. If SSRDR is read, the RDRF bit is automatically cleared to 0. When the SSU is set as a master device and reception is ended, received data is read after setting the RSSTP bit in SSER to 1. Then the SSU outputs eight bits of clocks and operation is stopped. After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if SSRDR is read while the RE bit is set to 1, received clock is output again. When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1, reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before reception. The set timings of the RDRF and ORER flags differ according to the CPHS setting. These timings are shown in figure 22.2. When the CPHS bit is set to 1, the flag is set during the frame. Therefore care should be taken at the end of reception. The sample flowchart for serial data reception is the same as that in clocked synchronous communication mode. Rev. 1.00 Oct. 03, 2008 Page 795 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) (1) When CPOS = 0 and CPHS = 0: SCS (output) SSCK (High impedance) SSI Bit 7 One frame Bit 0 Bit 7 One frame Bit 0 Bit 7 Bit 0 RDRF RSSTP LSI operation RXI generated RXI generated RXI generated User processing Dummy read on SSRDR Read data in SSRDR Set RSSTP to 1 Read data in SSRDR (2) When CPOS = 0 and CPHS = 1: SCS (output) SSCK (High impedance) SSI Bit 7 One frame Bit 0 Bit 7 One frame Bit 0 Bit 7 Bit 0 RDRF RSSTP LSI operation RXI generated RXI generated RXI generated User processing Dummy read on SSRDR Read data in SSRDR Set RSSTP to 1 Read data in SSRDR Figure 22.12 Example of Operation in Data Reception (MSS = 1) Rev. 1.00 Oct. 03, 2008 Page 796 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.3.7 SCS Pin Control and Arbitration When the SSUMS bit in SSMR2 is set to 1 and the CSS1 bit is set to 1, the MSS bit in SSCRH is set to 1 and then the arbitration of the SCS pin is checked before starting serial transfer. If the SSU detects that the synchronized internal SCS pin goes low in this period, the CE bit in SSSR is set and the MSS bit in SSCRH is cleared. Note: When a conflict error is set, subsequent transmit operation is not possible. Therefore the CE bit must be cleared to 0 before starting transmission. When the multimaster error is used, the CSOS bit in SSMR2 should be set to 1. SCS input Internal SCS (synchronized) MSS Transfer start Write data in SSTDR CE (Hi-Z) SCS output Maximum time of SCS internal synchronization Arbitration detection period Figure 22.13 Arbitration Check Timing Rev. 1.00 Oct. 03, 2008 Page 797 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.4 Interrupt Requests The SSU has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the common vector address, interrupt sources must be determined by flags. Table 22.3 lists the interrupt requests. Table 22.3 Interrupt Requests Interrupt Request Transmit data empty Transmit end Receive data full Overrun error Conflict error Abbreviation TXI TEI RXI OEI CEI Interrupt Condition (TIE = 1), (TDRE = 1) DTC Activation Possible (TEIE = 1), (TEND = 1) Impossible (RIE = 1), (RDRF = 1) (RIE = 1), (ORER = 1) (CEIE = 1), (CE = 1) Possible Impossible Impossible When an interrupt exception handling by an interrupt source shown in table 22.4 is executed, each interrupt source must be cleared during the exception handling. Note that the TDRE and TEND bits are automatically cleared by writing transmit data in SSTDR and the RDRF bit is automatically cleared by reading SSRDR. When transmit data is written in SSTDR, the TDRE bit is set again at the same time. Then if the TDRE bit is cleared, additional one byte of data may be transmitted. The DTC can be activated by a TXI interrupt to transfer data. The TDRE flag is automatically cleared upon data transfer by the DTC. The DTC can also be activated by an RXI interrupt to transfer data. The RDRF flag is automatically cleared upon data transfer by the DTC. Rev. 1.00 Oct. 03, 2008 Page 798 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) 22.5 (1) Usage Notes If the NMOS open-drain output is selected for the SSCK output pin, the SSO output pin, and the SCS output pin, use the PMC to allocate that pin from port 5. If the pins are allocated from a port other than port 5, only the CMOS output is available. Rev. 1.00 Oct. 03, 2008 Page 799 of 962 REJ09B0465-0100 Section 22 Synchronous Serial Communication Unit (SSU) Rev. 1.00 Oct. 03, 2008 Page 800 of 962 REJ09B0465-0100 Section 23 Hardware LIN Section 23 Hardware LIN The hardware LIN works in cooperation with timer RA and SCI3_1 to provide LIN communications. 23.1 Overview * Master mode Generates Sync Break. Detects bus conflicts. * Slave mode Detects Sync Break. Measures Sync Field. Controls Sync Break and Sync Field signal inputs to SCI3_1. Detects bus conflicts. Figure 23.1 shows a block diagram of the hardware LIN interface. Hardware LIN RXD pin Sync Field controller Timer RA Timer RA TIOSEL = 0 RXD data LSTART bit SBE bit LINE bit RXD input controller TIOSEL = 1 Timer RA underflow signal Interrupt controller Bus conflict detector Timer RA Timer RA interrupt SCI3_1 BCIE, SBIE, and SFIE bits SCI3_1 transfer clock SCI3_1 TE bit Timer RA output pulse MST bit TXD pin SCI3_1 TXD data Figure 23.1 Block Diagram of Hardware LIN Rev. 1.00 Oct. 03, 2008 Page 801 of 962 REJ09B0465-0100 Section 23 Hardware LIN Table 23.1 shows the hardware LIN pins. Table 23.1 Pin Configuration Pin Symbol RXD TXD I/O Input Output Description Receive-data input to the hardware LIN Transmit-data output from the hardware LIN 23.2 Register Configuration The hardware LIN interface has the following registers. * LIN control register (LINCR) * LIN status register (LINST) 23.2.1 LIN Control Register (LINCR) Address: H'FF0518 Bit: b7 LINE Value after reset: 0 b6 MST 0 b5 SBE 0 b4 LSTART 0 b3 RXDSF 0 b2 BCIE 0 b1 SBIE 0 b0 SFIE 0 Bit 7 6 Symbol LINE MST Bit Name LIN start LIN operating 2 mode setting* RXD input mask cancellation timing select Description 0: Enables LIN operation. 1: Disables LIN operation.* 1 R/W R/W R/W 0: Slave mode (Enables the Sync Break detector.) 1: Master mode (Takes the OR between timer RA output and TXD data.) (Valid only in slave mode) 0: Cancels the mask upon Sync Break detection. 1: Cancels the mask upon completion of Sync Field measurement. 5 SBE R/W Rev. 1.00 Oct. 03, 2008 Page 802 of 962 REJ09B0465-0100 Section 23 Hardware LIN Bit 4 3 2 Symbol LSTART RXDSF BCIE Bit Name Sync Break detection start RXD input status flag Description 0: Don't care. 1: Enables timer RA input and disables RXD input. 0: Indicates that RXD input has been enabled. 1: Indicates that RXD input has been disabled. R/W R/W R R/W Bus conflict 0: Disables a bus conflict detection interrupt. detection 1: Enables a bus conflict detection interrupt. interrupt enable Sync Break 0: Disables a Sync Break detection interrupt. detection 1: Enables a Sync Break detection interrupt. interrupt enable Sync Field measurement end interrupt enable 0: Disables a Sync Field measurement end interrupt. 1: Enables a Sync Field measurement end interrupt. 1 SBIE R/W 0 SFIE R/W Note: 1. Immediately after setting this bit to 1, inputs to timer RA and SCI3_1 are prohibited. 2. Before switching the LIN operating modes, temporarily disable the LIN (LINE = 0). 3. After setting LSTART and then checking that the RXDSF flag is 1, start inputting Sync Break. Rev. 1.00 Oct. 03, 2008 Page 803 of 962 REJ09B0465-0100 Section 23 Hardware LIN 23.2.2 LIN Status Register (LINST) Address: H'FF0519 Bit: b7 b6 b5 B2CLR 0 b4 B1CLR 0 b3 B0CLR 0 b2 BCDCT 0 b1 SBDCT 0 b0 SFDCT 0 Value after reset: 0 0 Bit 7, 6 5 Symbol B2CLR Bit Name Reserved BCDCT flag clear Description These bits are read as 0. The write value should be 0. The BCDCT flag is cleared when 1 is written to this bit. This bit is always read as 0. The SBDCT flag is cleared when 1 is written to this bit. This bit is always read as 0. The SFDCT flag is cleared when 1 is written to this bit. This bit is always read as 0. 0: No bus conflict is detected. 1: Indicates that bus conflict has been detected. 0: Sync Bread is not detected. 1: Indicates that Sync Break has been detected. 0: Sync Field measurement is not ended. 1: Indicates that Sync Field measurement has been ended. R/W R/W 4 B1CLR SBDCT flag clear R/W 3 B0CLR SFDCT flag clear R/W 2 1 0 BCDCT SBDCT SFDCT Bus conflict detection flag Sync Break detection flag Sync Field measurement end flag R R R Rev. 1.00 Oct. 03, 2008 Page 804 of 962 REJ09B0465-0100 Section 23 Hardware LIN 23.3 23.3.1 Operation Master Mode Figure 23.2 shows the example of hardware LIN interface operation for transmitting the header field in master mode. Figures 23.3 and 23.4 show the flowcharts for header field transmission. The hardware LIN interface operates as follows for header field transmission. 1. When 1 is written to the TSTART bit in TRACR register of timer RA, the hardware LIN keeps outputting a low level from the TXD pin for the period specified by the TRAPRE and TRATR registers of timer RA. 2. When timer RA underflows, the hardware LIN inverts the TXD pin output, thus setting the SBDCT flag in the LINST register to 1. In this case, if the SBIE bit in the LINCR register is set to 1, the timer RA/HW-LIN interrupt occurs. 3. The hardware LIN interface transmits H'55 using SCI3_1. 4. After completing H'55 transmission, the hardware LIN interface transmits the ID field using SCI3_1. 5. After completing ID field transmission, the hardware LIN interface performs response field communications. Sync Break Sync Field IDENTIFIER TXD pin 1 0 Write 1 to the B1CLR bit in LINST. SBDCT flag in LINST 1 0 Timer RA/ HW-LIN interrupt 1 0 1. 2. 3. 4. 5. Note: The following conditions are assumed: LINE = 1, MST = 1, SBIE =1. Figure 23.2 Example of LIN Operation for Transmitting Header Field Rev. 1.00 Oct. 03, 2008 Page 805 of 962 REJ09B0465-0100 Section 23 Hardware LIN Timer RA Set to timer mode by setting the TMOD[2:0] bits in the TRAMR register to b'000. Timer RA Set the TEDGSEL bit in the TRAIOC register to 1 to set the initial timer pulse output level to low. Timer RA Set the TRAIO pin to RXD by setting the TIOSEL bit in the TRAIOC register to 1. For the hardware LIN function, set the TIOSEL bit in the TRAIOC register to 1. Timer RA Select the count source by setting the TCK[2:0] bits in the TRAMR register. Timer RA Set the Sync Break width by setting the TRAPRE and TRATR registers. Set the count source, TRAPRE register, and TRATR register appropriately for the Sync Break width. Hardware LIN Stop operation by setting the LINE bit in the LINCR register to 0. Hardware LIN Set to master mode by setting the MST bit in the LINCR register to 1. Hardware LIN Start operation by setting the LINE bit in the LINCR register to 1. Hardware LIN Clear the status flags (bus conflict detection, Sync Break detection, and Sync Field measurement end) by setting the B2CLR, B1CLR, and B0CLR bits in the LINST register to 0. The Sync Field measurement end interrupt cannot be used in master mode. Hardware LIN Enable/disable the interrupts (bus conflict detection and Sync Break detection) by setting the BCIE and SBIE bits in the LINCR register. A Figures 23.3 Header Field Transmission Flowchart (1) Rev. 1.00 Oct. 03, 2008 Page 806 of 962 REJ09B0465-0100 Section 23 Hardware LIN A Timer RA Start the timer counter by setting the TSTART bit in the TRACR register to 1. Timer RA Read the count status flag (TCSTF) from the TRACR register. Generate Sync Break by timer RA. After writing 1 to the TSTART bit, reading 1 from the TCSTF flag can be omitted if neither TRAPRE register nor TRATR register of timer RA is read or modified. TCSTF = 1? Yes No Hardware LIN Read the Sync Break detection flag (SBDCT) from the LINST register. No The timer RA interrupt can be used upon completion of Sync Break generation. SBDCT = 1? Yes Timer RA Read the Sync Break detection flag (SBDCT) from the LINST register. Timer RA Stop the timer counter by setting the TSTART bit in the TRACR register to 0. No After generating timer RA Sync Break, stop the timer counter. After writing 0 to the TSTART bit, reading 0 from the TCSTF flag can be omitted if neither TRAPRE register nor TRATR register of timer RA is read or modified. TC STF = 0? Yes SCI3_1 Initialize SCI3_1 and set asynchronous mode, transmission, and clock source by setting the SCR3, SMR, and BRR registers. SCI3_1 Perform communications using SCI3_1. Read 1 from the TDRE bit in the SSR register. Transfer H'55 to TDR register. SCI3_1 Perform communications using SCI3_1. Transfer the ID field to TDR register. Initialize SCI3 following the initialization procedure and set the appropriate clock source for Sync Field transmission. Transmit the Sync Field. Transmit the ID field. Figures 23.4 Header Field Transmission Flowchart (2) Rev. 1.00 Oct. 03, 2008 Page 807 of 962 REJ09B0465-0100 Section 23 Hardware LIN 23.3.2 Slave Mode Figure 23.5 shows the example of hardware LIN interface operation for receiving the header field in slave mode. Figures 23.6 to 23.8 show the flowcharts for header field reception. The hardware LIN interface operates as follows for header field reception. 1. When 1 is written to the LSTART bit in LINCR register of the hardware LIN interface, Sync Break detection is enabled. 2. When a low level input is longer than the time set in timer RA, it is detected as Sync Break, thus setting the SBDCT flag in the LINST register to 1. In this case, if the SBIE bit in the LINCR register is set to 1, the timer RA/HW-LIN interrupt occurs. The hardware LIN interface then measures the Sync Field. 3. The hardware LIN interface receives the Sync Field (H'55). During reception, the hardware LIN interface measures the time from the start bit through bit 6. Here, the Sync Field input to the SCI3 RXD can be either enabled or disabled depending on the SBE bit setting in the LINCR register. 4. Completion of Sync Field measurement sets the SFDCT flag in the LINST register to 1. In this case, if the SFIE bit in the LINCR register is 1, the timer RA/HW-LIN interrupt occurs. 5. After completing Sync Field measurement, the hardware LIN interface calculates the transfer rate from the timer RA count value and sets the rate in SCI3_1, and also updates the TRAPRE and TRATR registers in timer RA. Then the hardware LIN interface receives the ID field using SCI3_1. 6. After completing ID field reception, the hardware LIN interface performs response field communications. Rev. 1.00 Oct. 03, 2008 Page 808 of 962 REJ09B0465-0100 Section 23 Hardware LIN Sync Break Sync Field IDENTIFIER RXD pin "1" "0" "1" "0" RXD input to SCI3_1 Write 1 to the LSTART bit in LINCR. RXDSF flag in LINCR "1" "0" Write 1 to the B1CLR bit in LINST. Automatically cleared to 0 after Sync Field measurement. SBDCT flag in LINST "1" "0" Measure this period. Write 1 to the B0CLR bit in LINST. SFDCT flag in LINST "1" "0" Timer RA/ "1" HW-LIN interrupt "0" 1. Note: The following conditions are assumed: LINE = 1, MST = 0, SBE = 1, SBIE =1, SFIE = 1. 2. 3. 4. 5. 6. Figure 23.5 Example of LIN Operation for Receiving Header Field Rev. 1.00 Oct. 03, 2008 Page 809 of 962 REJ09B0465-0100 Section 23 Hardware LIN Timer RA Set to pulse width measurement mode by setting the TMOD[2:0] bits in the TRAMR register to b'011. Timer RA Set the TEDGSEL bit in the TRAIOC register to 0 to measure the low level width of pulses. For the hardware LIN function, set the TIOSEL bit in the TRAIOC register to 1. Timer RA Set the TRAIO pin to RXD by setting the TIOSEL bit in the TRAIOC register to 1. Timer RA Select the count source by setting the TCK[2:0] bits in the TRAMR register. Set the count source, TRAPRE register, and TRATR register appropriately for the Sync Break width. Timer RA Set the Sync Break width by setting the TRAPRE and TRATR registers. Hardware LIN Stop operation by setting the LINE bit in LINCR register to 0. Hardware LIN Set to slave mode by setting the MST bit in LINCR register to 0. Hardware LIN Start operation by setting the LINE bit in the LINCR register to 1. Select the mask cancellation timing of the RXD input to SCI3_1. When a timing is selected such that the mask is cancelled upon Sync Break detection, the Sync Field signal is also input to SCI3_1. Hardware LIN Select the RXD input mask cancellation timing (upon Sync Break detection or completion of Sync Field measurement) by setting the SBE bit in the LINCR register. Hardware LIN Clear the status flags (bus conflict detection, Sync Break detection, and Sync Field measurement end) by setting the B2CLR, B1CLR, and B0CLR bits in the LINST register to 1. A Figures 23.6 Header Field Reception Flowchart (1) Rev. 1.00 Oct. 03, 2008 Page 810 of 962 REJ09B0465-0100 Section 23 Hardware LIN A Hardware LIN Enable/disable the interrupts (bus conflict detection, Sync Break detection, and Sync Field measurement end) by setting the BCIE, SBIE, and SFIE bits in the LINCR register. Timer RA Start pulse width measurement by setting the TSTART bit in the TRACR register to 1. Timer RA Read the count status flag (TCSTF) from the TRACR register. No Wait until timer RA starts counting. TCSTF = 1? Yes Hardware LIN Start Sync Break detection by setting the LSTART bit in the LINCR register to 1. Hardware LIN Read the RXD input status flag (RXDSF) from the LINCR register. No Wait until the RXD input to SCI3_1 is masked by the hardware LIN. After writing 1 to the LSTART bit, do not input a low level to the RXD pin until 1 is read from the RXDSF flag; during this period, the low level input is directly input to the SCI3_1. After 1 is read from the RXDSF flag, input to timer RA and SCI3_1 is possible. RXDSF = 1? Yes Hardware LIN Read the Sync Break detection flag (SBDCT) from the LINST register. No SBDCT = 1? Yes B Detect the hardware LIN Sync Break. The timer RA interrupt can be used. When Sync Break is detected, the timer RA counter is reloaded with the initially set value. If the low level input is shorter than the specified time, the timer RA counter is also reloaded with the initially set value and waits for another low level input. When the SBE bit in the LINCR register is 0 (the input mask is cancelled upon Sync Break detection), timer RA can be used in timer mode after the SBDCT flag in the LINST register becomes 1. Figure 23.7 Header Field Reception Flowchart (2) Rev. 1.00 Oct. 03, 2008 Page 811 of 962 REJ09B0465-0100 Section 23 Hardware LIN B Yes Hardware LIN Read the Sync Field measurement end flag (SFDCT) from the LINST register. No SFDCT = 1? Yes Calculate the hardware LIN Sync Field. The timer RA/HW-LIN interrupt can be used. (When the timer RA counter underflows, the SBDCT flag is set). When the SBE bit in the LINCR register is 1 (the input mask is cancelled upon completion of Sync Break measurement), timer RA can be used in timer mode after the SFDCT flag in the LINST register becomes 1. SCI3_1 Set the SCI3_1 transfer rate by setting the BRR register. Timer RA Update the Sync Break width by setting the TRAPRE and TRATR registers. SCI3_1 Perform communications using SCI3_1. Receive the ID field in clock asynchronous serial interface (UART) mode. Set the appropriate transfer rate according to the Sync Field measurement results. Perform communications using SCI3_1 (when the timer RA counter underflows, the SBDCT flag is set). Figure 23.8 Header Field Reception Flowchart (3) Rev. 1.00 Oct. 03, 2008 Page 812 of 962 REJ09B0465-0100 Section 23 Hardware LIN 23.3.3 Bus Conflict Detection Function The hardware LIN interface can detect bus conflicts if SCI3_1 is enabled for transmission (TE bit in SCR3_1 register is 1). Figure 23.9 shows the example of hardware LIN interface operation for detecting bus conflicts. TXD pin "1" "0" RXD pin "1" "0" "1" "0" Set to 1 through programming. Transfer clock LINE bit in LINCR "1" "0" Set to 1 through programming. TE bit in "1" SCR3_1 register "0" Write 1 to the B2CLR bit in LINST. BCDCT flag in LINST "1" "0" Timer RA/ "1" HW-LIN "0" interrupt TRAIF Figure 23.9 Example of LIN Operation for Detecting Bus Conflicts Rev. 1.00 Oct. 03, 2008 Page 813 of 962 REJ09B0465-0100 Section 23 Hardware LIN 23.3.4 Terminating Hardware LIN Figure 23.10 shows the flowchart for terminating hardware LIN communications. The hardware LIN interface should be terminated at the following timing. * Case 1: When the bus conflict detection function is used After checksum field transmission * Case 2: When the bus conflict detection function is not used After header field transmission/reception Timer RA Stop the timer counter by setting the TSTART bit in the TRACR register to 0. Timer RA Read the count status flag (TCSTF) from the TRACR register. No Stop the timer counter. TCSTF = 0? Yes SCI3_1 Terminate SCI3_1 communications. When the bus conflict detection function is not used, SCI3_1 transmission does not need to be terminated. Hardware LIN Clear the status flags (bus conflict detection, Sync Break detection, and Sync Field measurement end) by setting the B2CLR, B1CLR, and B0CLR bits in the LINST register to 1. Hardware LIN Stop operation by setting the LINE bit in LINCR register to 0. Before stopping the hardware LIN, clear the status flags of the hardware LIN. Figure 23.10 Flowchart for Terminating Hardware LIN Communications Rev. 1.00 Oct. 03, 2008 Page 814 of 962 REJ09B0465-0100 Section 23 Hardware LIN 23.4 Interrupt Requests The hardware LIN interface can request four types of interrupts: Sync Break detection, Sync Break generation end, Sync Field measurement end, and bus conflict detection. All these interrupts are requested as the timer RA interrupt. Table 23.2 describes these interrupt requests. Table 23.2 Interrupt Requests by Hardware LIN Interrupt Request Sync Break detection Status Flag SBDCT Interrupt Source * The low-level period of the RXD input is measured using timer RA and the counter underflows The low-level period of the RXD input is longer than the Sync Break period during communications. * Sync Break generation end Sync Field measurement end Bus conflict detection SFDCT BCDCT The low level has been output via TXD for the period specified by timer RA. Measuring the 8-bit Sync Field period has been completed using timer RA. The RXD input and TXD output values differ from each other when data is latched while SCI3_1 is enabled for transmission. 23.5 Usage Note For processing the header and response field timeout, measure the time from the Sync Break detection interrupt using another timer. Rev. 1.00 Oct. 03, 2008 Page 815 of 962 REJ09B0465-0100 Section 23 Hardware LIN Rev. 1.00 Oct. 03, 2008 Page 816 of 962 REJ09B0465-0100 Section 24 A/D Converter Section 24 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter (one unit or two units) that allows up to sixteen analog input channels to be selected. Figures 24.1 and 24.2 show the block diagrams of A/D converters unit 1 and unit 2, respectively. The differences between unit 1 and unit 2 are the number of analog input channels and the number of data registers. The other functions of units 1 and 2 are the same. 24.1 Features * 10-bit resolution * Input channels Unit 1: 12 channels for the H8S/20223 and H8S/20203 groups and 8 channels for the H8S/20103 group Unit 2: 4 channels for the H8S/20223 group * Conversion time: 2 s per channel (at 20 MHz operation) * Operating modes: Two A/D conversion mode: A selected analog input is A/D converted Compare mode: A selected analog input is compared with the voltage specified by the user * Channel select modes Single mode: Single-channel A/D conversion or comparison Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels * Data registers: 8 data registers for unit 1 and 4 data registers for unit 2 Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of conversion start Conversion can be started by software, conversion start trigger by 16-bit timer (timer RC or RD), or external trigger signal. * Interrupt request A/D conversion end interrupt (ADI) request can be generated Compare result change interrupt (CMPI) request can be generated * Module standby function can be set Rev. 1.00 Oct. 03, 2008 Page 817 of 962 REJ09B0465-0100 Section 24 A/D Converter Successive approximations register AVcc 10-bit D/A AVss ADDR2/CMPVALH ADDR3/CMPVALL ADDR1/CMPCSR ADDR0/CMPR ADCSR ADDR4 ADDR5 ADDR6 ADDR7 + AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Comparator Multiplexer Control circuit Sample-and-hold circuit AAZB CMPI interrupt signal ADI interrupt signal Conversion start trigger from timer RC or RD ADTRG1 Figure 24.1 Block Diagram of A/D Converter (Unit 1) Rev. 1.00 Oct. 03, 2008 Page 818 of 962 REJ09B0465-0100 ADMR ADCR Bus interface Module data bus Internal data bus Section 24 A/D Converter ADDR2_2/CMPVALH_2 ADCSR_2 10-bit D/A AVss + AN0_2 AN1_2 AN2_2 AN3_2 Multiplexer Comparator Control circuit Sample-and-hold circuit ADMR_2 ADCR_2 AVcc ADDR1_2/CMPCSR_2 ADDR3_2/CMPVALL_2 Successive aproximations register ADDR0_2/CMPR_2 Conversion start trigger from timer RC or RD ADTRG2 Figure 24.2 Block Diagram of A/D Converter (Unit 2) Rev. 1.00 Oct. 03, 2008 Page 819 of 962 REJ09B0465-0100 Bus interface CMPI interrupt signal AD interrupt signal Module data bus Internal data bus Section 24 A/D Converter Table 24.1 shows the pin configuration of the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. Unit 1 has 12 analog input pins; unit 2 has four analog input pins. Note that the actual number of analog inputs in units 1 and 2 depends on the product group. Table 24.1 Pin Configuration Unit Common Pin Name AVCC AVSS Unit 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 ADTRG1 Unit 2 AN0_2 AN1_2 AN2_2 AN3_2 ADTRG2 I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input 2 for starting A/D conversion External trigger input 1 for starting A/D conversion Unit 2 group 0 analog inputs*2 Unit 1 group 2 analog inputs*1 Unit 1 group 1 analog inputs Function Analog block power supply Analog block ground Unit 1 group 0 analog inputs Notes: 1. Not supported in the H8S/20103 and H8S/20203 groups. 2. Supported only in the H8S/20223 group. Rev. 1.00 Oct. 03, 2008 Page 820 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.2 Register Description The A/D converter has the following registers. Unit 1: * * * * * * * * * * * * * * * A/D data register 0 (ADDR0) A/D data register 1 (ADDR1) A/D data register 2 (ADDR2) A/D data register 3 (ADDR3) A/D data register 4 (ADDR4) A/D data register 5 (ADDR5) A/D data register 6 (ADDR6) A/D data register 7 (ADDR7) A/D control/status register (ADCSR) A/D control register (ADCR) A/D mode register (ADMR) Compare data register (CMPR) Compare control status register (CMPCSR) Compare voltage register H (CMPVALH) Compare voltage register L (CMPVALL) Unit 2: * * * * * * * * * * * A/D data register 0_2 (ADDR0_2) A/D data register 1_2 (ADDR1_2) A/D data register 2_2 (ADDR2_2) A/D data register 3_2 (ADDR3_2) A/D control/status register_2 (ADCSR_2) A/D control register_2 (ADCR_2) A/D mode register_2 (ADMR_2) Compare data register_2 (CMPR_2) Compare control status register_2 (CMPCSR_2) Compare voltage register H_2 (CMPVALH_2) Compare voltage register L_2 (CMPVALL_2) Rev. 1.00 Oct. 03, 2008 Page 821 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.2.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7) Address: H'FF05E0 to H'FF05EE, H'FF0600 to H'FF0606 Bit: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 - b4 - 0 b3 - 0 b2 - 0 b1 - 0 b0 - 0 Value after reset: 0 0 0 0 0 0 0 0 0 0 0 ADDR registers are 16-bit read-only registers which are used to store the results of A/D conversion. Unit 1 incorporates eight registers ADDR0 to ADDR7. Unit 2 incorporates four registers ADDR0_2 to ADDR3_2. The ADDR registers, which store a conversion result for each channel, are shown in table 24.2. The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter is 16-bit width. Data can be accessed in 16 bits at one time or 8 bits at two times. Table 24.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Channel Set 0 (CH3 = 0) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Channel Set 1 (CH3 = 1) AN8 AN9 AN10 AN11 A/D Data Register which Stores Conversion Result ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 Rev. 1.00 Oct. 03, 2008 Page 822 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.2.2 A/D Control/Status Register (ADCSR) Address: H'FF05F0, H'FF0610 Bit: b7 ADF b6 ADIE 0 b5 ADST 0 b4 b3 b2 CH[3:0] b1 b0 Value after reset: 0 0 0 0 0 0 Bit 7 Symbol ADF Bit Name A/D end flag Description 0: A/D conversion or comparison is in progress. 1: A/D conversion or comparison has been completed. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode When 0 is written after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read R/W R/W* [Clearing conditions] * * 6 5 ADIE ADST A/D interrupt enable A/D start 0: Disables an ADF interrupt. 1: Enables an ADF interrupt. 0: Stops A/D conversion and places the A/D converter in the wait state. 1: Starts A/D conversion. This bit is read as 0. The write value should be 0. R/W R/W 4 Reserved bit R/W 3 to 0 CH[3:0] Channel select When SCANE = 0 and SCANS = x 3 to 0 0000: AN0 0111: AN7 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 1000: AN8 1001: AN9 1010: AN10 1011: AN11 11xx: Setting prohibited Rev. 1.00 Oct. 03, 2008 Page 823 of 962 REJ09B0465-0100 Section 24 A/D Converter Bit Symbol Bit Name Description R/W R/W 3 to 0 CH[3:0] Channel select When SCANE = 1 and SCANS = 0 3 to 0 0000: AN0 0111: AN4 to AN7 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4 and AN5 0110: AN4 to AN6 When SCANE = 1 and SCANS = 1 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN0 to AN4 0101: AN0 to AN5 0110: AN0 to AN6 0111: AN0 to AN7 1000: AN8 1001: AN8 and AN9 1010: AN8 to AN10 1011: AN8 to AN11 11xx: Setting prohibited 1000: AN8 1001: AN8 and AN9 1010: AN8 to AN10 1011: AN8 to AN11 11xx: Setting prohibited [Legend] x: Don't care. Notes: * Only 0 can be written in bit 7, to clear the flag. 1. The A/D converter should be stopped (ADST = 0) while the Input channels are being selected. 2. In unit 2, channels can be selected from four channels AN0_2 to AN3_2. Accordingly, the CH3 and CH2 bits should be cleared to 0 in unit 2. * ADST bit (A/D start) Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. When this bit is set to 1 by software, timer RC, timer RD (conversion start trigger), or the ADTRG pin, A/D conversion starts. This bit remains set to 1 during A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel ends. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by a reset, a transition to standby mode or software. ADST is cleared to 0 if A/D conversion of all the selected channels has been completed while the ADSTCLR bit is 1. The event link function can be used to set the ADST bit. When the event specified in ELSR10 or ELS11 of the ELC occurs, the corresponding ADST bits (in A/D converter unit 1 or A/D converter unit 2, respectively) are set and the A/D conversion starts. Rev. 1.00 Oct. 03, 2008 Page 824 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.2.3 A/D Control Register (ADCR) Address: H'FF05F0, H'FF0611 Bit: b7 TRGS[1:0] b6 b5 SCANE 0 0 b4 SCANS 0 1 b3 CKS[1:0] 0 b2 b1 ADSTCLR 0 b0 EXTRGS 0 Value after reset: 0 Bit 7, 6 Symbol TRGS[1:0] Bit Name Description R/W R/W Trigger select 1 b0 b7 b6 and 0 0 0 0: A/D conversion start by external trigger is disabled. 0 0 1: A/D conversion start by external trigger pin 1 (ADTRG1) is enabled. 0 1 0: A/D conversion start by external trigger pin 1 2 (ADTRG2) is enabled.* 0 1 1: A/D conversion start by external trigger 2 (timer RC) is enabled.* 1 0 0: A/D conversion start by external trigger (timer RD_0) is enabled. 1 0 1: A/D conversion start by external trigger (timer RD_1) is enabled.*3 1 1 x: Reserved (setting prohibited) 5 4 SCANE SCANS Channel 0x: Single mode selection mode 10: Scan mode (A/D conversion is performed continuously for channels 1 to 4) 11: Scan mode (A/D conversion is performed continuously for channels 1 to 8.) R/W 3, 2 CKS[1:0]*4 Clock select 1 to 0 00: Setting prohibited 01: Setting prohibited 10: A/D conversion time = 84 states (max) (initial value) 11: A/D conversion time = 43 states (max) R/W 1 ADSTCLR ADST clear If ADSTCLR is set to 1 in scan mode, the ADST bit R/W is automatically cleared to 0 when A/D conversion of all the selected channels has been completed. R/W 0 EXTRGS External trigger EXTRGS combined with the TRGS1 and TRGS0 select bits selects a trigger signal. For details, see the above description for the TRGS1 and TRGS0 bits. Rev. 1.00 Oct. 03, 2008 Page 825 of 962 REJ09B0465-0100 Section 24 A/D Converter [Legend] x: Don't care. Note: 1. Selected only for the H8S/20223 group. 2. Selected only for the H8S/20103 group. 3. Not selected only for the H8S/20103 group. 4. Select these bits to fall the conversion time within the specified time. * TRGS[1:0] bits (trigger select 1 and 0) These bits combined with the EXTRGS bit select enable or disable the A/D conversion start by a trigger signal. * CKS[1:0] bits (clock select 1 to 0) These bits the A/D conversion time. The conversion time should be set while the A/D conversion is stopped (ADST = 0). Rev. 1.00 Oct. 03, 2008 Page 826 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.2.4 A/D Mode Register (ADMR) Address: H'FF05F4, H'FF0614 Bit: b7 b6 b5 ADM1 0 b4 b3 b2 b1 b0 Value after reset: 0 0 0 0 0 0 0 Bit 7, 6 5 Symbol ADM1 Bit Name Reserved A/D converter operating mode selection All 0 Description These bits are read as 0. The write value should be 0. 0: A/D conversion mode 1: Compare mode These bits are read as 0. The write value should be 0. R/W R/W 4 to 0 Note: The A/D converter operating mode should be changed while the ADST bit in ADCSR is 0. * ADM1 bit (A/D conversion mode selection) If the A/D converter operating mode changes from conversion mode to compare mode, CMPR, CMPCSR, and CMPVAL are initialized to H'00. Rev. 1.00 Oct. 03, 2008 Page 827 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.2.5 Compare Data Register (CMPR) Address: H'FF05E0, H'FF0600 Bit: b7 CMP7 b6 CMP6 0 b5 CMP5 0 b4 CMP4 0 b3 CMP3 0 b2 CMP2 0 b1 CMP1 0 b0 CMP0 0 Value after reset: 0 Bit 7 6 5 4 3 2 1 0 Symbol CMP7 CMP6 CMP5 CMP4 CMP3 CMP2 CMP1 CMP0 Bit Name Compare data 7 Compare data 6 Compare data 5 Compare data 4 Compare data 3 Compare data 2 Compare data 1 Compare data 0 Description [Setting condition] When the voltage of the selected analog input channel is greater than the voltage set in the CMPVAL register in compare mode. [Clearing conditions] * R/W R R R When the A/D converter operating mode is changed from A/D conversion mode to compare R mode according to the ADM bit in ADMR R setting. When the voltage of the selected analog input channel is equal to or lower than the voltage set R in the CMPVAL register in compare mode. R R * [Legend] x: Don't care. Note: * Only 0 can be written to clear the flag. CMPR holds the comparison result. CMPR is a read-only register that is assigned to the same address as ADDR0 and ADDR0_2. CMPR is valid in compare mode. Rev. 1.00 Oct. 03, 2008 Page 828 of 962 REJ09B0465-0100 Section 24 A/D Converter CMP bits and the corresponding analog input channels are shown in table 24.3. Table 24.3 Relationship between CMP Bits and Corresponding Analog Input Channels Unit Unit 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Unit 2 AN0_2 AN1_2 AN2_2 AN3_2 Channel AN8 AN9 AN10 AN11 Corresponding Compare Data Bit CMP0 CMP1 CMP2 CMP3 CMP4 CMP5 CMP6 CMP7 CMP0 CMP1 CMP2 CMP3 Rev. 1.00 Oct. 03, 2008 Page 829 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.2.6 Compare Control Status Register (CMPCSR) Address: H'FF05E2, H'FF0602 Bit: b7 CMPF b6 CMPIE 0 b5 CMPFC1 0 b4 CMPFC0 0 b3 0 b2 0 b1 0 b0 0 Value after reset: 0 Bit 7 Symbol CMPF Bit Name CMPI interrupt status Description [Setting condition] If the condition specified by the CMPFC1 or CMPFC0 bit is satisfied when comparison has been completed. [Clearing conditions] * When the A/D converter operating mode is changed from A/D conversion mode to compare mode according to the ADM bit in ADMR setting. When 0 is written to this bit after this bit is read as 1. When the DTC is activated by a CMPI interrupt and the DISEL bit in MRB of the DTC is 0. When this LSI enters standby mode or module standby mode. R/W R/W * * * 6 CMPIE CMPI interrupt enable 0: Disables a compare match interrupt (CMPI). 1: Enables a compare match interrupt (CMPI). R/W Rev. 1.00 Oct. 03, 2008 Page 830 of 962 REJ09B0465-0100 Section 24 A/D Converter Bit 5 Symbol CMPFC1 Bit Name CMPI interrupt condition 1 Description 0: Does not generate an interrupt by a comparison result change. 1: In single compare mode: Sets the CMPF bit to 1 if the comparison result of the selected channel changes from 0 to 1. In scan compare mode: Sets the CMPF bit to 1 if the comparison result of any of the selected channels changes from 0 to 1. R/W R/W 4 CMPFC0 CMPI interrupt condition 0 0: Does not generate an interrupt by a comparison result change. 1: In single compare mode: Sets the CMPF bit to 1 if the comparison result of the selected channel changes from 0 to 1. In scan compare mode: Sets the CMPF bit to 1 if the comparison result of any of the selected channels changes from 0 to 1. R/W 3 to 0 Reserved These bits are read as 0. The write value should be 0. Rev. 1.00 Oct. 03, 2008 Page 831 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.2.7 CMPVALH Compare Analog Level Registers H and L (CMPVALH and CMPVALL) Address: H'FF05E4, H'FF0604 Bit: b7 b6 b5 b4 b3 b2 b1 VAL9 0 b0 VAL8 0 Value after reset: CMPVALL 0 0 0 0 0 0 Address: H'FF05E6, H'FF0606 Bit: b7 VAL7 Value after reset: 0 b6 VAL6 0 b5 VAL5 0 b4 VAL4 0 b3 VAL3 0 b2 VAL2 0 b1 VAL1 0 b0 VAL0 0 * CMPVALH Bit Symbol Bit Name Reserved Description This bit is read as 0. The write value should be 0. These bits set the compare voltage VAL[9:8]. R/W R/W R/W 7 to 2 1 0 VAL9 VAL8 * CMPVALL Bit 7 6 5 4 3 2 1 0 Symbol VAL7 VAL6 VAL5 VAL4 VAL3 VAL2 VAL1 VAL0 Bit Name Description These bits set the compare voltage VAL[7:0]. R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00 Oct. 03, 2008 Page 832 of 962 REJ09B0465-0100 Section 24 A/D Converter CMPVALL and the lower 2 bits of CMPVALH specify the voltage to be compared. CMPVALH and CMPVALL are assigned to the same addresses as ADDR2 (ADDR2_2) and ADDR3 (ADDR3_2), respectively. CMPVALH and CMPVALL become valid in compare mode. Table 24.4 shows the correspondence between VAL[9:0] setting and the voltage to be compared. Table 24.4 VAL[9:0] Setting and Corresponding Voltage to be Compared VAL[9:0] Setting B'0000000000 B'0000000001 B'0000000010 : B'111111100 B'111111101 B'111111110 B'111111111 Voltage to be Compared AVss AVcc x 1/1024 AVcc x 2/1024 : AVcc x 1020/1024 AVcc x 1021/1024 AVcc x 1022/1024 AVcc x 1023/1024 Rev. 1.00 Oct. 03, 2008 Page 833 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.3 Operation The A/D converter operates in two operating modes as shown in table 24.5. In A/D conversion mode, the A/D converter converts the analog input of the selected channel by successive approximation with 10-bit resolution. In compare mode, the analog input of the selected channel is compared with the voltage to be specified. Each operating mode has two operating modes: single mode and scan mode. When changing the analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. Table 24.5 A/D Converter Operating Mode Operating Mode A/D conversion mode Channel Selection Mode Single mode Scan mode Compare mode Single mode Scan mode Register Setting ADM1 = 0, SCANE = 0 ADM1 = 0, SCANE = 1 ADM1 = 1, SCANE = 0 ADM1 = 1, SCANE = 1 Rev. 1.00 Oct. 03, 2008 Page 834 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.4 24.4.1 A/D Conversion Mode Operation Single Mode in A/D Conversion Mode In single mode in A/D conversion mode, A/D conversion is to be performed only once on the specified single channel. Operations are as follows. 1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to the software or external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters wait state. Rev. 1.00 Oct. 03, 2008 Page 835 of 962 REJ09B0465-0100 Section 24 A/D Converter Set* ADIE ADST ADF Channel 0 (AN0) operating status Channel 1 (AN1) operating status Channel 2 (AN2) operating status Channel 3 (AN3) operating status ADDR0 ADDR1 ADDR2 ADDR3 Conversion result read A/D conversion result 1 Conversion result read A/D conversion start Set* Clear* Set* Clear* Wait for A/D conversion Wait for A/D conversion Wait for A/D conversion A/D conversion 1 A/D conversion 2 Wait for A/D conversion Wait for A/D conversion Wait for A/D conversion A/D conversion result 2 Note: * At , an instruction is executed by software. Figure 24.3 A/D Converter Operation in A/D Conversion Mode (When Channel 1 Is Selected in Single Mode) Rev. 1.00 Oct. 03, 2008 Page 836 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.4.2 Scan Mode in A/D Conversion Mode In scan mode in A/D conversion mode, A/D conversion is to be performed sequentially on the specified channels: maximum four channels or maximum eight channels. Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by a software, timer RC, timer RD or external trigger input, A/D conversion starts on the first channel of the channel set. The consecutive A/D conversion on maximum four channels (SCANE = 1 and SCANS = 0) or on maximum eight channels (SCANE = 1 and SCANS = 1) can be selected. When the consecutive A/D conversion is performed on the four channels, the A/D conversion starts on AN0 when CH3 = 0 and CH2 =0, AN4 when CH3 = 0 and CH2 = 1, or AN8 when CH3 = 1 and CH2 = 0. When the consecutive A/D conversion is performed on the eight channels, the A/D conversion starts on AN0 when CH3 = 0 and CH2 = 0. 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. The A/D conversion starts again from the first channel of the channel set again. 4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from the first channel of the channel set. Rev. 1.00 Oct. 03, 2008 Page 837 of 962 REJ09B0465-0100 Section 24 A/D Converter A/D conversion is performed sequentially. Set*1 ADST ADF A/D conversion time Channel 0 (AN0) operating status Channel 1 (AN1) operating status Channel 2 (AN2) operating status Channel 3 (AN3) operating status Transfer ADDR0 ADDR1 ADDR2 ADDR3 Notes: 1. At , an instruction is executed by software. 2. Data to be converted is ignored. A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Wait for A/D conversion Clear*1 Clear*1 A/D conversion 1 Wait for A/D conversion A/D conversion 2 A/D conversion 4 Wait for A/D conversion A/D conversion 5 *2 Wait for A/D conversion Wait for A/D conversion Wait for A/D conversion A/D conversion 3 Wait for A/D conversion Wait for A/D conversion Wait for A/D conversion Figure 24.4 A/D Converter Operation in A/D Conversion Mode (When AN0 to AN2 Channels are Selected in Scan Mode) Rev. 1.00 Oct. 03, 2008 Page 838 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.5 24.5.1 Compare Mode Operation Single Mode in Compare Mode In single mode in compare mode, the analog input of one selected channel is compared with the specified voltage. Operations are as follows. The setting of the channel by the CH[3:0] bits in ADCSR is the same as that in A/D conversion mode. 1. Comparison between the analog input of the selected channel and the voltage specified by the VAL[9:0] bits is started when the ADST bit in ADCSR is set to 1 by software or external trigger input. 2. When the comparison is completed, the result is transferred to a bit corresponding to the channel. 3. On completion of comparison, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. In addition, if a condition specified by the CMPFC1 or CMPFC0 bit is satisfied, the CMPF bit in CMPCSR is set to 1. If the CMPIE bit is set to 1 at this time, a CMPI interrupt is requested. 4. The ADST bit remains set to 1 during comparison, and is automatically cleared to 0 when comparison ends. When the ADST bit is cleared to 0 during comparison, the A/D converter stops operation and enters wait state. ADST ADF AN0 Comparison voltage input Wait for comparison VAL[9:0] Specified voltage CMP0 in CMPR Previous comparison result Comparison result Figure 24.5 A/D Converter Operation in Compare Mode (When Channel 0 Is Selected in Single Mode) Rev. 1.00 Oct. 03, 2008 Page 839 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.5.2 Scan Mode in Comparison Mode In scan mode in comparison mode, the analog input of the selected channels (four or eight maximum) are compared sequentially with the specified voltage. Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by a software, timer RC, timer RD or external trigger input, comparison between the analog input of the selected channels and the voltage specified by the VAL[9:0] bits is started. The comparison on maximum four channels (SCANE = 1 and SCANS= 0) or on maximum eight channels (SCANE = 1 and SCANS= 1) can be selected. When the consecutive comparison is performed on the four channels, the comparison starts on AN0 when CH3 = 0 and CH2 = 0, AN4 when CH3 = 0 and CH2 = 1, or AN8 when CH3 = 1 and CH2 = 0. When the consecutive comparison is performed on the eight channels, the comparison starts on AN0 when CH3 = 0 and CH2 = 0. 2. When comparison for each channel is completed, the result is sequentially transferred to a bit corresponding to each channel. 3. When comparison of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. In addition, if a condition specified by the CMPFC1 or CMPFC0 bits is satisfied in any of the selected channels, the CMPF bit in CMPCSR is set to 1. If the CMPIE bit is set to 1 at this time, a CMPI interrupt is requested. The A/D converter starts comparison from the first channel of the channel set. 4. The ADST bit is not cleared automatically when ADSTCLR = 0, and steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0 during comparison, the A/D converter stops operation and enters wait state. If the ADST bit is later set to 1, the A/D converter starts comparison from the first channel of the channel set. Rev. 1.00 Oct. 03, 2008 Page 840 of 962 REJ09B0465-0100 Section 24 A/D Converter ADST ADF AN0 Comparison voltage input Wait for comparison AN1 Wait for comparison Comparison voltage input Wait for comparison VAL[9:0] Specified voltage CMP0 in CMPR Previous comparison result Comparison result CMP1 in CMPR Previous comparison result Comparison result Figure 24.6 A/D Converter Operation in Compare Mode (When AN0 to AN2 Channels are Selected in Scan Mode) 24.5.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when A/D conversion start delay time (tD) passes after the ADST bit is set to 1, then starts conversion. Figure 24.7 shows the A/D conversion timing. Table 24.6 indicates the A/D conversion time. As indicated in figure 24.7, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in tables 24.6. In scan mode, the values given in table 24.6 apply to the first conversion time. The values given in table 24.7 apply to the second and subsequent conversions. In any conversions, the CKS[1:0] bits in ADCR should be set so that the conversion time should fall within the specified A/D conversion characteristics range. Rev. 1.00 Oct. 03, 2008 Page 841 of 962 REJ09B0465-0100 Section 24 A/D Converter (1) Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1) : ADCSR write cycle (2) : ADCSR address : A/D conversion start delay time tD tSPL : Input sampling time tCONV : A/D conversion time Figure 24.7 A/D Conversion Timing Table 24.6 A/D Conversion Time (Single Mode) CKS1 = 1 CKS0 = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min 3 83 Typ 30 Max 4 84 Min CKS0 = 1 Typ 3 15 43 Max Note: Values in the table are the number of states. Rev. 1.00 Oct. 03, 2008 Page 842 of 962 REJ09B0465-0100 Section 24 A/D Converter Table 24.7 A/D Conversion Time (Scan Mode) CKS1 1 CKS0 0 1 Conversion Time (State) 80 40 24.5.4 External Trigger Input Timing A/D conversion can be externally triggered. When the EXTRGS, TRGS1 and TRGS0 bits are set to B' 000 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge of the ADTRG pin sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 24.8 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 24.8 External Trigger Input Timing Rev. 1.00 Oct. 03, 2008 Page 843 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.6 Interrupt Source In A/D conversion mode, an A/D conversion end interrupt (ADI) occurs at the end of A/D conversion. Specifically, the ADF bit in ADCSR is set to 1 when A/D conversion is completed; and if the ADIE bit is 1 at this time, the A/D converter generates an ADI interrupt. In compare mode, a compare result change interrupt (CMPI) occurs if the comparison result of the specified channel changes (in three cases: from 1 to 0, from 0 to 1, and both). Specifically, the CMPF bit is set when the comparison result between the specified channel and the specified voltage satisfies the specified condition; and if the CMPIE bit is 1 at this time, the A/D converter generates a CMPI interrupt. The DTC can be activated by an ADI or CMPI interrupt. Having the converted data read by the DTC in response to an ADI or CMPI interrupt enables continuous conversion to be achieved without imposing a load on software. Table 24.8 A/D Converter Interrupt Source Name ADI CMPI Interrupt Source End of A/D conversion or comparison Comparison result change Interrupt Flag ADF CMPF DTC Activation Possible Possible Rev. 1.00 Oct. 03, 2008 Page 844 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.7 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 24.9). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 24.10). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 24.10). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 24.10). * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 1.00 Oct. 03, 2008 Page 845 of 962 REJ09B0465-0100 Section 24 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 24.9 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage Offset error Figure 24.10 A/D Conversion Accuracy Definitions Rev. 1.00 Oct. 03, 2008 Page 846 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.8 24.8.1 Usage Notes Module Standby Mode Setting Operation of the A/D converter can be disabled or enabled using the module standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode. For details, see section 6, Power-Down Modes. 24.8.2 Permissible Signal Source Impedance This LSI's analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is TBD k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds TBD k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally for conversion in single mode, the input load will essentially comprise only the internal input resistance of TBD k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 24.11). When converting a high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted. This LSI Equivalent circuit of A/D converter Sensor output impedance TBD k Sensor input Low-pass filter C to 0.1 F Cin = TBD TBD TBD k Figure 24.11 Example of Analog Input Circuit Rev. 1.00 Oct. 03, 2008 Page 847 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.8.3 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. 24.8.4 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of the device may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ANn AVcc. * Relation between AVcc, AVss and Vcc, Vss As the relationship between AVcc, AVss and Vcc, Vss, set AVcc Vcc and AVss = Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. 24.8.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN1, AN0_2 to AN3_2) and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss) on the board. Rev. 1.00 Oct. 03, 2008 Page 848 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.8.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN11, AN0_2 to AN3_2) should be connected between AVcc and AVss as shown in figure 24.12. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN11 or AN0_2 to AN3_2 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN1, AN0_2 to AN3_2) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Rin *2 100 AN0 to AN11, AN0_2 to AN3_2 0.1 F AVSS *1 Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 24.12 Example of Analog Input Protection Circuit Rev. 1.00 Oct. 03, 2008 Page 849 of 962 REJ09B0465-0100 Section 24 A/D Converter 24.8.7 Notes on Analog Input Pins Analog input pins (AN0 to AN11, AN0_2 to AN3_2) are multiplexed with general I/O ports. Accordingly, if the direction of input or output of the general I/O port is changed or the output value of the general I/O port is changed during A/D conversion, the conversion accuracy may be affected. Before using an analog input pin multiplexed with general I/O port as a general I/O port, influence on the A/D conversion accuracy should be evaluated carefully. Rev. 1.00 Oct. 03, 2008 Page 850 of 962 REJ09B0465-0100 Section 25 D/A Converter Section 25 D/A Converter 25.1 * * * * * Features 8-bit resolution Output channels: 2 channels Maximum conversion time of 3 s (with 20 pF load capacitance) Output voltage of 0 V to AVcc Settable for the module standby mode Module data bus Internal data bus AVcc 8-bit DA1 DA0 AVss D/A D A D R 0 D A D R 1 D A C R Control circuit Figure 25.1 Block Diagram of D/A Converter Rev. 1.00 Oct. 03, 2008 Page 851 of 962 REJ09B0465-0100 Bus interface Section 25 D/A Converter Table 25.1 shows the input/output pin configuration of the D/A converter. Table 25.1 Pin Configuration Pin Name AVcc AVss DA0 DA1 I/O Input Input Output Output Function Analog power supply Analog ground Channel 0 analog output Channel 1 analog output 25.2 Register Descriptions * D/A data register 0 (DADR0) * D/A data register 1 (DADR1) * D/A control register (DACR) 25.2.1 D/A Data Registers 0 and 1 (DADR0 and DADR1) * DADR0 and DADR1 DADR0, DADR1 Address: H'FF05D4, H'FF05D5 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 0 0 0 0 0 0 0 0 DADR0 and DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever analog output is enabled, the values in DADR are converted and output to the analog output pins. DADR is initialized to H'00 in standby mode or module standby. Rev. 1.00 Oct. 03, 2008 Page 852 of 962 REJ09B0465-0100 Section 25 D/A Converter 25.2.2 D/A Control Register (DACR) Address: H'FF05D6 Bit: b7 DAOE1 b6 DAOE0 0 b5 b4 b3 b2 b1 b0 Value after reset: 0 0 0 0 0 0 0 Bit 7 Symbol DAOE1 Bit Name D/A output enable 1 D/A output enable 0 Reserved Description 0: Disables the analog output on channel 1 (DA1). 1: Enables the channel 1 D/A conversion; enables the analog output (DA1). 0: Disables the analog output on channel 0 (DA0). 1: Enables the channel 0 D/A conversion; enables the analog output (DA0). These bits are always read as 0 and cannot be modified. R/W R/W 6 DAOE0 R/W 5 to 0 Note: In standby mode or module standby mode, the contents of DACR are retained. * DAOE1 bit and DAOE0 bit (D/A output enable 1 and 0) These bits control the D/A conversion and analog output. The event link function can be used to set the DAOE[1:0] bits. When the event specified in ELSR31 or ELSR32 of the ELC occurs, the corresponding DAOE1 or DAOE0 bit is set to 1, respectively and the D/A conversion starts. Rev. 1.00 Oct. 03, 2008 Page 853 of 962 REJ09B0465-0100 Section 25 D/A Converter 25.3 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When DAOE bit in DACR is set to 1, D/A conversion is enabled and the conversion result is output. The operation example of D/A conversion on channel 0 is as follows. Figure 25.2 shows the timing of this operation. 1. Write the conversion data to DADR0. 2. Set the DAOE0 bit in DACR to 1 to start D/A conversion. The conversion result is output from the analog output pin DA0 after the conversion time tDCONV has elapsed. The conversion result is continued to be output until DADR0 is written to again or the DAOE0 bit is cleared to 0. The output value is expressed by the following formula: DADR contents x AVcc 256 3. If DADR0 is written to again, the conversion is immediately started. The conversion result is output after the conversion time tDCONV has elapsed. 4. If the DAOE0 bit is cleared to 0, analog output is disabled. Rev. 1.00 Oct. 03, 2008 Page 854 of 962 REJ09B0465-0100 Section 25 D/A Converter DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Address DADR0 Conversion data 1 Conversion data 2 DAOE0 DA0 High-impedance state tDCONV Legend: tDCONV: D/A conversion time Conversion result 1 tDCONV Conversion result 2 Figure 25.2 Example of D/A Converter Operation Rev. 1.00 Oct. 03, 2008 Page 855 of 962 REJ09B0465-0100 Section 25 D/A Converter 25.4 25.4.1 Usage Notes Setting for Module Stop Mode The module standby control can select to enable/disable the D/A converter operation. The D/A converter does not operate by the initial value of the register. The register can be accessed by releasing the module standby mode. DADR is initialized in module standby. 25.4.2 Operation in Standby Mode If D/A conversion is enabled and this LSI enters standby mode, DADR is initialized while DACR is held. When the analog power supply current is required to go low in software standby mode, the DAOE1 and DAOE0 bits should be cleared to 0, and D/A output should be disabled. Rev. 1.00 Oct. 03, 2008 Page 856 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits Section 26 Low-Voltage Detection Circuits This microcontroller includes a low-voltage detection module consisting of three circuits, LVD0, LVD1, and LVD2. The circuits are used to prevent abnormal operation (runaway execution) from occurring due to the power supply voltage falling and to recreate the state of the microcontroller before the power supply voltage fell when the power supply voltage rises again. If the power supply voltage falls below a threshold voltage set by the users application, a warning can be given to the application so the application can shutdown in a controlled manner. If the power supply voltage continues to fall below a second programmable threshold voltage, the device can be safely placed in the reset state. This avoids the situation where the power supply voltage falls below the guaranteed operating voltage and the microcontroller enters an unstable state. Thus, system stability can be improved. If the power supply voltage rises again, active mode is automatically entered. The circuits monitor the power-supply voltage, and generate a reset or an interrupt when the voltage falls below or rises above a specified value. Figure 26.1 is a block diagram of the low-voltage detection circuits. Figures 26.2, 26.3, and 26.4 are block diagrams of the LVD2, LVD1 and LVD0 interrupt/reset generation circuits, respectively. Rev. 1.00 Oct. 03, 2008 Page 857 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits 26.1 Features * Power-on reset function Monitors the power-supply voltage input to the VCC pin to generate an internal reset signal when power is first supplied. Releases a reset when the power-supply voltage rises above the specified voltage. * Low-voltage detection function Reset function: Monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a specified value. Interrupt function: Monitors the power-supply voltage, and generates an interrupt when the voltage falls below or rises above respective specified values. Detection levels: 11 levels are available for LVD1 and two levels are available for LVD0. (The level is fixed for LVD2. External voltage input function: For detection, external pins can be selected for a detection voltage and a reference voltage, respectively (LVD2 only). loco CK Prescaler R R Reset control circuit Q S VDCPR Internal reset signal Vdet2 LD2CRH LD2CRL + LVD2 Control circuit LD1CRH LD1CRL LD0CRH VCC Ladder resistor + Vdet1 LVD1 Interrupt control circuit LD0CRL + Vdet0 Detection voltage generator LVD0 Interrupt request Figure 26.1 Block Diagram of Low-Voltage Detection Circuits Rev. 1.00 Oct. 03, 2008 Page 858 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits VCC LVD2 detection voltage + - Noise canceler Digital filter Edge detection circuit Reset control circuit LVD2 circuit reset signal loco/8 loco/4 loco/2 loco Interrupt control circuit LVD2 circuit interrupt signal Figure 26.2 Block Diagram of LVD2 Interrupt/Reset Generation Circuit VCC LVD1 detection voltage + - Noise canceler Digital filter Edge detection circuit Reset control circuit LVD1 circuit reset signal loco/8 loco/4 loco/2 loco Interrupt control circuit LVD1 circuit interrupt signal Figure 26.3 Block Diagram of LVD1 Interrupt/Reset Generation Circuit VCC LVD0 detection voltage + - Noise canceler Digital filter Edge detection circuit Reset control circuit LVD0 circuit reset signal loco/8 loco/4 loco/2 loco Figure 26.4 Block Diagram of LVD0 Reset Generation Circuit Rev. 1.00 Oct. 03, 2008 Page 859 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits 26.2 Register Descriptions This module has the following registers. * * * * * * * Low-voltage detection circuit control protect register (VDCPR) Low-voltage detection circuit 2 control register H (LD2CRH) Low-voltage detection circuit 2 control register L (LD2CRL) Low-voltage detection circuit 1 control register H (LD1CRH) Low-voltage detection circuit 1 control register L (LD1CRL) Low-voltage detection circuit 0 control register H (LD0CRH) Low-voltage detection circuit 0 control register L (LD0CRL) Rev. 1.00 Oct. 03, 2008 Page 860 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits 26.2.1 Low-Voltage Detection Circuit Control Protect Register (VDCPR) Address: H'FF0628 Bit: 7 WRI 6 5 4 3 2 1 0 LDPRC 0 0 0 0 0 0 0 Value after reset: 1 Bit 7 Symbol WRI Bit Name Description R/W R/W VDCPR write disable 0: Writing to the VDCPR bit is enabled. 1: Writing to the VDCPR bit is disabled. Reserved 6 to 1 0 LDPRC These bits are read as 0. The write value should always be 0. R/W Low-voltage detection 0: Writing to each low-voltage detection circuit circuit control register control register is disabled. write enable 1: Writing to each low-voltage detection circuit control register is enabled. Note: Use a MOV instruction to modify this register. * WRI bit (VDCPR write disable) Only when this bit is written to 0, writing to this register is enabled. This bit is always read as 1. * LDPRC bit (Low-voltage detection circuit control register write enable) Only when the value of this bit is 1, writing to the low-voltage detection circuit control register (LD2CRH, LD2CRL, LD1CRH, LD1CRL, LD0CRH and LD0CRL) is enabled. Rev. 1.00 Oct. 03, 2008 Page 861 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits 26.2.2 Low-Voltage Detection Circuit 2 Control Register H (LD2CRH) Address: H'FF0622 Bit: b7 VF2DF b6 VD2UF 0 b5 b4 b3 VD2DFS 0 b2 VD2IRCS 0 b1 VD2MS 0 b0 VD2RE 0 VD2DFCK[1:0] 0 0 Value after reset: 0 Bit 7 Symbol VD2DF Bit Name LVD2 power supply voltage drop flag Description [Setting condition] * * * When the power-supply voltage falls below Vdet2. When 1 is read from this bit and then 0 is written to this bit. When the LVD2 circuit is in standby mode. [Clearing conditions] R/W R/W 6 VD2UF LVD2 [Setting condition] power * When the power supply voltage falls below Vdet2 supply and rises to Vdet2 or higher before falling to Vdet0 voltage rise or lower. flag [Clearing conditions] * * When 1 is read from this bit and then 0 is written to this bit. When the LVD2 circuit is in standby mode. R/W 5, 4 VD2DFCK[1:0] LVD2 00: loco/1 digital filter 01: loco/2 sampling clock select 10: loco/4 11: loco/8 VD2DFS LVD2 0: Disables the digital filter function digital filter 1: Enables the digital filter function function select LVD2 interrupt request generation condition select 0: when VCC rises to Vdet2 or higher. 1: when VCC falls to Vdet2 or lower. When VD2DFS = 1, an interrupt request is generated when the voltage reaches Vdet2, regardless of this bit setting. When VD2MS = 1, a reset request is generated when the voltage falls below Vdet2, regardless of this bit setting. R/W 3 R/W 2 VD2IRCS R/W Rev. 1.00 Oct. 03, 2008 Page 862 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits Bit 1 Symbol VD2MS Bit Name LVD2 mode select LVD2 interrupt/ reset request enable Description 0: Generates an interrupt request when the voltage reaches Vdet2. 1: Generates a reset request when the voltage reaches Vdet2. This bit is enabled when the VD2E bit is 1. 0: Disables interrupt/reset requests when the specified voltage level is detected. 1: Enables interrupt/reset requests when the specified voltage level is detected. R/W R/W 0 VD2RE R/W Table 26.1 shows the relationship between LD2CRH settings and the selection function. LD2CRH should be used according to table 26.1. Table 26.1 LD2CRH Settings and Select Functions LD2CRH Settings VD2MS 1 0 0 0 [Legend] VD2DFS x 1 0 0 x: Don't care. VD2IRCS x x 1 0 LVD2 Falling Reset O Selection Function LVD2 Falling Interrupt O O LVD2 Rising Interrupt O O Rev. 1.00 Oct. 03, 2008 Page 863 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits 26.2.3 Low-Voltage Detection Circuit 2 Control Register L (LD2CRL) Address: H'FF0623 Bit: b7 VD2E b6 VD2CVS 0 b5 VD2RVS 0 b4 b3 b2 b1 b0 0 0 0 0 0 Value after reset: 0 Bit 7 6 Symbol VD2E VD2CVS Bit Name LVD2 circuit enable Description R/W 0: The LVD2 circuit is not used. (In standby mode) R/W 1: The LVD2 circuit is used. R/W LVD2 circuit 0: VCC voltage is used as the reference voltage. reference voltage 1: Externally input (PA7) voltage is used as the input select reference voltage.* LVD2 circuit 0: Internally generated voltage is used as the detection voltage detection voltage. input select 1: Externally input (PA6) voltage is used as the detection voltage.* Reserved These bits are read as 0. The write value should be 0. 5 VD2RVS R/W 4 to 0 Note: * When an externally input voltage is used as the reference voltage or detection voltage, the externally input voltage must not exceed 1/2 Vcc. Rev. 1.00 Oct. 03, 2008 Page 864 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits 26.2.4 Low-Voltage Detection Circuit 1 Control Register H (LD1CRH) Address: H'FF0624 Bit: b7 VD1DF b6 VD1UF 0 b5 b4 b3 VD1DFS 0 b2 VD1IRCS 0 b1 VD1MS 0 b0 VD1RE 0 VD1DFCK[1:0] 0 0 Value after reset: 0 Bit 7 Symbol VD1DF Bit Name Description R/W R/W LVD1 power [Setting condition] supply * When the power-supply voltage falls below Vdet1. voltage drop [Clearing conditions] flag * When 1 is read from this bit and then 0 is written to. * When the LVD1 circuit is in standby mode. LVD1 power [Setting condition] supply * When the power supply voltage falls below Vdet1 and voltage rise rises to Vdet1 or higher before falling to Vdet0 or lower flag [Clearing conditions] * * When 1 is read from this bit and then 0 is written to. When the LVD1 circuit is in standby mode. 6 VD1UF R/W 5, 4 VD1DFCK LVD1 digital 00: loco/1 [1:0] filter 01: loco/2 sampling clock select 10: loco/4 11: loco/8 3 VD1DFS LVD1 digital 0: Disables the digital filter function filter 1: Enables the digital filter function function select R/W R/W 2 VD1IRCS LVD1 interrupt request generation condition select 0: Generates an interrupt request when VCC rises to Vdet1 R/W or more. 1: Generates an interrupt request when VCC falls to Vdet1 or less. When VD1DFS = 1, an interrupt request is generated when the voltage reaches Vdet1, regardless of this bit setting. When VD1MS = 1, a reset request is generated when the voltage falls below Vdet1, regardless of this bit setting. Rev. 1.00 Oct. 03, 2008 Page 865 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits Bit 1 Symbol VD1MS Bit Name Description R/W LVD1 mode 0: Generates an interrupt request when the voltage reaches R/W select Vdet1. 1: Generates a reset request when the voltage reaches Vdet1. 0 LD1RE LVD1 interrupt/ reset request enable This bit is enabled when the VD1E bit is 1. 0: Disables interrupt/reset requests generated when the specified voltage level is detected. 1: Enables interrupt/reset requests generated when the specified voltage level is detected. R/W Table 26.2 shows the relationship between the LD1CRH settings and selection function. LD1CRH should be set according to table 26.2. Table 26.2 LD1CRH Settings and Select Functions LD1CRH VD1MS 1 0 0 0 [Legend] VD1DFS x 1 0 0 x: Don't care. VD1IRCS x x 1 0 LVD1 Falling Reset O Select Functions LVD1 Falling Interrupt O O LVD1 Rising Interrupt O O Rev. 1.00 Oct. 03, 2008 Page 866 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits 26.2.5 Low-Voltage Detection Circuit 1 Control Register L (LD1CRL) Address: H'FF0625 Bit: b7 VD1E b6 b5 b4 b3 b2 VD1LS[3:0] 0 0 0 0 b1 b0 0 0 0 Value after reset: 0 Bit 7 6 to 4 3 to 0 Symbol VD1E VD1LS [3:0] Bit Name LVD1 circuit enable Reserved LVD1 detection voltage level select 3 to 0 Description 0: The LVD1 circuit is not used. (In standby mode) 1: The LVD1 circuit is used. R/W R/W These bits are read as 0. The write value should be 0. 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: Setting prohibited 0100: Setting prohibited 0101: 2.85 V (typ.) 0110: 2.92 V (typ.) 0111: 3.07 V (typ.) 1000: 3.22 V (typ.) 1001: 3.37 V (typ.) 1010: 3.52 V (typ.) 1011: 3.67 V (typ.) 1100: 3.82 V (typ.) 1101: 3.97 V (typ.) 1110: 4.12 V (typ.) 1111: 4.27 V (typ.) R/W Rev. 1.00 Oct. 03, 2008 Page 867 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits 26.2.6 Low-Voltage Detection Circuit 0 Control Register H (LD0CRH) Address: H'FF0626 Bit: b7 b6 b5 b4 b3 VD0DFS 0 b2 b1 b0 0 VD0DFCK[1:0] 0 0 0 0 1 Value after reset: Bit 7 6 5, 4 Symbol Bit Name Reserved Reserved Description This bit is read as undefined value. The write value should be 0. This bit is read as 0. The write value should be 0. R/W R/W VD0DFCK[1:0] LVD0 digital 00: loco/1 filter 01: loco/2 sampling clock select 10: loco/4 11: loco/8 VD0DFS LVD0 digital 0: Disables the digital filter function. filter function 1: Enables the digital filter function. select Reserved Reserved These bits are read as 0. The write value should always be 0. This bit is read as 1. The write value should be 1. 3 R/W 2, 1 0 Rev. 1.00 Oct. 03, 2008 Page 868 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits 26.2.7 Low-Voltage Detection Circuit 0 Control Register L (LD0CRL) Address: H'FF0627 Bit: b7 b6 b5 b4 b3 b2 b1 VD0LS1 0 b0 0 0 0 0 0 1 Value after reset: 1 Bit 7 6 to 2 1 Symbol VD0LS1 Bit Name Reserved Reserved LVD0 detection voltage level select Reserved Description This bit is read as 1. The write value should be 1. This bit is read as 0. The write value should be 0. 0: 2.35 V (typ.) 1: 3.80 V (typ.) The write value should always be 0. R/W R/W 0 Rev. 1.00 Oct. 03, 2008 Page 869 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits 26.3 26.3.1 Operation Power-On Reset Function Figure 26.5 shows the operation timing of the power-on reset function. During the power-on reset function, the LVD0 circuit monitors the power-supply voltage level to initialize the entire chip. When the power-supply voltage level rises above Vdet0, the prescaler is released from its reset state and it starts counting. The OVF signal is generated to release the internal reset signal after the prescaler has counted 128 loco cycles. After a power-on reset, the LVD0 reset function is always enabled. Vdet0 Vcc VLVDR0min Prescaler reset signal OVF Internal reset signal 128 loco cycles Prescaler counter starts Reset released Figure 26.5 Operational Timing of Power-On Reset Rev. 1.00 Oct. 03, 2008 Page 870 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits 26.3.2 (1) Low-Voltage Detection Circuit Low Voltage Detect Reset 2 (LVDR2) LVDR2 is a reset generated by the LVD2 circuit. Figure 26.6 shows the operation timing of the LVDR2. The LVD2 enters the module-standby state after release from a power-on reset. To operate the LVDR2, set the VD2E bit in LD2CRL to 1, wait for TBD s (tLVD2ON) until the detection voltage and the low-voltage detection circuit 2 operation have stabilized using a software timer, etc., then set the VD2MS and VD2RE bits in LD2CRH to 1. After that, the output settings of I/O ports must be made. To cancel the LVDR2, first the VD2RE bit in LD2CRH should be cleared to 0 and then the VD2E bit in LD2CRL should be cleared to 0. Figure 26.7 shows the procedure to set the LVDR2. When the power-supply voltage falls below Vdet2, the LVDR2 clears the LVDRES2 signal to 0, and resets the prescaler. The low-voltage detection reset state remains in place until a power-on reset is generated. When the power-supply voltage rises above the Vdet2 voltage again, the prescaler starts counting. It counts 32 loco cycles, and then releases the internal reset signal. Note that if the power supply voltage falls below VLVDR2min = TBD V and then rises from that point, the LVDR2 may not occur. Such a case should be evaluated thoroughly. If the power supply voltage falls below Vdet0, a power-on reset occurs. Rev. 1.00 Oct. 03, 2008 Page 871 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits VCC Vdet2 Vdet0 GND LVDRES2 Prescaler reset signal OVF Internal reset signal 32 loco cycles Prescaler counter starts Reset released Figure 26.6 Operation Timing of LVDR2 Start Set VD2E in LD2CRL to 1. [1] Set VD2E in LD2CRL to activate the LVD2 circuit and wait for the stabilization. [2] Set the digital filter. [1] Wait for tLVD2ON period. [3] Set the LVD2 circuit to generate reset requests. [4] Enable the LVD2 circuit reset requests. [2] Set VD2DFCK[1:0] in LD2CRH. Set VD2DFS in LD2CRH. [3] Set VD2MS in LD2CRH to 1. [4] Set VD2RE in LD2CRH to 1. End Figure 26.7 Procedure to Set LVDR2 Rev. 1.00 Oct. 03, 2008 Page 872 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits (2) Low Voltage Detect Interrupt 2 (LVDI2) LVDI2 is an interrupt generated by the LVD2 circuit. Figure 26.8 shows the operation timing of LVDI2. The LVD2 enters the module-standby state after release from a power-on reset. To operate the LVDI2, set the VD2E bit in LD2CRL to 1, wait for TBD s (tLVD2ON) until the detection voltage and the low-voltage detection circuit 2 operation have stabilized using a software timer, etc., then clear the VD2MS bit to 0 and set the VD2RE bit to 1 in LD2CRH. After that, the output settings of I/O ports must be made. To cancel the LVDI2, first the VD2RE bit in LD2CRH should be cleared to 0 and then the VD2E bit in LD2CRL should be cleared to 0. Figure 26.9 shows the procedure to set the LVDI2. When the power-supply voltage falls below Vdet2, the LVDI2 clears the LVDINT2 signal to 0 and the VD2DFS bit in LD2CRH is set to 1. If the VD2DFS or VD2IRCS bit in LD2CRH is 1 at this time, an LVD2 interrupt request is simultaneously generated. In this case, the necessary data must be saved in the on-chip flash memory area or external EEPROM, etc, and a transition must be made to standby mode or sleep mode. Until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. When the power-supply voltage does not fall below Vdet0 but rises above Vdet2, the LVDI2 sets the LVDINT2 signal to 1 and set the VD2UF bit in LD2CRH to 1. If the VD2DFS bit in LD2CRH is 1 or the VD2IRCS bit in LD2CRH is 0 at this time, an LVD2 interrupt request is simultaneously generated. If the power supply voltage falls below Vdet0, a power-on reset occurs. Rev. 1.00 Oct. 03, 2008 Page 873 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits VCC Vdet2 Vdet0 GND LVDINT2 VD2DFS VD2DF VD2UF LVD2 drop interrupt LVD2 rise interrupt Figure 26.8 Operation Timing of LVDI2 Rev. 1.00 Oct. 03, 2008 Page 874 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits Start Set VD2E in LD2CRL to 1. [1] Set VD2E in LD2CRL to 1 to activate the LVD2 circuit and wait for the stabilization. [2] Set interrupt request generation conditions when the digital filter is not used. [3] Set the digital filter. [1] Wait for tLVD2ON. [2] Set VD2IRCS in LD2CRH. [4] Set the LVD2 circuit to generate interrupt requests. [3] [5] Enable the LVD2 circuit interrupt requests. Set VD2DFCK[1:0] in LD2CRH. Set VD2DFS in LD2CRH. [4] Clear VD2MS in LD2CRH to 0. [5] Set VD2RE in LD2CRH to 1. End Figure 26.9 Procedure to Set LVDR2 Rev. 1.00 Oct. 03, 2008 Page 875 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits (3) Low Voltage Detect Reset 1 (LVDR1) LVDR1 is a reset generated by the LVD1 circuit. Figure 26.10 shows the operation timing of the LVDR1. The LVD1 enters the module-standby state after release from a power-on reset. To operate the LVDR1, set the VD1E bit in LD1CRL to 1, wait for TBD s (tLVD1ON) until the detection voltage and the low-voltage detection circuit 1 operation have stabilized using a software timer, etc., then set the VD1MS and VD1RE bits in LD1CRH to 1. After that, the output settings of I/O ports must be made. To cancel the LVDR1, first the VD1RE bit in LD1CRH should be cleared to 0 and then the VD1E bit in LD1CRL should be cleared to 0. Figure 26.11 shows the procedure to set the LVDR1. When the power-supply voltage falls below Vdet1, the LVDR1 clears the LVDRES1 signal to 0, and resets the prescaler. The low-voltage detection reset state remains in place until a power-on reset is generated. When the power-supply voltage rises above the Vdet1 voltage again, the prescaler starts counting. It counts 32 loco cycles, and then releases the internal reset signal. Note that if the power supply voltage falls below VLVDR1min = TBD V and then rises from that point, the LVDR1 may not occur. Such a case should be evaluated thoroughly. If the power supply voltage falls below Vdet0, a power-on reset occurs. VCC Vdet1 Vdet0 GND LVDRES1 Prescaler reset signal OVF Internal reset signal 32 loco cycles Prescaler counter starts Reset released Figure 26.10 Operation Timing of LVDR1 Rev. 1.00 Oct. 03, 2008 Page 876 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits Start Set VD1E in LD1CRL to 1. [1] Set VD1E in LD1CRL to 1 to activate the LVD1 circuit and wait for the stabilization. [2] Set the digital filter. [1] Wait for tLVD1ON. [3] Set the LVD1 circuit to generate reset requests. [4] Enable the LVD1 circuit reset requests. [2] Set VD1DFCK[1:0] in LD1CRH. Set VD1DFS in LD1CRH. [3] Set VD1MS in LD1CRH to 1. [4] Set VD1RE in LD1CRH to 1. End Figure 26.11 Procedure to Set LVDR1 Rev. 1.00 Oct. 03, 2008 Page 877 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits (4) Low Voltage Detect Interrupt 1 (LVDI1) LVDI1 is an interrupt generated by the LVD1 circuit. Figure 26.12 shows the operation timing of LVDI1. The LVD1 enters the module-standby state after release from a power-on reset is canceled. To operate the LVDI1, set the VD1E bit in LD1CRL to 1, wait for TBD s (tLVD1ON) until the detection voltage and the low-voltage detection circuit 1 operation have stabilized using a software timer, etc., then clear the VD1MS bit to 0 and set the VD1RE bit to 1 in LD1CRH. After that, the output settings of I/O ports must be made. To cancel the LVDI1, first the VD1RE bit in LD1CRH should be cleared to 0 and then the VD1E bit in LD1CRL should be cleared to 0. Figure 26.13 shows the procedure to set the LVDI1. When the power-supply voltage falls below Vdet1, the LVDI1 clears the LVDINT1 signal to 0 and the VD1DFS bit in LD1CRH is set to 1. If the VD1DFS or VD1IRCS bit in LD1CRH is 1 at this time, an LVD1 interrupt request is simultaneously generated. In this case, the necessary data must be saved in the on-chip flash memory area or external EEPROM, etc, and a transition must be made to standby mode or sleep mode. Until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. When the power-supply voltage does not fall below Vdet0 but rises above Vdet1, the LVDI2 sets the LVDINT1 signal to 1 and set the VD1UF bit in LD2CRH to 1. If the VD1DFS bit in LD1CRH is 1 or the VD1IRCS bit in LD1CRH is 0 at this time, an LVD1 interrupt request is simultaneously generated. If the power supply voltage falls below Vdet0, a power-on reset occurs. Rev. 1.00 Oct. 03, 2008 Page 878 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits VCC Vdet1 Vdet0 GND LVDINT1 VD1DFS VD1DF VD1UF LVD1 drop interrupt LVD1 rise interrupt Figure 26.12 Operational Timing of LVDI1 Rev. 1.00 Oct. 03, 2008 Page 879 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits Start Set VD1E in LD1CRL to 1. [1] Set VD1E in LD1CRL to 1 to activate the LVD1 circuit and wait for the stabilization. [2] Set interrupt request generation conditions when the digital filter is not used. [3] Set the digital filter. [1] Wait for tLVD1ON. [2] Set VD1IRCS in LD1CRH. [4] Set the LVD1 circuit to generate interrupt requests. [3] [5] Enable the LVD1 circuit interrupt requests. Set VD1DFCK[1:0] in LD1CRH. Set VD1DFS in LD1CRH. [4] Clear VD1MS in LD1CRH to 0. [5] Set VD1RE in LD1CRH to 1. End Figure 26.13 Procedure to Set LVDI1 (5) Low Voltage Detect Reset 0 (LVDR0) LVDR0 is a reset generated by the LVD0 circuit. Figure 26.14 shows the operation timing of the LVDR0. After a power-on reset is released, the LVD0 circuit is always enabled. When the power-supply voltage falls below Vdet0, the LVDR0 clears the LVDRES0 signal to 0, and resets the prescaler, and a power-on reset operation is enabled. When the power-supply voltage rises above the Vdet0 voltage again, the prescaler starts counting. It counts 128 loco cycles, and then releases the internal reset signal. Note that if the power supply voltage falls below VLVDR0min = TBD V and then rises from that point, the LVDR0 may not occur. Such a case should be evaluated thoroughly. Rev. 1.00 Oct. 03, 2008 Page 880 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits VCC Vdet0 VLVDR0min GND LVDRES0 Prescaler reset signal OVF Internal reset signal 128 loco cycles Prescaler counter starts Reset released Figure 26.14 Operation Timing of LVDR0 Rev. 1.00 Oct. 03, 2008 Page 881 of 962 REJ09B0465-0100 Section 26 Low-Voltage Detection Circuits Rev. 1.00 Oct. 03, 2008 Page 882 of 962 REJ09B0465-0100 Section 27 List of Registers Section 27 List of Registers The address list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operation mode. The information is given as shown below. 1. * * * * Register Addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The data bus width is indicated. The number of access states is indicated. 2. Register Bits * Bit configurations of the registers are described in the same order as the register addresses (address order). * Reserved bits are indicated by in the bit name column. * When registers consist of 16 bits, bits are described from the MSB side. 3. Register States in Each Operating Mode * Register states are described in the same order as the register addresses (address order). * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, see the section on that on-chip peripheral module. Rev. 1.00 Oct. 03, 2008 Page 883 of 962 REJ09B0465-0100 Section 27 List of Registers 27.1 Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register. Note: Do not attempt to access undefined or reserved addresses. Correct operation of the access itself or later operations is not guaranteed when such an address is accessed. Number of Data Bus Access States Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Name Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 5 Port mode register 6 Port mode register 8 Port mode register 9* Port mode register A IIC/SSU select register Port mode register J Port pull-up control register 1 Port pull-up control register 2 Port pull-up control register 3 Port pull-up control register 5 Port pull-up control register 6 Port pull-up control register 8 Port pull-up control register 9* Port pull-up control register A Port pull-up control register B Port pull-up control register J Port drive control register 1 1 1 Number Abbreviation of Bits Address PMR1 PMR2 PMR3 PMR5 PMR6 PMR8 PMR9 PMRA ICSUSR PMRJ PUCR1 PUCR2 PUCR3 PUCR5 PUCR6 PUCR8 PUCR9 PUCRA PUCRB PUCRJ PDVR1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF0000 H'FF0001 H'FF0002 H'FF0004 H'FF0005 H'FF0007 H'FF0008 H'FF0009 H'FF000B H'FF000C H'FF0010 H'FF0011 H'FF0012 H'FF0014 H'FF0015 H'FF0017 H'FF0018 H'FF0019 H'FF001A H'FF001C H'FF0030 Module I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port IIC/SSU I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port Rev. 1.00 Oct. 03, 2008 Page 884 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Port drive control register 2 Port drive control register 3 Port drive control register 5 Port drive control register 6 Port drive control register 8 Port drive control register 9* 1 Number Abbreviation of Bits Address PDVR2 PDVR3 PDVR5 PDVR6 PDVR8 PDVR9 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF0031 H'FF0032 H'FF0034 H'FF0035 H'FF0037 H'FF0038 H'FF0040 H'FF0041 H'FF0042 H'FF0043 H'FF0044 H'FF0045 H'FF0046 H'FF0047 H'FF0048 H'FF0049 H'FF004A H'FF004B H'FF0050 H'FF0051 Module I/O port I/O port I/O port I/O port I/O port I/O port PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC Number of Data Bus Access States Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Port 1 peripheral function mapping PMCR11 register 1 Port 1 peripheral function mapping PMCR12 register 2 Port 1 peripheral function mapping PMCR13 register 3 Port 1 peripheral function mapping PMCR14 register 4 Port 2 peripheral function mapping PMCR21 register 1 Port 2 peripheral function mapping PMCR22 register 2 Port 2 peripheral function mapping PMCR23 register 3 Port 2 peripheral function mapping PMCR24 register 4 Port 3 peripheral function mapping PMCR31 register 1 Port 3 peripheral function mapping PMCR32 register 2 Port 3 peripheral function mapping PMCR33 register 3 Port 3 peripheral function mapping PMCR34 register 4 Port 5 peripheral function mapping PMCR51 register 1 Port 5 peripheral function mapping PMCR52 register 2 Rev. 1.00 Oct. 03, 2008 Page 885 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Number Abbreviation of Bits Address 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF0052 H'FF0053 H'FF0054 H'FF0055 H'FF0056 H'FF0057 H'FF005E H'FF005F H'FF0060 H'FF0061 H'FF0062 H'FF0063 H'FF0065 H'FF0066 H'FF0067 H'FF0518 H'FF0519 H'FF0520 H'FF0521 H'FF0522 Module PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC HW-LIN HW-LIN Interrupt Interrupt Interrupt Number of Data Bus Access States Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Port 5 peripheral function mapping PMCR53 register 3 Port 5 peripheral function mapping PMCR54 register 4 Port 6 peripheral function mapping PMCR61 register 1 Port 6 peripheral function mapping PMCR62 register 2 Port 6 peripheral function mapping PMCR63 register 3 Port 6 peripheral function mapping PMCR64 register 4 Port 8 peripheral function mapping PMCR83 register 3 Port 8 peripheral function mapping PMCR84 register 4 Port 9 peripheral function mapping PMCR91 1 register 1* Port 9 peripheral function mapping PMCR92 1 register 2* Port 9 peripheral function mapping PMCR93 1 register 3* Port 9 peripheral function mapping PMCR94 1 register 4* Peripheral function mapping register write-protect register PMCWPR Port A peripheral function mapping PMCRA3 register 3 Port A peripheral function mapping PMCRA4 register 4 LIN control register LIN status register Interrupt control register IRQ enable register IRQ sense control register H LINCR LINST INTCR IER ISCRH Rev. 1.00 Oct. 03, 2008 Page 886 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name IRQ sense control register L IRQ status register Number Abbreviation of Bits Address ISCRL ISR 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF0523 H'FF0524 H'FF0525 H'FF0526 H'FF0528 H'FF0529 H'FF052A H'FF052B H'FF052C H'FF052D H'FF052E H'FF052F H'FF0530 H'FF0531 H'FF0534 H'FF0535 H'FF0536 H'FF0537 H'FF0538 H'FF0539 H'FF053A H'FF053B H'FF053D H'FF0550 H'FF0551 H'FF0552 H'FF0553 H'FF0554 H'FF0555 H'FF0556 Module Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt DTC DTC DTC DTC DTC DTC DTC DTC DTC SCI SCI SCI SCI SCI SCI SCI Number of Data Bus Access States Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 IRQ noise canceler control register INCCR Interrupt vector offset register Event link interrupt control status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F* Interrupt priority register G Interrupt priority register H Interrupt priority register I DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC enable register F* DTC enable register G DTC enable register H DTC vector register Serial mode register Bit rate register Serial control register 3 Transmit data register Transmit shift register Receive data register Sampling mode register 1 1 VOFR ELCSR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTCERH DTVECR SMR BRR SCR3 TDR SSR RDR SPMR Rev. 1.00 Oct. 03, 2008 Page 887 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Serial mode register_2 Bit rate register_2 Serial control register 3_2 Transmit data register_2 Transmit shift register_2 Receive data register_2 Sampling mode register_2 Serial mode register_3 Bit rate register_3 Serial control register 3_3 Transmit data register_3 Transmit shift register_3 Receive data register_3 Sampling mode register_3 Timer RD counter_2* 1 Number Abbreviation of Bits Address SMR_2 BRR_2 SCR3_2 TDR_2 SSR_2 RDR_2 SPMR_2 SMR_3 BRR_3 SCR3_3 TDR_3 SSR_3 RDR_3 SPMR_3 TRDCNT_2 GRA_2 GRB_2 GRC_2 GRD_2 TRDCNT_3 GRA_3 GRB_3 GRC_3 GRD_3 1 Module SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 SCI_3 Timer RD (unit 1, channel 2) Number of Data Bus Access States Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16* 16* 16* 2 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 H'FF0558 H'FF0559 H'FF055A H'FF055B H'FF055C H'FF055D H'FF055E H'FF0560 H'FF0561 H'FF0562 H'FF0563 H'FF0564 H'FF0565 H'FF0566 H'FF0570 H'FF0572 H'FF0574 H'FF0576 H'FF0578 H'FF057A H'FF057C H'FF057E H'FF0580 H'FF0582 H'FF0584 H'FF0585 H'FF0586 H'FF0587 H'FF0588 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 General register A_2* General register B_2* 1 2 1 2 General register C_2* General register D_2* Timer RD counter_3* 1 1 16* 16* Timer RD (unit 1, channel 3) 2 1 2 16* 16* 16* 2 General register A_3* General register B_3* 1 2 1 2 General register C_3* General register D_3* 1 16* 16* Timer RD (unit 1, channel 2) 8 8 8 8 8 2 1 2 Timer RD control register_2* Timer RD I/O control register 1 A_2* Timer RD I/O control register 1 C_2* Timer RD status register_2* Timer RD interrupt enable 1 register_2* 1 TRDCR_2 TRDIORA_2 TDRIORC_2 TRDSR_2 TRDIER_2 Rev. 1.00 Oct. 03, 2008 Page 888 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name PWM mode output level control 1 register_2* Timer RD digital filtering function 1 select register_2* Timer RD control register_3* Timer RD I/O control register 1 A_3* Timer RD I/O control register 1 C_3* Timer RD status register_3* Timer RD interrupt enable 1 register_3* PWM mode output level control 1 register_3* Timer RD digital filtering function 1 select register_3* Timer RD status register_23* Timer RD mode register_23* Timer RD PWM mode 1 register_23* Timer RD function control 1 register_23* Timer RD output master enable 1 register 1_23* Timer RD output master enable 1 register 2_23* Timer RD output control 1 register_23* Timer RD A/D conversion start 1 trigger control register_23* I C bus control register 1 SS control register H I C bus control register 2 SS control register L 2 2 1 1 1 Number Abbreviation of Bits Address POCR_2 TRDDF_2 TRDCR_3 TRDIORA_3 TDRIORC_3 TRDSR_3 TRDIER_3 POCR_3 TRDDF_3 TRDSTR_23 TRDMDR_23 TRDPMR_23 TRDFCR_23 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF0589 H'FF058A H'FF058B H'FF058C H'FF058D H'FF058E H'FF058F H'FF0590 H'FF0591 H'FF0592 H'FF0593 H'FF0594 H'FF0595 H'FF0596 H'FF0597 H'FF0598 H'FF0599 H'FF05C8 Module Timer RD (unit 1, channel 2) Number of Data Bus Access States Width 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Timer RD (unit 1, channel 3) 1 Timer RD (unit 1, channels 2 and 3 in common) 8 8 8 8 8 8 8 8 TRDOER1_23 8 TRDOER2_23 8 TRDOCR_23 TRDADCR_2 3 ICCR1 SSCRH ICCR2 SSCRL 8 8 8 8 IIC2/SSU 8 8 H'FF05C9 IIC2/SSU 8 8 Rev. 1.00 Oct. 03, 2008 Page 889 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name I C bus mode register SS mode register I C bus interrupt enable register SS enable register I C bus status register SS status register Slave address register SS mode register 2 I C bus transmit data register SS transmit data register I C bus receive data register SS receive data register D/A data register 0 D/A data register 1 D/A control register IrDA control register A/D data register 0 2 2 2 2 2 Number Abbreviation of Bits Address ICMR SSMR ICIER SSER ICSR SSSR SAR SSMR2 ICDRT SSTDR ICDRR SSRDR DADR0 DADR1 DACR IrCR ADDR0 8 8 8 8 16 H'FF05D4 H'FF05D5 H'FF05D6 H'FF05DE H'FF05E0 8 H'FF05CF 8 H'FF05CE 8 H'FF05CD 8 H'FF05CC 8 H'FF05CB 8 H'FF05CA Module IIC2/SSU Number of Data Bus Access States Width 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 IIC2/SSU 8 8 IIC2/SSU 8 8 IIC2/SSU 8 8 IIC2/SSU 8 8 IIC2/SSU 8 8 D/A converter D/A converter D/A converter SCI3_2 A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 1) 8 8 8 8 16 Compare data register CMPR 8 H'FF05E0 16* 3 2 A/D data register 1 ADDR1 16 H'FF05E2 16 2 Compare control status register CMPCSR 8 H'FF05E2 16* 3 2 A/D data register 2 ADDR2 16 H'FF05E4 16 2 Rev. 1.00 Oct. 03, 2008 Page 890 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Compare voltage register H Number Abbreviation of Bits Address CMPVALH 8 H'FF05E4 Module A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 1) A/D converter (unit 2) A/D converter (unit 2) A/D converter (unit 2) Number of Data Bus Access States Width 16* 3 2 A/D data register 3 ADDR3 16 H'FF05E6 16 2 Compare voltage register L CMPVALL 8 H'FF05E6 16* 3 2 A/D data register 4 ADDR4 16 H'FF05E8 16 2 A/D data register 5 ADDR5 16 H'FF05EA 16 2 A/D data register 6 ADDR6 16 H'FF05EC 16 2 A/D data register 7 ADDR7 16 H'FF05EE 16 2 A/D control/status register ADCSR 8 H'FF05F0 8 2 A/D control register ADCR 8 H'FF05F1 8 2 A/D mode register ADMR 8 H'FF05F4 8 2 A/D data register 0_2* 4 ADDR0_2 16 H'FF0600 16 2 Compare data register_2* 4 CMPR_2 8 H'FF0600 16* 3 2 A/D data register 1_2* 4 ADDR1_2 16 H'FF0602 16 2 Rev. 1.00 Oct. 03, 2008 Page 891 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Compare control status 4 register_2* A/D data register 2_2* 4 Number Abbreviation of Bits Address CMPCSR_2 8 H'FF0602 Module A/D converter (unit 2) A/D converter (unit 2) A/D converter (unit 2) A/D converter (unit 2) A/D converter (unit 2) A/D converter (unit 2) A/D converter (unit 2) A/D converter (unit 2) Exception handling Lowvoltagedetection circuit Number of Data Bus Access States Width 16* 3 2 ADDR2_2 16 H'FF0604 16 2 Compare voltage register H_2* 4 CMPVALH_2 8 H'FF0604 16* 3 2 A/D data register 3_2* 4 ADDR3_2 16 H'FF0606 16 2 Compare voltage register L_2* 4 CMPVALL_2 8 H'FF0606 16* 3 2 A/D control/status register_2* 4 ADCSR_2 8 H'FF0610 8 2 A/D control register_2* 4 ADCR_2 8 H'FF0611 8 2 A/D mode register_2* 4 ADMR_2 8 H'FF0614 8 2 Reset source flag register Low-voltage detection circuit 2 control register H Low-voltage detection circuit 2 control register L Low-voltage detection circuit 1 control register H Low-voltage detection circuit 1 control register L Low-voltage detection circuit 0 control register H Low-voltage detection circuit 0 control register L RSTFR LD2CRH LD2CRL LD1CRH LD1CRL LD0CRH LD0CRL 8 8 8 8 8 8 8 H'FF0620 H'FF0622 H'FF0623 H'FF0624 H'FF0625 H'FF0626 H'FF0627 8 8 8 8 8 8 8 2 2 2 2 2 2 2 Rev. 1.00 Oct. 03, 2008 Page 892 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Low-voltage detection circuit control protect register Number Abbreviation of Bits Address VDCPR 8 H'FF0628 Module Lowvoltagedetection circuit Clock oscillator Number of Data Bus Access States Width 8 2 High-speed OCO control register High-speed OCO trimming data protect register High-speed OCO trimming data register 1 High-speed OCO trimming data register 2 High-speed OCO trimming data register 3 High-speed OCO trimming data register 4 Timer RG counter General register A General register B Timer RG mode register Timer RG counter control register Timer RG control register Timer RG I/O control register Timer RG status register HOCR HOTRMDPR HOTRMDR1 HOTRMDR2 HOTRMDR3 HOTRMDR4 TRGCNT GRA GRB TRGMDR TRGCNTCR TRGCR TRGIOR TRGSR 8 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 8 8 8 8 8 8 8 H'FF062A H'FF062B H'FF062C H'FF062D H'FF062E H'FF062F H'FF0640 H'FF0642 H'FF0644 H'FF0646 H'FF0647 H'FF0648 H'FF0649 H'FF064A H'FF064B H'FF064C H'FF064E H'FF0660 H'FF0661 H'FF0662 H'FF0663 H'FF0680 H'FF0681 H'FF0682 8 8 16* 16* 16* 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 16* Timer RG Timer RG Timer RG Timer RG Timer RG Timer RG Timer RG Timer RG Timer RG Timer RG Timer RG FLASH FLASH FLASH FLASH ELC ELC ELC 16* 16* 16* 8 8 8 8 8 8 16* 16* 8 8 8 8 8 8 8 3 2 2 2 Timer RG interrupt enable register TRGIER GRA buffer register GRB buffer register Flash memory control register 1 Flash memory control register 2 Flash memory data flash protect register Flash memory status register Event link setting register 0 Event link setting register 1 Event link setting register 2* 5 BRA BRB FLMCR1 FLMCR2 DFPR FLMSTR ELSR0 ELSR1 ELSR2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Oct. 03, 2008 Page 893 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Event link setting register 3 Event link setting register 4 Event link setting register 8 Event link setting register 10 Event link setting register 11* Event link setting register 12 Event link setting register 14 Event link setting register 15 Event link setting register 18 Event link setting register 19 Event link setting register 21 Event link setting register 22 Event link setting register 23 Event link setting register 24 Event link setting register 29 Event link setting register 30 Event link setting register 31 Event link setting register 32 Port-group setting register 1 Port-group setting register 2 Port-group control register 1 Port-group control register 2 Port buffer register 1 Port buffer register 2 Event link port setting register 0 Event link port setting register 1 Event link port setting register 2 Event link port setting register 3 6 Number Abbreviation of Bits Address ELSR3 ELSR4 ELSR8 ELSR10 ELSR11 ELSR12 ELSR14 ELSR15 ELSR18 ELSR19 ELSR21 ELSR22 ELSR23 ELSR24 ELSR29 ELSR30 ELSR31 ELSR32 PGR1 PGR2 PGC1 PGC2 PDBF1 PDBF2 PEL0 PEL1 PEL2 PEL3 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF0683 H'FF0684 H'FF0688 H'FF068A H'FF068B H'FF068C H'FF068E H'FF068F H'FF0692 H'FF0693 H'FF0695 H'FF0696 H'FF0697 H'FF0698 H'FF069D H'FF069E H'FF069F H'FF06A0 H'FF06A2 H'FF06A3 H'FF06A6 H'FF06A7 H'FF06AA H'FF06AB H'FF06AD H'FF06AE H'FF06AF H'FF06B0 H'FF06B5 H'FF06B6 H'FF06B7 Module ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC ELC Number of Data Bus Access States Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Event link option setting register A ELOPA Event link option setting register B ELOPB Event link option setting register C ELOPC Rev. 1.00 Oct. 03, 2008 Page 894 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Event-generation timer control register Event-generation timer interval setting register A Event-generation timer interval setting register B Even-generation delay time selection register Event link control register ELC timer counter System clock control register Power-down control register 1 Power-down control register 2 Power-down control register 3 Backup control register OSC oscillation settling control status register Reset control register Timer RA control register Timer RA I/O control register Timer RA mode register Timer RA prescaler register Timer RA timer register Timer RA interrupt request status register Timer RC counter* 5 Number Abbreviation of Bits Address ELTMCR ELTMSA ELTMSB ELTMDR ELCR ELTMCNT SYSCCR LPCR1 LPCR2 LPCR3 BAKCR OSCCSR RSTCR TRACR TRAIOC TRAMR TRAPRE TRATR TRAIR TRCCNT GRA GAB GRC GRD 5 Module ELC ELC ELC ELC ELC ELC SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM Clock oscillator Exception handling Timer RA Timer RA Timer RA Timer RA Timer RA Timer RA Timer RC Timer RC Timer RC Timer RC Timer RC Timer RC Timer RC Number of Data Bus Access States Width 8 8 8 8 8 16* 16* 16* 16* 16* 16* 16* 16* 8 8 8 8 8 8 16* 16* 16* 2 2 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 H'FF06B8 H'FF06B9 H'FF06BA H'FF06BB H'FF06BC H'FF06C0 H'FF06D0 H'FF06D1 H'FF06D2 H'FF06D3 H'FF06D4 H'FF06D5 H'FF06DA H'FF06F0 H'FF06F1 H'FF06F2 H'FF06F3 H'FF06F4 H'FF06F5 H'FFFF80 H'FFFF82 H'FFFF84 H'FFFF86 H'FFFF88 H'FFFF8A H'FFFF8B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 7 7 7 7 7 7 7 General register A* General register B* 5 2 5 2 General register C* General register D* 5 16* 16* 8 8 2 5 2 Timer RC mode register* TRCMR 5 Timer RC control register 1* TRCCR1 Rev. 1.00 Oct. 03, 2008 Page 895 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Timer RC interrupt enable 5 register* Timer RC status register* 5 Number Abbreviation of Bits Address TRCIER TRCSR 5 Module Timer RC Timer RC Timer RC Timer RC Timer RC Timer RC Timer RC Timer RC WDT WDT WDT WDT WDT Timer RB Timer RB Timer RB Timer RB Timer RB Timer RB Timer RB Timer RB Timer RE Timer RE Timer RE Timer RE Timer RE Timer RE Number of Data Bus Access States Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFFF8C H'FFFF8D H'FFFF8E H'FFFF8F H'FFFF90 H'FFFF91 H'FFFF92 H'FFFF93 H'FFFF98 H'FFFF99 H'FFFF9A H'FFFF9B H'FFFF9C H'FFFFA0 H'FFFFA1 H'FFFFA2 H'FFFFA3 H'FFFFA4 H'FFFFA5 H'FFFFA6 H'FFFFA7 H'FFFFA8 H'FFFFA9 H'FFFFAA H'FFFFAB H'FFFFAC H'FFFFAD Timer RC I/O control register 0* Timer RC I/O control register 1* Timer RC control register 2* 5 TRCIOR0 TRCIOR1 TRCCR2 TRCDF 5 5 Timer RC digital filtering function 5 select register* Timer RC output enable register* Timer RC A/D conversion start 5 trigger control register* Timer counter WD Timer mode register WD Timer control/status register WD Timer interrupt control/status register WD Timer interrupt flag register WD Timer RB control register TRCOER TRCADCR TCWD TMWD TCSRWD TICRWD TIFRWD TRBCR Timer RB one-shot control register TRBOCR Timer RB I/O control register Timer RB mode register Timer prescaler register Timer RB secondary register Timer RB primary register Timer RB interrupt request status register Timer RE second data register Timer RE minute data register Timer RE hour data register Timer RE day-of-week data register Timer RE control register 1 Timer RE control register 2 TRBIOC TRBMR TRBPRE TRBSC TRBPR TRBIR TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 Rev. 1.00 Oct. 03, 2008 Page 896 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Timer RE interrupt flag register Time RE clock source register Timer RD counter_0 General register A_0 General register B_0 General register C_0 General register D_0 Timer RD counter_1 General register A_1 General register B_1 General register C_1 General register D_1 Timer RD control register_0 Timer RD I/O control register A_0 Timer RD I/O control register C_0 Timer RD status register_0 Timer RD interrupt enable register_0 PWM mode output level control register_0 Timer RD digital filtering function select register_0 Timer RD control register_1 Timer RD I/O control register A_1 Timer RD I/O control register C_1 Timer RD status register_1 Timer RD interrupt enable register_1 PWM mode output level control register_1 Timer RD digital filtering function select register_1 Number Abbreviation of Bits Address TREIFR TRECSR TRDCNT_0 GRA_0 GRB_0 GRC_0 GRD_0 TRDCNT_1 GRA_1 GRB_1 GRC_1 GRD_1 TRDCR_0 TRDIORA_0 TDRIORC_0 TRDSR_0 TRDIER_0 POCR_0 TRDDF_0 TRDCR_1 TRDIORA_1 TDRIORC_1 TRDSR_1 TRDIER_1 POCR_1 TRDDF_1 8 8 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFFFAE H'FFFFAF H'FFFFB0 H'FFFFB2 H'FFFFB4 H'FFFFB6 H'FFFFB8 H'FFFFBA H'FFFFBC H'FFFFBE H'FFFFC0 H'FFFFC2 H'FFFFC4 H'FFFFC5 H'FFFFC6 H'FFFFC7 H'FFFFC8 H'FFFFC9 H'FFFFCA H'FFFFCB H'FFFFCC H'FFFFCD H'FFFFCE H'FFFFCF H'FFFFD0 H'FFFFD1 Module Timer RE Timer RE Number of Data Bus Access States Width 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 16* Timer RD unit 0 2 16* (channel 0) 2 16* 16* 16* 2 2 16* Timer RD unit 0 2 16* (channel 1) 2 16* 16* 16* 8 Timer RD unit 0 8 (channel 0) 8 8 8 8 8 8 Timer RD unit 0 8 (channel 1) 8 8 8 8 8 2 2 2 Rev. 1.00 Oct. 03, 2008 Page 897 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Timer RD start register_01 Timer RD mode register_01 Number Abbreviation of Bits Address TRDSTR_01 TRDMDR_01 8 8 8 8 H'FFFFD2 H'FFFFD3 H'FFFFD4 H'FFFFD5 H'FFFFD6 H'FFFFD7 H'FFFFD8 H'FFFFD9 H'FFFFDC H'FFFFDD H'FFFFDE H'FFFFE0 H'FFFFE1 H'FFFFE2 H'FFFFE4 H'FFFFE5 H'FFFFE7 H'FFFFE8 H'FFFFE9 H'FFFFEA H'FFFFEC H'FFFFF0 H'FFFFF1 H'FFFFF2 H'FFFFF4 H'FFFFF5 H'FFFFF7 Module Timer RD unit 0 (channels 0 and 1 in common) Number of Data Bus Access States Width 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Timer RD PWM mode register_01 TRDPMR_01 Timer RD function control register_01 Timer RD output master enable register 1_01 Time RD output master enable register 2_01 Timer RD output control register_01 Timer RC A/D conversion start trigger control register_01 Module standby control register 1 Module standby control register 2 Module standby control register 3 Port data register 1 Port data register 2 Port data register 3 Port data register 5 Port data register 6 Port data register 8 Port data register 9* Port data register A Port data register B Port data register J Port control register 1 Port control register 2 Port control register 3 Port control register 5 Port control register 6 Port control register 8 1 TRDFCR_01 TRDOER1_01 8 TRDOER2_01 8 TRDOCR_01 TRDADCR_0 1 MSTCR1 MSTCR2 MSTCR3 PDR1 PDR2 PDR3 PDR5 PDR6 PDR8 PDR9 PDRA PDRB PDRJ PCR1 PCR2 PCR3 PCR5 PCR6 PCR8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 SYSTEM SYSTEM SYSTEM I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port I/O Port 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 1.00 Oct. 03, 2008 Page 898 of 962 REJ09B0465-0100 Section 27 List of Registers Register Name Port control register 9* Port control register A Port control register B Port control register J 1 Number Abbreviation of Bits Address PCR9 PCRA PCRB PCRJ 8 8 8 8 H'FFFFF8 H'FFFFF9 H'FFFFFA H'FFFFFC Module I/O Port I/O Port I/O Port I/O Port Number of Data Bus Access States Width 8 8 8 8 2 2 2 2 Note: 1. 2. 3. 4. Not provided for the H8S/20103 Group. These addresses are reserved. Only 16-bit access is allowed. Access in 8-bit unit. Not provided for the H8S/20103 Group and H8S/20203 Group. These addresses are reserved. 5. Provided only for the H8S/20103 group. Addresses for the other groups are reserved. 6. Provided only for the H8S/20223 group. Addresses for the other groups are reserved. 7. Although these addresses are connected to the 16-bit bus, rewriting proceeds in byte units. Rev. 1.00 Oct. 03, 2008 Page 899 of 962 REJ09B0465-0100 Section 27 List of Registers 27.2 Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row. Register Abbreviation PMR1 PMR2 PMR3 PMR5 PMR6 PMR8 PMR9*1 PMRA ICSUSR PMRJ PUCR1 PUCR2 PUCR3 PUCR5 PUCR6 PUCR8 PUCR9* PUCRA PUCRB PUCRJ PDVR1 PDVR2 PDVR3 PDVR5 1 Bit 7 PMR17 PMR27 PMR37 PMR57 PMR67 PMR87 PMR97 PMRA7 PUCR17 PUCR27 PUCR37 PUCR67 PUCR87 PUCR97 PUCRA7 PUCRB7 PVDR17 PVDR27 PVDR37 Bit 6 PMR16 PMR26 PMR36 PMR56 PMR66 PMR86 PMR96 PMRA6 PUCR16 PUCR26 PUCR36 PUCR66 PUCR86 PUCR96 PUCRA6 PUCRB6 PVDR16 PVDR26 PVDR36 Bit 5 PMR15 PMR25 PMR35 PMR55 PMR65 PMR85 PMR95 PMRA5 PUCR15 PUCR25 PUCR35 PUCR55 PUCR65 PUCR85 PUCR95 PUCRA5 PUCRB5 PVDR15 PVDR25 PVDR35 PVDR55 Bit 4 PMR14* PMR24 PMR34 PMR54 PMR64 PMR94 PMRA4 PUCR14* PUCR24 PUCR34 PUCR54 PUCR64 PUCR94 PUCRA4 PUCRB4 PVDR14* PVDR24 PVDR34 PVDR54 1 1 1 Bit 3 PMR13 PMR23 PMR33 PMR53 PMR63 PMR93 PMRA3** PUCR13 PUCR23 PUCR33 PUCR53 PUCR63 PUCR93 PUCRA3* PUCRB3 PVDR13 PVDR23 PVDR33 PVDR53 1 2 Bit 2 PMR12 PMR22 PMR32 PMR52 PMR52 PMR92 PMRA2 PUCR12 PUCR22 PUCR32 PUCR52 PUCR62 PUCR92 PUCRA2* PUCRB2 PVDR12 PVDR22 PVDR32 PVDR52 1 Bit 1 PMR11 PMR21 PMR31 PMR51 PMR61 PMR91 PMRJ1 PUCR11 PUCR21 PUCR31 PUCR51 PUCR61 PUCR91 PUCRA1* PUCRB1 PUCRJ1 PVDR11 PVDR21 PVDR31 PVDR51 1 Bit 0 PMR10* PMR20 PMR30 PMR50 PMR60 PMR90 SELISU PMRJ0 PUCR10* PUCR20 PUCR30 PUCR50 PUCR60 PUCR90 PUCRA0*1 PUCRB0 PUCRJ0 PVDR10*1 PVDR20 PVDR30 PVDR50 1 1 Module I/O Port II2/SSU I/O Port Rev. 1.00 Oct. 03, 2008 Page 900 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation PDVR6 PDVR8 PDVR9* 1 Bit 7 PVDR67 PVDR87 PVDR97 B0WI Bit 6 PVDR66 PVDR86 PVDR96 Bit 5 PVDR65 PVDR85 PVDR95 P11MD[2:0] P13MD[2:0] P15MD[2:0] P17MD[2:0] P21MD[2:0] P23MD[2:0] P25MD[2:0] P27MD[2:0] P31MD[2:0] P33MD[2:0] P35MD[2:0] P37MD[2:0] P51MD[2:0] P53MD[2:0] P55MD[2:0] P57MD[2:0] P61MD[2:0] P63MD[2:0] P65MD[2:0] P85MD[2:0] P87MD[2:0] P91MD[2:0] P93MD[2:0] P95MD[2:0] P97MD[2:0] Bit 4 PVDR64 PVDR94 Bit 3 PVDR63 PVDR93 Bit 2 PVDR62 PVDR92 Bit 1 PVDR61 PVDR91 P10MD[2:0]* P12MD[2:0] P14MD[2:0]*1 P16MD[2:0] P20MD[2:0] P22MD[2:0] P24MD[2:0] P26MD[2:0] P30MD[2:0] P32MD[2:0] P34MD[2:0] P36MD[2:0] P50MD[2:0] P52MD[2:0] P54MD[2:0] P56MD[2:0] P60MD[2:0] P62MD[2:0] P64MD[2:0] 1 Bit 0 PVDR60 PVDR90 Module I/O Port PMCR11 PMCR12 PMCR13 PMCR14 PMCR21 PMCR22 PMCR23 PMCR24 PMCR31 PMCR32 PMCR33 PMCR34 PMCR51 PMCR52 PMCR53 PMCR54 PMCR61 PMCR62 PMCR63 PMCR83 PMCR84 PMCR91*1 PMCR92* PMCR93* PMCR94* PMCWPR PMCRA3 1 PMC P86MD[2:0] P90MD[2:0] P92MD[2:0] P94MD[2:0] P96MD[2:0] 1 1 PMCRWE PA5[MD2:0] PA4[MD2:0] Rev. 1.00 Oct. 03, 2008 Page 901 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation PMCRA4 LINCR LINST INTCR IER ISCRH ISCRL ISR INCCR VOFR Bit 7 LINE IRQ7E Bit 6 Bit 5 PA7[MD2:0] Bit 4 Bit 3 Bit 2 Bit 1 PA6[MD2:0] Bit 0 Module PMC MST IRQ6E SBE B2CLR LSTART B1CLR INTM[1:0] RXDSF B0CLR NMIEG IRQ3E BCIE BCDCT ADTRG1 IRQ2E SBIE SBDCT ADTRG0 IRQ1E SFIE SFDCT IRQ0E HW-LIN Interrupt IRQ5E IRQ4E [IRQ7CB:IRQ7CA] [IRQ3CB:IRQ3CA] IRQ7F IRQ6F [IRQ6CB:IRQ6CA] [IRQ2CB:IRQ2CA] IRQ5F IRQ4F INCCR[5:4] [IRQ5CB:IRQ5CA] [IRQ1CB:IRQ1CA] IRQ3F IRQ2F INCCR[3:2] [IRQ4CB:IRQ4CA] [IRQ0CB:IRQ0CA] IRQ1F IRQ0F INCCR[1:0] ELCSR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTCERH DTVECR IPRA[7:6] IPRB[7:6] IPRC[7:6] IPRD[7:6] IPRE[7:6] IPRH[7:6] IPRI[7:6] DTCEA7 DTCEB7 DTCEC7 DTCED7 DTCEE7 DTCEF7 SWDTE DTCEA6 DTCEB6 DTCEC6 DTCED6 DTCEE6 DTCEF6 DTVEC6 DTCEA5 DTCEB5 DTCEC5 DTCEE5 DTCEF5 DTVEC5 IPRG[5:4] IPRH[5:4] DTCEA4 DTCEB4 DTCEC4 DTCEE4 DTCEF4 DTCEG4 DTVEC4 DTCEA3 DTCEB3 DTCED3 DTCEE3 DTCEF3 DTCEG3 DTCEH3 DTVEC3 IPRA[5:4] IPRB[5:4] IPRC[5:4] IPRD[5:4]*2 IPRE[5:4] ELIE2 ELIE1 IPRA[3:2] IPRB[3:2] IPRC[3:2] IPRD[3:2] IPRE[3:2] IPRF[3:2] IPRG[3:2] IPRH[3:2]*4 IPRI[3:2] DTCEA2 DTCEB2 DTCED2 DTCEE2 DTCEF2 DTCEG2 DTCEH2 DTVEC2 ELF2 ELF1 IPRA[1:0] IPRB[1:0] IPRC[1:0] IPRD[1:0] IPRG[1:0]*3 IPRH[1:0]*4 DTCEA1 DTCEB1 DTCED1 DTCEE1 DTCEF1 DTCEG1 DTVEC1 DTCEA0 DTCEB0 DTCED0 DTCEE0 DTCEF0 DTCEG0 DTVEC0 DTC Rev. 1.00 Oct. 03, 2008 Page 902 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation SMR BRR SCR3 TDR SSR RDR SPMR SMR_2 BRR_2 SCR3_2 TDR_2 SSR_2 RDR_2 SPMR_2 SMR_3 BRR_3 SCR3_3 TDR_3 SSR_3 RDR_3 SPMR_3 TRDCNT_2* 5 Bit 7 COM Bit 6 CHR Bit 5 PE Bit 4 PM Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCI3_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF OER FER PER TEND MPBR MPBT COM CHR PE PM STOP NFEN MP CKS1 CKS0 SCI3_2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF OER FER PER TEND MPBR MPBT COM CHR PE PM STOP NFEN MP CKS1 CKS0 SCI3_3 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF OER FER PER TEND MPBR MPBT NFEN Timer RD Unit 1 (channel 2) GRA_2*5 GRB_2*5 GRC_2*5 GRD_2*5 Rev. 1.00 Oct. 03, 2008 Page 903 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation TRDCNT_3*5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Timer RD Unit 1 (channel 3) GRA_3*5 GRB_3*5 GRC_3*5 GRD_3*5 TRDCR_2*5 TRDIORA_2* 5 CCLR[2:0] IOB[2:0] IOD[3:0] DFCK[1:0] CCLR[2:0] 5 CKEG[1:0] TPSC[2:0] IOA[2:0] IOC[3:0] Timer RD Unit 1 (channel 2) TRDIORC_2* TRDSR_2*5 TRDIER_2* POCR_2*5 TRDDF_2*5 TRDCR_3* 5 5 5 OVF OVIE IMFD IMIED DFD CKEG[1:0] IMFC IMIEC POLD DFC IMFB IMIEB POLC DFB TPSC[2:0] IOA[2:0] IOC[3:0] IMFA IMIEA POLB DFA Timer RD Unit 1 (channel 3) TRDIORA_3* IOB[2:0] IOD[3:0] TRDIORC_3*5 TRDSR_3*5 TRDIER_3* POCR_3* 5 5 DFCK[1:0] UDF BFD0 PWMC1 ADEG EB1 OVF OVIE BFC0 PWMB1 ADTRG EA1 IMFD IMIED DFD CSTPN1 OLS1 ED0 IMFC IMIEC POLD DFC CSTPN0 PWMD0 OLS0 EC0 IMFB IMIEB POLC DFB STR1 PWMC0 IMFA IMIEA POLB DFA STR0 SYNC PWMB0 CMD[1:0] Timer RD Unit 1 (channels 2 TRDDF_3*5 TRDSTR_23*5 TRDMDR_23* 5 BFD1 PWM3 BFC1 PWMD1 STCLK EC1 TRDPMR_23*5 TRDFCR_23*5 and 3 in common) TRDOER1_23*5 ED1 EB0 EA0 Rev. 1.00 Oct. 03, 2008 Page 904 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 TOC1 ADTRGC1E Bit 5 TOB1 ADTRGB1E Bit 4 TOA1 ADTRGA1E Bit 3 TOD0 Bit 2 TOC0 Bit 1 TOB0 Bit 0 TOA0 Module Timer RD Unit 1 TRDOER2_23*5 PTO TRDOCR_23* 5 TOD1 ADTRGD1E TRDADCR_23 ADTRGD0E ADTRGC0E (channels 2 ADTRGB0E ADTRGA0E and 3 in common) ICCR1 SSCRH ICCR2 SSCRL ICMR SSMR ICIER SSER ICSR SSSR SAR SSMR2 ICDRT SSTDR ICDRR SSRDR DADR0 DADR1 DACR IrCR ICE BBSY MLS MLS TIE TIE TDRE TDRE SAV6 BIDE RCVD RSSTP SCP WAIT CPOS TEIE TEIE TEND TEND SAV5 SCKS MST MSS SDAO SOL CPHS RIE RIE RDRF RDRF SAV4 CSS1 TRS SDAOP SOLP NAKIE TE NACKF SAV3 CSS0 SCLO BCWP STIE RE STOP SAV2 SCKOS ACKE AL_OVE ORER SAV1 SOOS CKS[3:0] CKS[2:0] IICRST SRES BC[2:0] BC[2:0] ACKBR AAS SAV0 SCOS ACKBT CEIE ADZ CE FS SSUMS IIC2/SSU D/A converter DAOE1 IrE DAOE0 IrCK[2:0] IrTXINV IrRXINV SCI3_2 (IrDA) ADDR0 CMPR ADDR1 CMP7 CMP6 CMP5 CMP4 CMP3 CMP2 CMP1 CMP0 A/D converter (unit 1) Rev. 1.00 Oct. 03, 2008 Page 905 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation CMPCSR ADDR2 Bit 7 CMPF Bit 6 CMPIE Bit 5 CMPFC1 Bit 4 CMPFC0 Bit 3 Bit 2 Bit 1 Bit 0 Module A/D converter (unit 1) CMPVALH ADDR3 CMPVALL ADDR4 ADDR5 ADDR6 ADDR7 ADCSR ADCR ADMR ADDR0_2* 6 VAL9 VAL8 VAL4 VAL3 VAL2 VAL1 VAL0 VAL7 VAL6 VAL5 SCANS CH[3:0] ADF ADIE TRGS[1:0] ADST SCANE ADM1 CKS[1:0] ADSTCLR EXTRGS A/D converter CMPR_2*6 ADDR1_2* 6 CMP3 CMP2 CMP1 CMP0 (unit 2)*6 CMPCSR*6 ADDR2_2*6 CMPVALH_2* 6 CMPFC0 CMPF CMPIE CMPFC1 VAL9 VAL8 Rev. 1.00 Oct. 03, 2008 Page 906 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation Bit 7 ADDR3_2*6 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module A/D converter CMPVALL_2*6 VAL7 ADCSR_2* ADCR_2* 6 6 VAL4 SCANS PRST VD2DFCK0 VD1DFCK0 VD0DFCK0 TRMDRWE VAL3 VAL2 VAL1 CH[2:0] VAL0 (unit2) *6 VAL6 ADIE TRGS[1:0] VAL5 ADST SCANE ADM1 SWRST VD2DFCK1 VD2RVS VD1DFCK1 VD0DFCK1 LOCKDW ADF CKS[1:0] LVD2RST VD2DFS VD1DFS VD1LS3 VD0DFS LVD1RST VD2IRCS VD1IRCS VD1LS2 ADSTCLR PORRST VD2MS VD1MS VD1LS1 VD0LS1 EXTRGS WRST VD2RE VD1RE VD1LS0 LDPRC Clock oscillator Low-voltagedetection circuit ADMR_2* RSTFR LD2CRH LD2CRL LD1CRH LD1CRL LD0CRH LD0CRL VDCPR HOCR 6 VD2DF VD2E VD1DF VD1E WRI HOCOE WI VD2UF VD2CVS VD1UF WE HOTRMDPR HOTRMDR1 HOTRMDR2 HOTRMDR3 HOTRMDR4 TRGCNT Timer RG GRA GRB TRGMDR TRGCNTCR TRGCR TRGIOR TRGSR STR CNTEN7 BUFB CNTEN6 DFCK[1:0] CNTEN5 CNTEN4 DFB CNTEN3 CKEG[1:0] BUFA DFA CNTEN2 MDF CNTEN1 TPSC[2:0] IOA[2:0] PWM CNTEN0 CCLR[1:0] IOB[2:0] DIRF OVF UDF IMFB IMFA Rev. 1.00 Oct. 03, 2008 Page 907 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation Bit 7 TRGIER BRA Bit 6 Bit 5 Bit 4 Bit 3 OVIE Bit 2 UDIE Bit 1 IMIEB Bit 0 IMIEA Module Timer RG BRB FLMCR1 FLMCR2 DFPR FLMSTR ELSR0 ELSR1 ELSR2* ELSR3 ELSR4 ELSR8 ELSR10 ELSR11*6 ELSR12 ELSR14 ELSR15 ELSR18 ELSR19 ELSR21 ELSR22 ELSR23 ELSR24 ELSR29 ELSR30 ELSR31 ELSR32 7 FMRDYIF ELS07 ELS17 ELS27 ELS37 ELS47 ELS87 ELS107 ELS117 ELS127 ELS147 ELS157 ELS187 ELS197 ELS217 ELS227 ELS237 ELS247 ELS297 ELS307 ELS317 ELS327 FMRDYIE FMERSF ELS04 ELS14 ELS24 ELS34 ELS44 ELS84 ELS104 ELS114 ELS124 ELS144 ELS154 ELS184 ELS194 ELS214 ELS224 ELS234 ELS244 ELS294 ELS304 ELS314 ELS324 FMLBD FMWUS FMEWMOD FMSPREQ DFPR1 ELS01 ELS11 ELS21 ELS31 ELS41 ELS81 ELS101 ELS111 ELS121 ELS141 ELS151 ELS181 ELS191 ELS211 ELS221 ELS231 ELS241 ELS291 ELS301 ELS311 ELS321 FMCMDEN FMSPEN DFPR0 FMRDY ELS00 ELS10 ELS20 ELS30 ELS40 ELS80 ELS100 ELS110 ELS120 ELS140 ELS150 ELS180 ELS190 ELS210 ELS220 ELS230 ELS240 ELS290 ELS300 ELS310 ELS320 FLASH FMBSYRDIE FMISPE FMPRSF ELS03 ELS13 ELS23 ELS33 ELS43 ELS83 ELS103 ELS113 ELS123 ELS143 ELS153 ELS183 ELS193 ELS213 ELS223 ELS233 ELS243 ELS293 ELS303 ELS313 ELS323 ELS02 ELS12 ELS22 ELS32 ELS42 ELS82 ELS102 ELS112 ELS122 ELS142 ELS152 ELS182 ELS192 ELS212 ELS222 ELS232 ELS242 ELS292 ELS302 ELS312 ELS322 FMBSYRDIF FMEBSF ELS06 ELS16 ELS26 ELS36 ELS46 ELS86 ELS106 ELS116 ELS126 ELS146 ELS156 ELS186 ELS196 ELS216 ELS226 ELS236 ELS246 ELS296 ELS306 ELS316 ELS326 ELS05 ELS15 ELS25 ELS35 ELS45 ELS85 ELS105 ELS115 ELS125 ELS145 ELS155 ELS185 ELS195 ELS215 ELS225 ELS235 ELS245 ELS295 ELS305 ELS315 ELS325 ELC Rev. 1.00 Oct. 03, 2008 Page 908 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation Bit 7 PGR1 PGR2 PGC1 PGC2 PDBF1 PDBF2 PEL0 PEL1 PEL2 PEL3 ELOPA ELOPB ELOPC ELTMCR ELTMSA ELTMSB ELTMDR ELCR ELTMCNT PGR17 PGR27 PDBF17 PDBF27 Bit 6 PGR16 PGR26 Bit 5 PGR15 PGR25 PGCO1[2:0] PGCO2[2:0] Bit 4 PGR14 PGR24 Bit 3 PGR13 PGR23 Bit 2 PGR12 PGR22 PGCOVE1 PGCOVE2 PDBF12 PDBF22 PSP02 PSP12 PSP22 PSP32 TMRCM[2:1]* 3 Bit 1 PGR11 PGR21 Bit 0 PGR10 PGR20 PGCI1[1:0] PGCI2[1:0] Module ELC PDBF16 PDBF26 PDBF15 PDBF25 PSM0[1:0] PSM1[1:0] PSM2[1:0] PSM3[1:0] PDBF14 PDBF24 PDBF13 PDBF23 PSP0[4:3] PSP1[4:3] PSP2[4:3] PSP3[4:3] PDBF11 PDBF21 PSP01 PSP11 PSP21 PSP31 PDBF10 PDBF20 PSP00 PSP10 PSP20 PSP30 TMRAM[2:1] TMRD2M[2:1] TMRG1M[2:1] TMRSTR C1CLS[3:0] C3CLS[3:0] C3DLY[1:0] ELCON TMRBM[2:1] TMRDM[2:1] CLSRS[3:0] C0CLS[3:0] C2CLS[3:0] C2DLY[1:0] C1DLY[1:0] C0DLY[1:0] SYSCCR LPCR1 LPCR2 LPCR3 BAKCR OSCCSR RSTCR TRACR TRAIOC TRAMR WI WI WI WI WI WI WE WE WE WE WE WE TIOGT[1:0] PHIHSEL SSBY STBYINT OSCBAKE TUNDF PHILSEL PSCSTP SLEEPINT BAKCKSEL TEDGF TIPF[1:0] SLEEPRS CKSWIE STS3 TIOSEL SUBNC1 STBYRS PHI2 PHIS2 CKSWIF STS2 TSTOP TOENA SUBNC0 PHI1 PHIS1 OSCHLT STS1 TCSTF TOPCR TMOD[2:0] PHIBSEL PHI0 PHIS0 STS0 SRST TSTART TEDGSEL Clock oscillator Timer RA TCKCUT TCK[2:0] Rev. 1.00 Oct. 03, 2008 Page 909 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation Bit 7 TRAPRE TRATR TRAIR TRCCNT* 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Timer RA TRAIE TRAIF Timer RC GRA*7 GRB*7 GRC*7 GRD*7 TRCMR*7 TRCCR1* TRCIER*7 TRCSR*7 TRCIOR0* TRCIOR1* TRCCR2* TRCDF* 7 7 7 7 CTS CCLR OVIE OVF BUFEB CKS[2:0] BUFEA PWM2 TOD PWMD TOC IMIEC IMFC PWMC TOB IMIEB IMFB IOA[2:0] IOC[3:0] PWMB TOA IMIEA IMFA IOB[2:0] IOD[3:0] IMIED IMFD 7 TCEG[1:0] DFCK[1:0] CSTP DFTRG DFD ED ADTRGDE POLD DFC EC ADTRGCE POLC DFB EB ADTRGBE POLB DFA EA ADTRGAE WDT TRCOER* 7 PTO 7 TRCADCR* TCWD TMWD TCSRWD TICRWD TIFRWD TRBCR TRBOCR B6WI TCWE INTSEL[1:0] B4WI IWIE TCSRWE TMWLOCK TMWI TSTOP TOSSTF CKS[3:0] TCSTF TOSSP TSTART TOSST Timer RB IWF Rev. 1.00 Oct. 03, 2008 Page 910 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation Bit 7 TRBIOC TRBMR TRBPRE TRBSC TRBPR TRBIR TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TREIFR TRECSR TRDCNT_0 TRBIE BSY BSY BSY BSY TSTART TCKCUT Bit 6 Bit 5 Bit 4 TIPF[1:0] Bit 3 INOSEG TWRC Bit 2 INOSTG Bit 1 TOCNT Bit 0 TOPL TMOD[1:0] Module Timer RB TCK[2:0] TRBIF SCI2 MN12 H12_H24 RCS6 SCI1 MN11 HR11 PM COMIE COMF RCS5 SCI0 MN10 HR10 TRERST WKIE WKF RCS4 SC03 MN03 HR03 INT DYIE DYF RCS3 SC02 MN02 HR02 WK2 TOENA HRIE HRF RCS2 SC01 MN01 HR01 WK1 TCSTF MNIE MNF RCS1 SC00 MN00 HR00 WK0 SEIE SECF RCS0 Timer RD Unit 0 (channel 0) Timer RE GRA_0 GRB_0 GRC_0 GRD_0 TRDCNT_1 Timer RD Unit 0 (channel 1) GRA_1 GRB_1 Rev. 1.00 Oct. 03, 2008 Page 911 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation Bit 7 GRC_1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Timer RD Unit 0 (channel 1) GRD_1 TRDCR_0 TRDIORA_0 TRDIORC_0 TRDSR_0 TRDIER_0 POCR_0 TRDDF_0 TRDCR_1 TRDIORA_1 TRDIORC_1 TRDSR_1 TRDIER_1 POCR_1 TRDDF_1 TRDSTR_01 TRDMDR_01 TRDPMR_01 TRDFCR_01 BFD1 PWM3 DFCK[1:0] CCLR[2:0] IOB[2:0] IOD[3:0] CCLR[2:0] IOB[2:0] IOD[3:0] DFCK[1:0] BFC1 PWMD1 STCLK EC1 TOC1 UDF BFD0 PWMC1 ADEG EB1 TOB1 OVF OVIE BFC0 PWMB1 ADTRG EA1 TOA1 OVF OVIE CKEG[1:0] TPSC[2:0] IOA[2:0] IOC[3:0] Timer RD Unit 0 (channel 0) IMFD IMIED DFD CKEG[1:0] IMFC IMIEC POLD DFC IMFB IMIEB POLC DFB TPSC[2:0] IOA[2:0] IOC[3:0] IMFA IMIEA POLB DFA Timer RD Unit 0 (channel 1) IMFD IMIED DFD CSTPN1 OLS1 ED0 TOD0 IMFC IMIEC POLD DFC CSTPN0 PWMD0 OLS0 EC0 TOC0 IMFB IMIEB POLC DFB STR1 PWMC0 IMFA IMIEA POLB DFA STR0 SYNC PWMB0 CMD[1:0] Timer RD Unit 0 (channels 0 and 1 in common) TRDOER1_01 ED1 TRDOER2_01 PTO TRDOCR_01 TOD1 EB0 TOB0 ADTRGB0E EA0 TOA0 ADTRGA0E Power-down TRDADCR_01 ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E MSTPCR1 MSTPCR2 MSTWDT MSTAD1 MSTAD2* 2 ADTRGD0E ADTRGC0E MSTDA MSTDTC MSTICSU MSTSCI3_1 MSTSCI3_2 MSTSCI3_3 Rev. 1.00 Oct. 03, 2008 Page 912 of 962 REJ09B0465-0100 Section 27 List of Registers Register Abbreviation Bit 7 MSTPCR3 MSTTMRA Bit 6 MSTTMRB Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSTTMRE Module Power-down MSTTMRC*3 MSTTMRD1 MSTTMRD2 *1 MSTTRMRG PDR1 PDR2 PDR3 PDR5 PDR6 PDR8 PDR9* PDRA PDRB PDRJ PCR1 PCR2 PCR3 PCR5 PCR6 PCR8 PCR9* PCRA PCRB PCRJ 1 1 PDR17 PDR27 PDR37 PDR57 PDR67 PDR87 PDR97 PDRA7 PDRB7 PCR17 PCR27 PCR37 PCR57 PCR67 PCR87 PCR97 PCRA7 PCRB7 PDR16 PDR26 PDR36 PDR56 PDR66 PDR86 PDR96 PDRA6 PDRB6 PCR16 PCR26 PCR36 PCR56 PCR66 PCR86 PCR96 PCRA6 PCRB6 PDR15 PDR25 PDR35 PDR55 PDR65 PDR85 PDR95 PDRA5 PDRB5 PCR15 PCR25 PCR35 PCR55 PCR65 PCR85 PCR95 PCRA5 PCRB5 PDR14*1 PDR24 PDR34 PDR54 PDR64 PDR94 PDRA4 PDRB4 PCR14* PCR24 PCR34 PCR54 PCR64 PCR94 PCRA4 PCRB4 1 PDR13 PDR23 PDR33 PDR53 PDR63 PDR93 PDRA3* PDRB3 PCR13 PCR23 PCR33 PCR53 PCR63 PCR93 PCRA3* PCRB3 1 1 PDR12 PDR22 PDR32 PDR52 PDR62 PDR92 PDRA2* PDRB2 PCR12 PCR22 PCR32 PCR52 PCR62 PCR92 PCRA2* PCRB2 1 1 PDR11 PDR21 PDR31 PDR51 PDR61 PDR91 PDRA1* PDRB1 PDRJ1 PCR11 PCR21 PCR31 PCR51 PCR61 PCR91 PCRA1* PCRB1 PCRJ1 1 1 PDR10*1 PDR20 PDR30 PDR50 PDR60 PDR90 PDRA0*1 PDRB0 PDRJ0 PCR10*1 PCR20 PCR30 PCR50 PCR60 PCR90 PCRA0*1 PCRB0 PCRJ0 I/O port Notes: 1. 2. 3. 4. 5. 6. 7. Not provided for the H8S/20103 Group. These addresses and bits are reserved. Provided for the H8S/20223 Group. These bits for the other groups are reserved. Provided for the H8S/20103 Group. These bits for the other groups are reserved. Not provided for the H8S/20103 Group. These bits are reserved. Not provided for the H8S/20103 Group. These addresses are reserved. Provided for the H8S/20223 Group. These addresses for the other groups are reserved. Provided for the H8S/20103 Group. These addresses for the other groups are reserved. Rev. 1.00 Oct. 03, 2008 Page 913 of 962 REJ09B0465-0100 Section 27 List of Registers Rev. 1.00 Oct. 03, 2008 Page 914 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Section 28 Electrical Characteristics 28.1 Absolute Maximum Ratings Table 28.1 Absolute Maximum Ratings Item Power supply voltage Analog power supply voltage Internal power supply voltage Input voltage All pins (other VIN than AN pin, DA pin, OSC1, and X1) AN pin, DA pin OSC1, X1 OSC1 Operating temperature VIN VIN VIN Topr Tstg Symbol VCC AVCC Value -0.3 to +6.5 -0.3 to +6.5 -0.3 to +1.65 -0.3 to VCC +0.3 Unit V V V V Remark *1 -0.3 to AVCC +0.3 -0.3 to +1.65 -0.3 to VCC +0.3 N version: -20 to +85 D version: -40 to +85 -55 to +125 V V V C C C *2 *3 Storage temperature Note: 1. Permanent damage may result if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. The OSC1 pin is used when the external oscillator function is selected. (PMRJ1 = 1, PMRJ0 = 1) 3. When the external clock input function is selected. (PMRJ1 = 0, PMRJ0 = 1) Rev. 1.00 Oct. 03, 2008 Page 915 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics 28.2 28.2.1 (1) Electrical Characteristics Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range sub (kHz) 32.768 osc (MHz) 20.0 4.0 2.7 hoco (MHz) 20.0 5.5 Vcc(V) loco (kHz) 125.0 2.7 5.5 VCC (V) 16.0 2.7 5.5 VCC (V) 2.7 5.5 VCC (V) Rev. 1.00 Oct. 03, 2008 Page 916 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics (2) Power Supply Voltage and Operating Frequency Range (MHz) 20.0 0.004096 2.7 5.5 Vcc(V) (3) Accuracy Guarantee Range of Analog Power Supply Voltage and A/D Converter osc (MHz) 20.0 4.0 2.7 5.5 AVcc(V) Rev. 1.00 Oct. 03, 2008 Page 917 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics 28.3 DC Characteristics Table 28.2 DC Characteristics (1) Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC AVCC, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Value Item Input high voltage Symbol Applicable Pins VIH RES, NMI IRQ0 to IRQ7 TRAIO, TRGB, FTCI, TRGC, FTIOA, FTIOB, FTIOC, FTIOD, TRCOI, FTIOA0 FTIOB0, FTIOC0, FTIOD0, FTIOA1, FTIOB1, FTIOC1, FTIOD1, TRDOI_0, FTIOA2, FTIOB2, FTIOC2, FTIOD2, FTIOA3, FTIOB3, FTIOC3, FTIOD3, TRDOI_1, TCLKA TCLKB, TGIOA TGIOB, SCK3, SCK3_2, SCK3_3 ADTRG1, ADTRG2 RXD, RXD_2, RXD_3 SCL, SDA, SSCK, SCS, SSI, SSO P10 to P17, P20 to P27, P30 to P37 P50 to P57, P60 to P67 P85 to P87, P90 to P97 PA0 to PA7, PB0 to PB7 PJ1, PJ0 Test Condition Min. Typ. Max. VCC + 0.3 VCC + 0.3 Unit Remark V V VCC = 4.0 to 5.5 V VCC x 0.8 VCC x 0.9 VCC = 4.0 to 5.5 V VCC x 0.7 VCC x 0.8 VCC + 0.3 VCC + 0.3 V V OSC1 VCC = 4.0 to 5.5 V VCC - 0.5 PMRJ[1:0] = 01 PMRJ[1:0] = 01 VCC - 0.3 VCC + 0.3 VCC + 0.3 V V Note: Connect the TEST pin to Vss. Rev. 1.00 Oct. 03, 2008 Page 918 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Value Item Input low voltage Symbol Applicable Pins VIL RES, NMI IRQ0 to IRQ7 TRAIO, TRGB, FTCI, TRGC, FTIOA, FTIOB, FTIOC, FTIOD, TRCOI FTIOA0 FTIOB0, FTIOC0, FTIOD0, FTIOA1, FTIOB1, FTIOC1, FTIOD1, TRDOI_0, FTIOA2, FTIOB2, FTIOC2, FTIOD2, FTIOA3, FTIOB3, FTIOC3, FTIOD3, TRDOI_1, TCLKA TCLKB, TGIOA TGIOB, SCK3, SCK3_2, SCK3_3 ADTRG1, ADTRG2, RXD, RXD_2, RXD_3, SCL, SDA, SSCK, SCS, SSI, SSO P10 to P17 P20 to P27 P30 to P37 P50 to P57 P60 to P67 P85 to P87 P90 to P97 PA0 to PA7 PB0 to PB7 PJ, PJ0 Test Condition VCC = 4.0 to 5.5V Min. -0.3 Typ. Max. Unit Remark VCC x 0.2 V -0.3 VCC x 0.1 V VCC = 4.0 to 5.5V -0.3 VCC x 0.3 V -0.3 VCC x 0.2 V OSC1 VCC = 4.0 to 5.5V PMRJ[1:0] = 01 PMRJ[1:0] = 01 -0.3 -0.3 0.5 0.3 V V Rev. 1.00 Oct. 03, 2008 Page 919 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Item Applicable Symbol Pins P10 to P17 P20 to P27 P30 to P37 P50 to P55 P60 to P67 P85 to P87 P90 to P97 Setting Condition Test Condition Value Min. Typ. Max. Unit Remark V Output high VOH voltage PDVRn0 to 7 = VCC = 4.0 to VCC -1.0 0 5.5 V -IOH = 5.0mA (n = 1, 2, 3, 5, 6, 8, 9) -IOH = 0.1mA VCC -0.5 V PDVRn0 to 7 = VCC = 4.0 to 1 5.5V (n = 1, 2, 3, 5, 6, 8, 9) -IOH = 20.0mA VCC = 4.0 to 5.5V -IOH = 10.0mA VCC = 4.0 to 5.5V -IOH = 5.0mA - IOH = 0.1mA VCC -1.5 V Reference value VCC -1.0 V Reference value VCC -0.5 V Reference value VCC -1.0 VCC -0.4 V V Reference value PA0 to PA7 PB0 to PB7 PJ0, PJ1 VCC = 4.0 to 5.5V -IOH = 5.0mA -IOH = 0.1mA VCC -0.5 V P56, P57 4.0 VCC 5.5V -IOH = 0.1mA 3.0 VCC < 4.0V -IOH = 0.1mA VCC -2.5 V VCC -2.0 V Rev. 1.00 Oct. 03, 2008 Page 920 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Item Applicable Symbol Pins P10 to P17 P20 to P27 P30 to P37 P50 to P57 P60 to P67 P85 to P87 P90 to P97 Setting Condition Test Condition Value Min. Typ. Max. Unit Remark 0.6 V Output low VOL voltage PDVRn0 to 7 = VCC = 4.0 to 0 5.5V (n = 1, 2, 3, 5, 6, 8, 9) IOL = 1.6mA IOL = 0.4mA 0.4 1.5 V V PDVRn0 to 7 = VCC = 4.0 to 1 5.5V (n = 1, 2, 3, 5, 6, 8, 9) IOL = 20.0mA IOL = 5.0mA VCC = 4.0 to 5.5V IOL = 1.6mA IOL = 0.4mA 0.6 1.0 V V Reference value 0.4 0.6 V V Reference value PA0 to PA7 PB0 to PB7 PJ0, PJ1 VCC = 4.0 to 5.5V IOL = 1.6mA IOL = 0.4mA 0.4 V SCL, SDA VCC = 4.0 to 5.5V IOL = 6.0mA IOL = 3.0mA 0.6 V 0.4 V Rev. 1.00 Oct. 03, 2008 Page 921 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Item Input/output leakage current Symbol IIL Applicable Pins NMI, IRQ0 to IRQ7 TRAIO,TRGB, FTCI, TRGC, FTIOA FTIOB, FTIOC, FTIOD, TRCOI, FTIOA0, FTIOB0, FTIOC0, FTIOD0, FTIOA1, FTIOB1, FTIOC1, FTIOD1 TRDOI_0, FTIOA2 FTIOB2, FTIOC2, FTIOD2 FTIOA3, FTIOB3, FTIOC3, FTIOD3 TRDOI_1, TCLKA TCLKB, TGIOA TGIOB, SCK3 SCK3_2, SCK3_3 ADTRG1, ADTRG2 RXD, RXD_2, RXD_3 SCL, SDA SSCK, SCS SSI, SSO, OSC1 P10 to P17 P20 to P27 P30 to P37 P50 to P57 P60 to P67 P85 to P87 P90 to P97 PA0 to PA7 PB0 to PB7 PJ1, PJ0 Value Test Condition VIN = 0.5 V to (VCC - 0.5 V) Min. Typ. Max 1.0 Unit A Remark Rev. 1.00 Oct. 03, 2008 Page 922 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Item Pull-up MOS current Symbol -Ip Applicable Pins P10 to P17 P20 to P27 P30 to P37 P50 to P57 P60 to P67 P85 to P87 P90 to P97 PA0 to PA7 PB0 to PB7 PJ1, PJ0 Value Test Condition VCC = 5.0 V, VIN = 0.0 V VCC = 3.0 V, VIN = 0.0 V Min. 40.0 Typ. 40.0 Max 200.0 Unit A Remark A Reference value Input capacitance CIN All input pins except power supply pins VCC = 1MHz, VIN = 0.0 V, Ta = 25C Active mode 1, OSC = 20MHz Active mode 1, OSC = 10MHz 15.0 pF Active mode lOPE1 supply current T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D mA mA mA mA mA mA mA mA * Reference value* lOPE2 VCC Active mode 2, OSC = 20MHz Active mode 2, OSC = 10MHz * Reference value* lOPE3 VCC Active mode 3, OSC = 20MHz Active mode 3, OSC = 10MHz * Reference value* lOPE4 lOPE5 VCC VCC Active mode 4, SUB = 32kHz Active mode 5, SUB = 32kHz * Reference value* Rev. 1.00 Oct. 03, 2008 Page 923 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Item Symbol Applicable Pins VCC Value Test Condition Sleep mode 1, OSC = 20MHz Sleep mode 1, OSC = 10MHz Min. Typ. T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D Max T.B.D T.B.D T.B.D T.B.D Unit mA mA mA mA mA mA mA mA A * Reference value* Remark * Reference value* Sleep mode lSLEEP1 supply current lSLEEP2 VCC Sleep mode 2, OSC = 20MHz Sleep mode 2, OSC = 10MHz * Reference value* lSLEEP3 VCC Sleep mode 3, OSC = 20MHz Sleep mode 3, OSC = 10MHz * lSLEEP4 lSLEEP5 Standby mode lSTBY supply current VCC VCC VCC Sleep mode 4, sub = 32kHz Sleep mode 5, sub = 32kHz Ta 50 C when 32-kHZ crystal resonator not used Ta > 50 C when 32-kHZ crystal resonator not used * T.B.D A RAM data retaining voltage VRAM VCC 2.0 V Note: * The following table shows pin states during the measurement of supply current except the current through pull-up MOS transistors and output buffers. Rev. 1.00 Oct. 03, 2008 Page 924 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics RES Pin Internal State VCC Operating ( = OSC) Operating ( = OSC/64) Mode Active mode 1 Active mode 2 Active mode 3 Sleep mode 1 Sleep mode 2 Sleep mode 3 Active mode 4 Active mode 5 Sleep mode 4 Sleep mode 5 Standby mode PSCSTP Other Pins Oscillator Pins 0 0 VCC Main clock oscillator: Ceramic resonator or crystal resonator Subclock oscillator: Pin X1 = VSS Operating ( = OSC/128) 0 VCC Only timers operating Only timers operating ( = OSC/64) Only timers operating ( = OSC/128) VCC Operating ( = sub) Operating ( = sub /8) VCC Only timers operating ( = sub) Only timers operating ( = sub /8) VCC Both CPU and timers stopped. 0 0 0 1 1 1 1 VCC Main clock oscillator: Ceramic resonator or crystal resonator Subclock oscillator: Pin X1 = VSS VCC VCC Main clock oscillator: Ceramic resonator or crystal resonator Subclock oscillator: Crystal resonator VCC Rev. 1.00 Oct. 03, 2008 Page 925 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Table 28.3 DC Characteristics (2) Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC AVCC, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Applicable Symbol Pins IOL P10 to P17 P20 to P27 P30 to P37 P50 to P57 P60 to P67 P85 to P87 P90 to P97 PJ0, PJ1 PA0 to PA7, PB0 to PB7 SCL, SDA Allowable output IOL low current (total) All input pins VCC = 4.0 to 5.5 V VCC = 4.0 to 5.5 V VCC = 4.0 to 5.5 V 2.0 0.5 6.0 80 mA mA mA mA PDVRn0 to 7 = 1 (n = 1, 2, 3, 5, 6, 8, 9, J) VCC = 4.0 to 5.5 V 20.0 5.0 mA mA Setting Conditions PDVRn0 to 7 = 0 (n = 1, 2, 3, 5, 6, 8, 9, J) Test Conditions VCC = 4.0 to 5.5 V Value Min. Typ. Max. 2.0 Unit mA Item Allowable output low current (per pin) 0.5 mA 40 mA Rev. 1.00 Oct. 03, 2008 Page 926 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Item Allowable output high current (per pin) Applicable Symbol Pins -IOH P10 to P17 P20 to P27 P30 to P37 P50 to P55 P60 to P67 P85 to P87 P90 to P97 PJ0, PJ1 PA0 to PA7, PB0 to PB7 P56, P57 Setting Conditions PDVRn0 to 7 = 0 (n = 1, 2, 3, 5, 6, 8, 9, J) Test Conditions VCC = 4.0 to 5.5 V Value Min. Typ. Max. 5.0 Unit mA 0.2 mA PDVRn0 to 7 = 1 (n = 1, 2, 3, 5, 6, 8, 9, J) VCC = 4.0 to 5.5 V 20.0 mA 5.0 mA VCC = 4.0 to 5.5 V 5.0 0.2 0.4 0.2 80 40 mA mA mA mA mA mA VCC = 4.0 to 5.5 V Allowable output high current (total) -IOH All input pins VCC = 4.0 to 5.5 V Rev. 1.00 Oct. 03, 2008 Page 927 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics 28.4 AC Characteristics Table 28.4 AC Characteristics Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC AVCC, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Applicable Symbol Pins OCS1, OSC2 Test Conditions Min. 4.0 Value Typ. Max. 20.0 Unit MHz Reference Figure Item Oscillation frequency of the OSC main oscillator Oscillation frequency of the sub subclock oscillator Oscillation frequency of the loco low-speed on-chip oscillator Oscillation stabilization time trc of the low-speed on-chip oscillator Cycle time of the system reference clock (base) tbase X1, XC 32.768 MHz 25 125 225 kHz T.B.D s 1 1 OSC sub loco hoco tbase * 1 2 Cycle time of the system clock () Cycle time of the instruction Oscillation stabilization time trc (crystal resonator) Oscillation stabilization time trc (ceramic resonator) Oscillation stabilization time trcx External clock high width tCPH OSC1, OSC2 OSC1, OSC2 X1, X2 OSC1 tcyc 1 1 VCC = 4.0 to 20.0 5.5 V 40.0 External clock low width tCPL OSC1 VCC = 4.0 to 20.0 5.5 V 40.0 2 128 244.2 s 6.5 6.5 2.0 tcyc ms ms s ns ns ns ns Figure 28.1 Figure 28.3 Rev. 1.00 Oct. 03, 2008 Page 928 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Item Test Symbol Applicable Pins Conditions OSC1 VCC = 4.0 to 5.5 V Value Min. Min. Min. 10.0 15.0 10.0 15.0 Unit ns ns ns ns ms Reference Figure Figure 28.1 External clock rising time tCPr External clock falling time tCPf OSC1 VCC = 4.0 to 5.5 V RES pin low width tREL1 RES At power-on or T.B.D in mode other than below In active mode T.B.D or sleep mode Figure 28.2 tREL2 Width at high level for input pins tIH NMI IRQ0 to IRQ7 FTIOA to FTIOD, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA2 to FTIOD2, FTIOA3 to FTIOD3, FTCI, TRGC, TRCOI, TRDOI_0, TRDOI_1, TCLKA, TCLKB, TGIOA, TGIOB ms Figure 28.4 T.B.D T.B.D 3 tcyc 2 40* ADTRG, ADTRG_2 3 tcyc Rev. 1.00 Oct. 03, 2008 Page 929 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Item Width at low level for input pins Test Symbol Applicable Pins Conditions tIL NMI IRQ0 to IRQ7 FTIOA to FTIOD, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA2 to FTIOD2, FTIOA3 to FTIOD3, FTCI, TRGC, TRCOI, TRDOI_0, TRDOI_1, TCLKA, TCLKB, TGIOA, TGIOB ADTRG, ADTRG_2 Value Min. Typ. Max. tcyc 40*2 Unit Reference Figure Figure 28.4 T.B.D T.B.D 3 3 tcyc Note: 1. Determined by settings of the system clock control register (SYSCCR), power-down control register 1 (LPCR1), and power-down control register (LPCR2). 2. When the internal 40 clock is selected as the counter clock. Rev. 1.00 Oct. 03, 2008 Page 930 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Table 28.5 Timing of I2C Bus Interface Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC AVCC, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Value Item SCL input cycle time SCL input high width SCL input low width Falling time for SCL and SDA inputs Pulse width of spike on SCL and SD to be suppressed SDA input bus-free time Start condition input hold time Repeated start condition input setup time Stop condition input setup time Data-input setup time Data-input hold time Capacitive load of SCL and SDA Falling time of SCL and SDA outputs Symbol tSCL tSCLH tSCLL tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb tSf Test Conditions Min. 12tcyc + 600 3tcyc + 300 5tcyc + 300 5tcyc 3tcyc 3tcyc 3tcyc 1tcyc + 20 0 0 Vcc = 4.0 to 5.5V Typ. Max. 300 1tcyc 400 250 300 Reference Unit Figure ns ns ns ns ns ns ns ns ns ns ns pF ns ns Figure 28.5 Rev. 1.00 Oct. 03, 2008 Page 931 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Table 28.6 Timing of Serial Communication Interface (SCI) Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC AVCC, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Applicable Test Conditions Symbol Pins Asynchronous tscyc Clock synchronous tSCKW tTXD SCK3 TXD SCK3 Value Min. 4 6 0.4 Vcc = 4.0 to 5.5 V Item Input clock cycle Typ. Max. 0.6 1 1 Unit tcyc tcyc tscyc tcyc tcyc ns ns ns ns Reference Figure Figure 28.6 Input clock pulse width Transmit data delay time (clock synchronous) Receive data setup time (clock synchronous) Receive data hold time (clock synchronous) tRXS RXD Vcc = 4.0 to 5.5 V 50.0 Figure 28.7 100.0 tRXH RXD Vcc = 4.0 to 5.5 V 50.0 100.0 Rev. 1.00 Oct. 03, 2008 Page 932 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Table 28.7 Timing of Synchronous Serial Communication Unit (SSU) Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version), CL = 100 pF Applicable Test Conditions Symbol Pins tSUCYC tHI tLO tRISE SSCK SSCK SSCK SSCK Value Min. 4 0.4 0.4 tFALL SSCK tSU SSO SSI Data input hold time tH SSO SSI SCS setup time SCS hold time Slave Slave tLEAD tLAG tOD SCS SCS SSO SSI Slave access time Slave out release time tSA tOR SSI SSI 1.5tCYC ns + 100 1.5tCYC ns + 100 1tCYC + 50 1tCYC + 50 1 ns ns tCYC 1 tCYC 100 Typ. Max. 0.6 0.6 1 1.0 1 1.0 Unit tCYC tSUCYC tSUCYC tCYC s tCYC s ns Reference Figure Figures 28.8 to 28.12 Item Clock cycle Clock high pulse width Clock low pulse width Clock rising time Master Slave Clock falling time Master Slave Data input setup time Data output delay time Rev. 1.00 Oct. 03, 2008 Page 933 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics 28.5 A/D Converter Characteristics Table 28.8 A/D Converter Characteristics Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = AVSS = 0.0 V, VCC AVCC, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Applicable Test Conditions Symbol Pins AVcc AVIN AVcc AN0 to AN11 AN0_2 to AN3_2 Analog power supply current AIOPE AVcc AVcc = 5.0V fosc = 20MHz AISTOP1 AISTOP2 Analog input capacitance CAIN AVcc AVcc AN0 to AN11 AN0_2 to AN3_2 Permissible signal source impedance RAIN AN0 to AN11 AN0_2 to AN3_2 Resolution (data length) Conversion time A/D conversion mode (single mode) Nonlinearity error Offset error Full-scale error Quantization error Absolute precision tconv AN0 to AN11 AN0_2 to AN3_2 AVcc = 2.7 to 5.5V T.B.D LSB T.B.D LSB T.B.D LSB T.B.D LSB T.B.D LSB 10 2.0 10 10 43 bit s 5.0 k T.B.D A * Reference value 2 Value Min. 2.7 Vss - 0.3 Typ. Vcc Max. 5.5 Avcc + 0.3 Unit V V Remarks * 1 Item Analog power supply voltage Analog input voltage T.B.D mA T.B.D A 30.0 pF * 3 Note: 1. Connect AVcc to Vcc when the A/D converter is not used. Rev. 1.00 Oct. 03, 2008 Page 934 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics 2. AlSTOP1 is the current flowing while the A/D converter is idle and the chip is in active mode or sleep mode. 3. AlSTOP2 is the current flowing while the A/D converter is idle and the chip is in the reset state or in standby mode Rev. 1.00 Oct. 03, 2008 Page 935 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics 28.6 D/A Converter Characteristics Table 28.9 D/A Converter Characteristics Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = AVSS = 0.0 V, VCC AVCC, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Applicable Symbol Pins AVcc AVcc Value Test Conditions Min. 2.7 8 DA0 to DA1 DA0 to DA1 Load resistance = 2M Typ. Vcc 8 Max. 5.5 8 3 Unit V bit s Remarks Item Analog power supply voltage Resolution Conversion time Absolute precision T.B.D LSB Rev. 1.00 Oct. 03, 2008 Page 936 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics 28.7 Flash Memory Characteristics Table 28.10 Flash Memory Characteristics Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC AVSS, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Test Symbol Conditions Target Area Program ROM Data Flash Program ROM Data Flash Program ROM Data Flash Erasing time (per 1-block) Program ROM Data Flash Time for transition to erasesuspend mode Interval from the start of erasing to the request for suspension Interval from the start of erasing to the next request for suspension Interval from suspension to the resumption of erasing Voltage for programming/erasing Reading voltage td(SR-ES) Program ROM Data Flash Program ROM Data Flash Program ROM Data Flash Program ROM Data Flash Program ROM Data Flash Program ROM Data Flash Access states Program ROM Data Flash Programming/erasing temperature Program ROM Data Flash 1 2 0 -20* 3 Value Min. 1000* 2 Item Number of times programming/erasing is 1 performed* Programming time (per 4 bytes) Lock-bit programming time Typ. 2 Max. 50 + CPU clock x 3 states Unit Times 10000* 150 300 70 140 300 300 s s ms s 0 s 150 s 50 s 2.7 5.5 V 2.7 5.5 V 60 85 States C Rev. 1.00 Oct. 03, 2008 Page 937 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Notes: As a means of reducing the effective number of rewriting operations in a system where many rounds of rewriting proceed, go through the possible locations for programming in order until the remaining blank area has been minimized as much as is possible, and only then perform a round of erasure. For example, if data are being programmed in 16-byte sets, the number of effective reprogramming operations can be minimized by erasing once after having programmed the maximum of 256 sets. To retain per-block information on the number of times erasure has been executed, setting up a control number is recommended. If an erase-error occurs during erasure, execute the clear status command and then the erase command at least 3 times until the erase-error not occur. 1. Definition of number of times programming/erasing is performed The indicated number of times is the number of times programming/erasing can be performed per block. When the number of times is n (n = 1000, 10000), each block can be erased n times. Consider the 4-Kbyte blocks of data flash A as an example. When a block is erased after writing to the whole block has been performed by writing 4-byte units to the respective locations 1024 times, this counts as programming/erasure once. However, writing to a given address more than once after having erased the block is not possible (rewriting of values is prohibited). 2. This is the number of times for which all electrical characteristics can be guaranteed. (i.e. the values are guaranteed while the number of times is within the range from one to the minimum value.) 3. This becomes -40C for the D version. Rev. 1.00 Oct. 03, 2008 Page 938 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics 28.8 Electrical Characteristics for Low-Voltage Detection Circuits Table 28.11 Electrical Characteristics for Low-Voltage Detection Circuit 0 Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC AVCC, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Value Item Voltage-detection level Symbol Vdet0 Test Conditions VD0LS1 = 0 VD0LS1 = 1 Minimum value of operating voltage for low-voltage detection circuit 0 VLVDR0min Min. T.B.D T.B.D 1.8 Typ. 2.35 3.80 Max. T.B.D T.B.D V Unit V Rev. 1.00 Oct. 03, 2008 Page 939 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Table 28.12 Electrical Characteristics for Low-Voltage Detection Circuit 1 Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC AVCC, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Value Item Voltage-detection level Symbol Vdet1 Test Conditions VD1LS[3:0] = 0101 VD1LS[3:0] = 0110 VD1LS[3:0] = 0111 VD1LS[3:0] = 1000 VD1LS[3:0] = 1001 VD1LS[3:0] = 1010 VD1LS[3:0] = 1011 VD1LS[3:0] = 1100 VD1LS[3:0] = 1101 VD1LS[3:0] = 1110 VD1LS[3:0] = 1111 Voltage hysteresis between detection for rising and falling cases Current drawn by low-voltage detection circuit 1 VLVD1HYS Min. Typ. Max. T.B.D Unit V Falling voltage T.B.D 2.85 Rising voltage 3.07 Falling voltage T.B.D 2.92 Rising voltage 3.15 Falling voltage T.B.D 3.07 Rising voltage 3.30 Falling voltage T.B.D 3.22 Rising voltage 3.45 Falling voltage T.B.D 3.37 Rising voltage 3.60 Falling voltage T.B.D 3.52 Rising voltage 3.75 Falling voltage T.B.D 3.67 Rising voltage 3.90 Falling voltage T.B.D 3.82 Rising voltage 4.05 Falling voltage T.B.D 3.97 Rising voltage 4.20 Falling voltage T.B.D 4.12 Rising voltage 4.35 Falling voltage T.B.D 4.27 Rising voltage 4.50 0.22 T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D T.B.D V Vcc = 5.0V T.B.D A Rev. 1.00 Oct. 03, 2008 Page 940 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Value Item Time to wait for low-voltage detection circuit 1 to start operating Minimum value of operating voltage for low-voltage detection circuit 1 Symbol td(E-A) Test Conditions Min. Typ. Max. T.B.D Unit s VLVDR1min 2.7 V Table 28.13 Electrical Characteristics for Low-Voltage Detection Circuit 2 Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC AVCC, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Value Item Voltage-detection level Current drawn by low-voltage detection circuit 1 Time to wait for low-voltage detection circuit 1 to start operating Voltage-detection level for external input pins Range of input for voltage-detection of external inputs Range of input for comparison voltage for external inputs td(E-A) Symbol Vdet2 Test Conditions Rising voltage Falling voltage Vcc = 5.0V Min. 2.04 T.B.D 0 0 Typ. 2.14 T.B.D 1.33 Max. 2.24 T.B.D T.B.D 1/2Vcc 1/2Vcc V V Unit V A s Rev. 1.00 Oct. 03, 2008 Page 941 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics 28.9 Electrical Characteristics for Power-On Reset Function Table 28.14 Characteristics for Power-On Reset Function Unless otherwise indicated, VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC AVCC, Ta = -20 to +85 C (N version)/ -40 to +85 C (D version) Test Conditions Min. 0 0.5 Value Typ. Max. Vdet0 T.B.D Unit V V/msec Reference Figure Figure 28.13 Item Voltage where the power-on reset signal becomes effective Slope of rise for external power supply Vcc Symbol Vpor trth Rev. 1.00 Oct. 03, 2008 Page 942 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics 28.10 Timing Charts tOSC OSC1 VIH VIL tCPH tCPr tCPL tCPf Figure 28.1 System Clock Input Timing Vcc Vccx0.7 Low-speed OCO tREL1 RES VIL VIL tREL2 Figure 28.2 Timing of RES Pin Low Width Rev. 1.00 Oct. 03, 2008 Page 943 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics * When switching the clock VCC osc base Oscillation settling time trc Switch the clock source to osc. * When canceling standby mode VCC osc base In standby mode Oscillation settling time trc Standby mode canceling trigger Figure 28.3 Timing of Oscillation Settling Time Rev. 1.00 Oct. 03, 2008 Page 944 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics NMI, IRQ0 to IRQ7, ADTRG, ADTRG_2, FTIOA to FTIOD, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA2 to FTIOD2, FTIOA3 to FTIOD3, TCLKA, TCLKB, FTCI, TGIOA , TRGC, TGIOB, TRCOI, TRDOI_0, TRDOI_1 tIL tIH VIH VIL Figure 28.4 Input Timing SDA tBUF VIH VIL tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf tSCLL tSCL Sr* tSr tSDAH tSDAS P* Notes: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Repeated start condition Figure 28.5 Timing of I2C Bus Interface Input/Output Rev. 1.00 Oct. 03, 2008 Page 945 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics tSCKW SCK3 tscyc Figure 28.6 SCK3 Input Clock Timing tscyc VIH or VOH* VIL or VOL* tTXD VOH* VOL* tRXS SCK3 TXD (transmit data) tRXH RXD (receive data) Note: * Output timing referenced levels Output high Output low VOH = 2.0V VOL = 0.8V For load conditions, see figure 28.14. Figure 28.7 SCI Input/Output Timing in Clock Synchronous Mode Rev. 1.00 Oct. 03, 2008 Page 946 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics tHI SSCK VIH or VOH VIH or VOH tLO tSUCYC SSO (Output) tOD SSI (Input) tSU tH Figure 28.8 SSU Input Timing in Clock Synchronous Mode VIH or VOH VIH or VOH tHI SSCK (Output) CPOS = 1 tLO tHI SSCK (Output) CPOS = 0 tLO SSO (Output) tOD SSI (Input) tSU tH tSUCYC tFALL tRISE SCS (Output) Figure 28.9 SSU Input/Output Timing (Four-Line Bus Communication Mode, Master, CPHS = 1) Rev. 1.00 Oct. 03, 2008 Page 947 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics SCS (Output) VIH or VOH VIH or VOH tHI tFALL tRISE SSCK (Output) CPOS = 1 tLO tHI SSCK (Output) CPOS = 0 tLO SSO (Output) tOD SSI (Input) tSU tH tSUCYC Figure 28.10 SSU Input/Output Timing (Four-Line Bus Communication Mode, Master, CPHS = 0) Rev. 1.00 Oct. 03, 2008 Page 948 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics SCS (Input) VIH or VOH VIH or VOH tLEAD tHI tFALL tRISE tLAG SSCK (Input) CPOS = 1 tLO tHI SSCK (Input) CPOS = 0 tLO SSO (Input) tSU SSI (Output) tOD tOR tSUCYC tH tSA Figure 28.11 SSU Input/Output Timing (Four-Line Bus Communication Mode, Slave, CPHS = 1) Rev. 1.00 Oct. 03, 2008 Page 949 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics SCS (Input) VIH or VOH VIH or VOH tLEAD tHI tFALL tRISE tLAG SSCK (Input) CPOS = 1 tLO tHI SSCK (Input) CPOS = 0 tLO SSO (Input) tSU SSI (Output) tSA tOD tOD tSUCYC tH Figure 28.12 SSU Input/Output Timing (Four-Line Bus Communication Mode, Slave, CPHS = 0) Vdet0 External power supply VCC Vpor Sampling time* trth 1.8V trth Vdet0 Internal reset signal ("L" enabled) 1 loco x 128 1 loco x 32 Note: * When a digital filter is used on LVD, the voltage must be at or above 1.8 V over the sampling period. Figure 28.13 Timing of Power-On Reset Rev. 1.00 Oct. 03, 2008 Page 950 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics 28.11 Output Load Circuit Vcc 2.4k LSI output pin 30pF 12k Figure 28.14 Output Load Circuit Rev. 1.00 Oct. 03, 2008 Page 951 of 962 REJ09B0465-0100 Section 28 Electrical Characteristics Rev. 1.00 Oct. 03, 2008 Page 952 of 962 REJ09B0465-0100 Appendix Appendix A. Package Dimensions RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g JEITA Package Code P-LQFP64-10x10-0.50 HD *1 48 D 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 HE E Reference Dimension in Millimeters Symbol 49 32 *2 c1 c 64 1 Index mark ZD 16 ZE 17 Terminal cross section F A2 A D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 e *3 A1 y bp L L1 Detail F x Min Nom Max 9.9 10.0 10.1 9.9 10.0 10.1 1.4 11.8 12.0 12.2 11.8 12.0 12.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.25 1.25 0.35 0.5 0.65 1.0 Figure A.1 Package Dimension (PLQP0064KB-A) Rev. 1.00 Oct. 03, 2008 Page 953 of 962 REJ09B0465-0100 c Appendix JEITA Package Code P-LQFP64-14x14-0.80 RENESAS Code PLQP0064GA-A Previous Code 64P6U-A MASS[Typ.] 0.7g HD *1 D 48 33 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 49 32 bp b1 c1 HE E c Reference Dimension in Millimeters Symbol *2 Terminal cross section 64 17 1 ZD Index mark 16 A A2 F L L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 y e *3 bp x Detail F Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0 8 0.8 0.20 0.10 1.0 1.0 0.3 0.5 0.7 1.0 ZE Figure A.2 Package Dimension (PLQP0064GA-A) Rev. 1.00 Oct. 03, 2008 Page 954 of 962 REJ09B0465-0100 A1 c Appendix JEITA Package Code P-LQFP80-14x14-0.65 RENESAS Code PLQP0080JA-A Previous Code FP-80W / FP-80WV MASS[Typ.] 0.6g HD *1 D 41 60 61 40 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp HE E b1 Reference Dimension in Millimeters Symbol *2 c1 c 80 21 1 ZD Index mark 20 ZE Terminal cross section A2 A F A1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 L y e *3 L1 bp Detail F x Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.27 0.32 0.37 0.30 0.09 0.145 0.20 0.125 0 8 0.65 0.13 0.10 0.825 0.825 0.35 0.5 0.65 1.0 Figure A.3 Package Dimension (PLQP0080JA-A) Rev. 1.00 Oct. 03, 2008 Page 955 of 962 REJ09B0465-0100 c Appendix JEITA Package Code P-LQFP80-12x12-0.50 RENESAS Code PLQP0080KB-A Previous Code 80P6Q-A MASS[Typ.] 0.5g HD *1 D 60 41 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 61 40 bp b1 c1 *2 HE E c Reference Dimension in Millimeters Symbol Terminal cross section ZE 80 21 1 ZD Index mark 20 F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 y e bp A1 *3 x L1 L Detail F Min Nom Max 11.9 12.0 12.1 11.9 12.0 12.1 1.4 13.8 14.0 14.2 13.8 14.0 14.2 1.7 0.1 0.2 0 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 10 0.5 0.08 0.08 1.25 1.25 0.3 0.5 0.7 1.0 A2 A Figure A.4 Package Dimension (PLQP0080KB-A) Rev. 1.00 Oct. 03, 2008 Page 956 of 962 REJ09B0465-0100 c Appendix B. Handling of Unused Pins Table B.1 shows the handling of unused pins. Table B.1 Pin Name RES NMI X1 X2 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port J NC Leave this pin open Handling of Unused Pins Example of Handling Pins Connect this pin to VCC via a pull-up resister Connect this pin to VCC via a pull-up resister Connect this pin to VSS Leave this pin open Set the corresponding PMR bit or the PCR bit to 0 to set these pins in general purpose mode. Connect these pins to VCC via a resister (pull-up) or to VSS via a resister (pull-down), respectively. Rev. 1.00 Oct. 03, 2008 Page 957 of 962 REJ09B0465-0100 Appendix Rev. 1.00 Oct. 03, 2008 Page 958 of 962 REJ09B0465-0100 Index A A/D conversion time............................... 841 A/D Converter ........................................ 817 Absolute Address...................................... 54 Acknowledge .......................................... 748 Activation by Software ................... 355, 359 Addressing Mode...................................... 53 ADI ......................................................... 844 Advanced Mode........................................ 24 Arithmetic Operations Instructions..... 43, 44 D Data Transfer Controller (DTC).............. 331 Data Transfer Instructions......................... 42 Digital filter includes ...................... 477, 662 DTC Vector Table................................... 344 E Effective Address...................................... 53 effective address extension ....................... 51 Effective Address Extension..................... 51 Exception Handling .................................. 63 Extended Control Register (EXR) ............ 33 External Trigger ...................................... 843 B Bit Manipulation Instructions ............. 47, 48 Bit synchronous circuit ........................... 765 Block Data Transfer Instruction ............... 51 Block Transfer Mode.............................. 353 Branch Instructions................................... 49 Buffer operation...................................... 573 G General Registers ...................................... 32 C Chain Transfer ........................................ 354 Chain Transfer when Counter = 0........... 361 Clock polarity ......................................... 780 Clock synchronous serial format ............ 756 Clocked synchronous communication mode ....................................................... 784 Communication mode............................. 783 Complementary PWM mode .................. 561 Condition Field ......................................... 51 Condition-Code Register .......................... 34 CPU Operating Modes.............................. 24 I I/O ports .................................................. 267 I2C bus format ......................................... 747 I2C bus interface 2 (IIC2)........................ 729 Immediate ................................................. 55 Initial setting procedure .......................... 618 Input capture function ............................. 547 Instruction Set ........................................... 40 Interrupt Control Modes............................ 96 Interrupt Exception Handling.................... 70 Interrupt Exception Handling Vector Table ......................................................... 89 Interrupt Priority Register (IPR) ............... 73 Interrupt Request Mask Level................... 33 Rev. 1.00 Oct. 03, 2008 Page 959 of 962 REJ09B0465-0100 L Logic Operations Instructions................... 45 M Memory Indirect....................................... 56 N NMI ........................................................ 104 NMI Interrupt ........................................... 87 Noise canceler ........................................ 759 Normal Mode.......................................... 351 O Operation Field......................................... 51 P Pin functions............................................. 14 Program Counter ...................................... 33 Program-Counter Relative ........................ 55 PWM mode..................................... 466, 551 PWM2 mode........................................... 471 R Register Direct.......................................... 53 Register Field............................................ 51 Register Indirect ....................................... 53 Register Indirect with Displacement......... 54 Register Indirect with Post-Increment ...... 54 Register indirect with pre-decrement........ 54 Register Information............................... 344 Registers ADCR..........................825, 827, 828, 832 ADCSR............................................... 823 ADDR................................................. 822 Rev. 1.00 Oct. 03, 2008 Page 960 of 962 REJ09B0465-0100 BRR .................................................... 690 CRA .................................................... 338 CRB .................................................... 338 DACR ................................................. 853 DADR ................................................. 852 DAR.................................................... 337 DTCER ............................................... 339 DTVECR ............................................ 341 ELCSR.................................................. 86 GRA............................................ 457, 517 GRB ............................................ 457, 517 GRC ............................................ 457, 517 GRD............................................ 457, 517 ICCR1 ......................................... 733, 736 ICDRR ................................................ 746 ICDRS................................................. 746 ICDRT ................................................ 745 ICIER.................................................. 739 ICMR .................................................. 738 ICSR ................................................... 741 IER........................................................ 79 INCCR .................................................. 84 INTCR .................................................. 76 IPR ........................................................ 77 IrCR .................................................... 695 ISCR ..................................................... 80 ISR ........................................................ 83 LD0CRH............................................. 868 LD0CRL ............................................. 869 LD1CRH............................................. 865 LD1CRL ............................................. 867 LD2CRH............................................. 862 LD2CRL ............................................. 864 MRA ................................................... 334 MRB ................................................... 336 PCR............ 269, 275, 281, 287, 293, 299, .................... 305, 311, 315, 319, 323, 328 PDR.................... 270, 276, 282, 288, 294, ............................ 300, 306, 312, 320, 329 PMR....................268, 274, 280, 286, 292, .....................298, 304, 310, 314, 318, 327 POCR.................................................. 529 RDR.................................................... 683 RSR..................................................... 683 SAR ............................................ 337, 745 SCR3................................................... 686 SMR.................................................... 684 SPMR ................................................. 695 SSCRH ............................................... 770 SSCRL................................................ 771 SSER................................................... 776 SSMR ................................................. 773 SSMR2 ............................................... 774 SSR ..................................................... 688 SSRDR ............................................... 779 SSSR................................................... 777 SSTDR................................................ 779 TDR .................................................... 684 TRCCNT ............................................ 456 TRCCR2 ............................................. 444 TRCDF ............................................... 454 TRCIER.............................................. 445 TRCIOR0............................................ 449 TRCIOR1............................................ 451 TRCMR .............................................. 441 TRCOER ............................................ 453 TRCSR ............................................... 446 TRDCNT ............................................ 516 TRDCR............................................... 519 TRDDF ............................................... 530 TRDFCR............................................. 509 TRDIER.............................................. 528 TRDIORA .......................................... 521 TRDIORC........................................... 521 TRDMDR ........................................... 507 TRDOCR............................................ 513 TRDOER1 .......................................... 511 TRDOER2 .......................................... 513 TRDPMR............................................ 508 TRDSR................................................ 525 TRDSTR ............................................. 505 VOFR.................................................... 85 Repeat Mode ........................................... 352 Reset ......................................................... 64 Reset exception handling .......................... 67 Reset synchronous PWM mode .............. 557 S Scan Mode ...................................... 837, 840 Shift Instructions....................................... 46 Single Mode.................................... 835, 839 Slave address........................................... 747 Software Activation ................................ 363 Stack Pointer (SP) ..................................... 32 Stack Status after Exception Handling...... 71 Start condition......................................... 747 Stop condition ......................................... 748 SWDTEND............................................. 355 Synchronous operation............................ 550 Synchronous serial communication unit (SSU) ............................................... 767 System Control Instruction ....................... 50 T Timer RC ................................................ 437 Timer RD ................................................ 495 Trace Bit ................................................... 33 Trace Exception Handling ........................ 69 Transfer clock ......................................... 780 Transfer rate............................................ 735 Trap Instruction Exception Handling........ 70 TRAPA ..................................................... 55 TRAPA instruction ................................... 70 Rev. 1.00 Oct. 03, 2008 Page 961 of 962 REJ09B0465-0100 V Vector number for the software activation interrupt.................................. 341 W Waveform output by compare match...... 544 Rev. 1.00 Oct. 03, 2008 Page 962 of 962 REJ09B0465-0100 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/20103, H8S/20203, H8S/20223 Group Publication Date: Rev.1.00, Oct. 03, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.2 H8S/20103, H8S/20203, H8S/20223 Group Hardware Manual |
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